
#ifndef _AT91SAMA5_
#define _AT91SAMA5_

/** \addtogroup AT91SAMA5_definitions AT91SAMA5 definitions
  This file defines all structures and symbols for AT91SAMA5:
    - registers and bitfields
    - peripheral base address
    - peripheral ID
    - PIO definitions
*/
/*@{*/

#ifdef __cplusplus
 extern "C" {
#endif

#ifndef __ASSEMBLY__
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
#else
typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
#endif
typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
#endif

typedef enum IRQn
{
  FIQ_IRQn             =  0, /**<  0 AT91SAMA5 Advanced Interrupt Controller (FIQ) */
  SYS_IRQn             =  1, /**<  1 AT91SAMA5 System Controller Interrupt (SYS) */
  DBGU_IRQn            =  2, /**<  2 AT91SAMA5 Debug Unit Interrupt (DBGU) */
  PIT_IRQn             =  3, /**<  3 AT91SAMA5 Periodic Interval Timer Interrupt (PIT) */
  WDT_IRQn             =  4, /**<  4 AT91SAMA5 Watchdog timer Interrupt (WDT) */
  SMC_IRQn             =  5, /**<  5 AT91SAMA5 Multi-bit ECC Interrupt (SMC) */
  PIOA_IRQn            =  6, /**<  6 AT91SAMA5 Parallel I/O Controller A (PIOA) */
  PIOB_IRQn            =  7, /**<  7 AT91SAMA5 Parallel I/O Controller B (PIOB) */
  PIOC_IRQn            =  8, /**<  8 AT91SAMA5 Parallel I/O Controller C (PIOC) */
  PIOD_IRQn            =  9, /**<  9 AT91SAMA5 Parallel I/O Controller D (PIOD) */
  PIOE_IRQn            = 10, /**< 10 AT91SAMA5 Parallel I/O Controller E (PIOE) */
  SMD_IRQn             = 11, /**< 11 AT91SAMA5 SMD Soft Modem (SMD) */
  USART0_IRQn          = 12, /**< 12 AT91SAMA5 USART 0 (USART0) */
  USART1_IRQn          = 13, /**< 13 AT91SAMA5 USART 1 (USART1) */
  USART2_IRQn          = 14, /**< 14 AT91SAMA5 USART 2 (USART2) */
  USART3_IRQn          = 15, /**< 15 AT91SAMA5 USART 3 (USART3) */
  UART0_IRQn           = 16, /**< 16 AT91SAMA5 UART 0 (UART0) */
  UART1_IRQn           = 17, /**< 17 AT91SAMA5 UART 1 (UART1) */
  TWI0_IRQn            = 18, /**< 18 AT91SAMA5 Two-Wire Interface 0 (TWI0) */
  TWI1_IRQn            = 19, /**< 19 AT91SAMA5 Two-Wire Interface 1 (TWI1) */
  TWI2_IRQn            = 20, /**< 20 AT91SAMA5 Two-Wire Interface 2 (TWI2) */
  HSMCI0_IRQn          = 21, /**< 21 AT91SAMA5 High Speed Multimedia Card Interface 0 (HSMCI0) */
  HSMCI1_IRQn          = 22, /**< 22 AT91SAMA5 High Speed Multimedia Card Interface 1 (HSMCI1) */
  HSMCI2_IRQn          = 23, /**< 23 AT91SAMA5 High Speed Multimedia Card Interface 2 (HSMCI2) */
  SPI0_IRQn            = 24, /**< 24 AT91SAMA5 Serial Peripheral Interface 0 (SPI0) */
  SPI1_IRQn            = 25, /**< 25 AT91SAMA5 Serial Peripheral Interface 1 (SPI1) */
  TC0_IRQn             = 26, /**< 26 AT91SAMA5 Timer Counter 0 (ch. 0, 1, 2) (TC0) */
  TC1_IRQn             = 27, /**< 27 AT91SAMA5 Timer Counter 1 (ch. 3, 4, 5) (TC1) */
  PWM_IRQn             = 28, /**< 28 AT91SAMA5 Pulse Width Modulation Controller (PWM) */
  ADC_IRQn             = 29, /**< 29 AT91SAMA5 Touch Screen ADC Controller (ADC) */
  DMAC0_IRQn           = 30, /**< 30 AT91SAMA5 DMA Controller 0 (DMAC0) */
  DMAC1_IRQn           = 31, /**< 31 AT91SAMA5 DMA Controller 1 (DMAC1) */
  UHPHS_IRQn           = 32, /**< 32 AT91SAMA5 USB Host High Speed (UHPHS) */
  UDPHS_IRQn           = 33, /**< 33 AT91SAMA5 USB Device High Speed (UDPHS) */
  GMAC_IRQn            = 34, /**< 34 AT91SAMA5 Gigabit Ethernet MAC (GMAC) */
  EMAC_IRQn            = 35, /**< 35 AT91SAMA5 Ethernet MAC (EMAC) */
  LCDC_IRQn            = 36, /**< 36 AT91SAMA5 LCD Controller (LCDC) */
  ISI_IRQn             = 37, /**< 37 AT91SAMA5 Image Sensor Interface (ISI) */
  SSC0_IRQn            = 38, /**< 38 AT91SAMA5 Synchronous Serial Controller 0 (SSC0) */
  SSC1_IRQn            = 39, /**< 39 AT91SAMA5 Synchronous Serial Controller 1 (SSC1) */
  CAN0_IRQn            = 40, /**< 40 AT91SAMA5 CAN controller 0 (CAN0) */
  CAN1_IRQn            = 41, /**< 41 AT91SAMA5 CAN controller 1 (CAN1) */
  SHA_IRQn             = 42, /**< 42 AT91SAMA5 Secure Hash Algorithm (SHA) */
  AES_IRQn             = 43, /**< 43 AT91SAMA5 Advanced Encryption Standard (AES) */
  TDES_IRQn            = 44, /**< 44 AT91SAMA5 Triple Data EncryptionStandard (TDES) */
  TRNG_IRQn            = 45, /**< 45 AT91SAMA5 True Random Number Generator (TRNG) */
  ARM_IRQn             = 46, /**< 46 AT91SAMA5 Performance Monitor Unit (ARM) */
  IRQ_IRQn             = 47, /**< 47 AT91SAMA5 Advanced Interrupt Controller (IRQ) */
  FUSE_IRQn            = 48, /**< 48 AT91SAMA5 Fuse Controller (FUSE) */
  MPDDRC_IRQn          = 49  /**< 49 AT91SAMA5 MPDDR controller (MPDDRC) */
} IRQn_Type;

/* ************************************************************************** */
/**  SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAMA5 */
/* ************************************************************************** */
/** \addtogroup AT91SAMA5_api Peripheral Software API */
/*@{*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_ADC Analog-to-digital Converter */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Adc hardware registers */
typedef struct {
  WoReg ADC_CR;       /**< \brief (Adc Offset: 0x00) Control Register */
  RwReg ADC_MR;       /**< \brief (Adc Offset: 0x04) Mode Register */
  RwReg ADC_SEQR1;    /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
  RwReg ADC_SEQR2;    /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
  WoReg ADC_CHER;     /**< \brief (Adc Offset: 0x10) Channel Enable Register */
  WoReg ADC_CHDR;     /**< \brief (Adc Offset: 0x14) Channel Disable Register */
  RoReg ADC_CHSR;     /**< \brief (Adc Offset: 0x18) Channel Status Register */
  RoReg Reserved1[1];
  RoReg ADC_LCDR;     /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
  WoReg ADC_IER;      /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
  WoReg ADC_IDR;      /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
  RoReg ADC_IMR;      /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
  RoReg ADC_ISR;      /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
  RoReg Reserved2[2];
  RoReg ADC_OVER;     /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
  RwReg ADC_EMR;      /**< \brief (Adc Offset: 0x40) Extended Mode Register */
  RwReg ADC_CWR;      /**< \brief (Adc Offset: 0x44) Compare Window Register */
  RwReg ADC_CGR;      /**< \brief (Adc Offset: 0x48) Channel Gain Register */
  RwReg ADC_COR;      /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
  RoReg ADC_CDR[12];  /**< \brief (Adc Offset: 0x50) Channel Data Register */
  RoReg Reserved3[5];
  RwReg ADC_ACR;      /**< \brief (Adc Offset: 0x94) Analog Control Register */
  RoReg Reserved4[6];
  RwReg ADC_TSMR;     /**< \brief (Adc Offset: 0xB0) Touchscreen Mode Register */
  RoReg ADC_XPOSR;    /**< \brief (Adc Offset: 0xB4) Touchscreen X Position Register */
  RoReg ADC_YPOSR;    /**< \brief (Adc Offset: 0xB8) Touchscreen Y Position Register */
  RoReg ADC_PRESSR;   /**< \brief (Adc Offset: 0xBC) Touchscreen Pressure Register */
  RwReg ADC_TRGR;     /**< \brief (Adc Offset: 0xC0) Trigger Register */
  RoReg Reserved5[8];
  RwReg ADC_WPMR;     /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
  RoReg ADC_WPSR;     /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
} Adc;
#endif /* __ASSEMBLY__ */
/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
#define ADC_CR_AUTOCAL (0x1u << 3) /**< \brief (ADC_CR) Automatic Calibration of ADC */
/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
#define ADC_SEQR1_USCH1_Pos 0
#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
#define ADC_SEQR1_USCH2_Pos 4
#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
#define ADC_SEQR1_USCH3_Pos 8
#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
#define ADC_SEQR1_USCH4_Pos 12
#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
#define ADC_SEQR1_USCH5_Pos 16
#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
#define ADC_SEQR1_USCH6_Pos 20
#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
#define ADC_SEQR1_USCH7_Pos 24
#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
#define ADC_SEQR1_USCH8_Pos 28
#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
#define ADC_SEQR2_USCH9_Pos 0
#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
#define ADC_SEQR2_USCH10_Pos 4
#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
#define ADC_SEQR2_USCH11_Pos 8
#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
#define ADC_SEQR2_USCH12_Pos 12
#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
#define ADC_SEQR2_USCH13_Pos 16
#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
#define ADC_SEQR2_USCH14_Pos 20
#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
#define ADC_SEQR2_USCH15_Pos 24
#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
#define ADC_SEQR2_USCH16_Pos 28
#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
#define ADC_LCDR_LDATA_Pos 0
#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
#define ADC_LCDR_CHNB_Pos 12
#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
#define ADC_IER_XRDY (0x1u << 20) /**< \brief (ADC_IER) Touchscreen Measure XPOS Ready Interrupt Enable */
#define ADC_IER_YRDY (0x1u << 21) /**< \brief (ADC_IER) Touchscreen Measure YPOS Ready Interrupt Enable */
#define ADC_IER_PRDY (0x1u << 22) /**< \brief (ADC_IER) Touchscreen Measure Pressure Ready Interrupt Enable */
#define ADC_IER_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Calibration Sequence */
#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
#define ADC_IER_PEN (0x1u << 29) /**< \brief (ADC_IER) Pen Contact Interrupt Enable */
#define ADC_IER_NOPEN (0x1u << 30) /**< \brief (ADC_IER) No Pen Contact Interrupt Enable */
/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
#define ADC_IDR_XRDY (0x1u << 20) /**< \brief (ADC_IDR) Touchscreen Measure XPOS Ready Interrupt Disable */
#define ADC_IDR_YRDY (0x1u << 21) /**< \brief (ADC_IDR) Touchscreen Measure YPOS Ready Interrupt Disable */
#define ADC_IDR_PRDY (0x1u << 22) /**< \brief (ADC_IDR) Touchscreen Measure Pressure Ready Interrupt Disable */
#define ADC_IDR_EOCAL (0x1u << 23) /**< \brief (ADC_IDR) End of Calibration Sequence */
#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
#define ADC_IDR_PEN (0x1u << 29) /**< \brief (ADC_IDR) Pen Contact Interrupt Disable */
#define ADC_IDR_NOPEN (0x1u << 30) /**< \brief (ADC_IDR) No Pen Contact Interrupt Disable */
/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
#define ADC_IMR_XRDY (0x1u << 20) /**< \brief (ADC_IMR) Touchscreen Measure XPOS Ready Interrupt Mask */
#define ADC_IMR_YRDY (0x1u << 21) /**< \brief (ADC_IMR) Touchscreen Measure YPOS Ready Interrupt Mask */
#define ADC_IMR_PRDY (0x1u << 22) /**< \brief (ADC_IMR) Touchscreen Measure Pressure Ready Interrupt Mask */
#define ADC_IMR_EOCAL (0x1u << 23) /**< \brief (ADC_IMR) End of Calibration Sequence */
#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
#define ADC_IMR_PEN (0x1u << 29) /**< \brief (ADC_IMR) Pen Contact Interrupt Mask */
#define ADC_IMR_NOPEN (0x1u << 30) /**< \brief (ADC_IMR) No Pen Contact Interrupt Mask */
/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
#define ADC_ISR_XRDY (0x1u << 20) /**< \brief (ADC_ISR) Touchscreen XPOS Measure Ready */
#define ADC_ISR_YRDY (0x1u << 21) /**< \brief (ADC_ISR) Touchscreen YPOS Measure Ready */
#define ADC_ISR_PRDY (0x1u << 22) /**< \brief (ADC_ISR) Touchscreen Pressure Measure Ready */
#define ADC_ISR_EOCAL (0x1u << 23) /**< \brief (ADC_ISR) End of Calibration Sequence */
#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
#define ADC_ISR_PEN (0x1u << 29) /**< \brief (ADC_ISR) Pen contact */
#define ADC_ISR_NOPEN (0x1u << 30) /**< \brief (ADC_ISR) No Pen contact */
#define ADC_ISR_PENS (0x1u << 31) /**< \brief (ADC_ISR) Pen detect Status */
/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
#define ADC_EMR_CMPMODE_Pos 0
#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
#define ADC_EMR_CMPSEL_Pos 4
#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
#define ADC_EMR_CMPFILTER_Pos 12
#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */
#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))
#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
#define ADC_CWR_LOWTHRES_Pos 0
#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
#define ADC_CWR_HIGHTHRES_Pos 16
#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
#define ADC_CGR_GAIN0_Pos 0
#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */
#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
#define ADC_CGR_GAIN1_Pos 2
#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */
#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
#define ADC_CGR_GAIN2_Pos 4
#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */
#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
#define ADC_CGR_GAIN3_Pos 6
#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */
#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
#define ADC_CGR_GAIN4_Pos 8
#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */
#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
#define ADC_CGR_GAIN5_Pos 10
#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */
#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
#define ADC_CGR_GAIN6_Pos 12
#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */
#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
#define ADC_CGR_GAIN7_Pos 14
#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */
#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
#define ADC_CGR_GAIN8_Pos 16
#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */
#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
#define ADC_CGR_GAIN9_Pos 18
#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */
#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
#define ADC_CGR_GAIN10_Pos 20
#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */
#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
#define ADC_CGR_GAIN11_Pos 22
#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */
#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */
#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */
#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */
#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */
#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */
#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */
#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */
#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */
#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */
#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */
#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */
#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */
#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
/* -------- ADC_CDR[12] : (ADC Offset: 0x50) Channel Data Register -------- */
#define ADC_CDR_DATA_Pos 0
#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[12]) Converted Data */
/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
#define ADC_ACR_PENDETSENS_Pos 0
#define ADC_ACR_PENDETSENS_Msk (0x3u << ADC_ACR_PENDETSENS_Pos) /**< \brief (ADC_ACR) Pen Detection Sensitivity */
#define ADC_ACR_PENDETSENS(value) ((ADC_ACR_PENDETSENS_Msk & ((value) << ADC_ACR_PENDETSENS_Pos)))
#define ADC_ACR_IBCTL_Pos 8
#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
/* -------- ADC_TSMR : (ADC Offset: 0xB0) Touchscreen Mode Register -------- */
#define ADC_TSMR_TSMODE_Pos 0
#define ADC_TSMR_TSMODE_Msk (0x3u << ADC_TSMR_TSMODE_Pos) /**< \brief (ADC_TSMR) Touchscreen Mode */
#define   ADC_TSMR_TSMODE_NONE (0x0u << 0) /**< \brief (ADC_TSMR) No Touchscreen */
#define   ADC_TSMR_TSMODE_4_WIRE_NO_PM (0x1u << 0) /**< \brief (ADC_TSMR) 4-wire Touchscreen without pressure measurement */
#define   ADC_TSMR_TSMODE_4_WIRE (0x2u << 0) /**< \brief (ADC_TSMR) 4-wire Touchscreen with pressure measurement */
#define   ADC_TSMR_TSMODE_5_WIRE (0x3u << 0) /**< \brief (ADC_TSMR) 5-wire Touchscreen */
#define ADC_TSMR_TSAV_Pos 4
#define ADC_TSMR_TSAV_Msk (0x3u << ADC_TSMR_TSAV_Pos) /**< \brief (ADC_TSMR) Touchscreen Average */
#define   ADC_TSMR_TSAV_NO_FILTER (0x0u << 4) /**< \brief (ADC_TSMR) No Filtering. Only one ADC conversion per measure */
#define   ADC_TSMR_TSAV_AVG2CONV (0x1u << 4) /**< \brief (ADC_TSMR) Averages 2 ADC conversions */
#define   ADC_TSMR_TSAV_AVG4CONV (0x2u << 4) /**< \brief (ADC_TSMR) Averages 4 ADC conversions */
#define   ADC_TSMR_TSAV_AVG8CONV (0x3u << 4) /**< \brief (ADC_TSMR) Averages 8 ADC conversions */
#define ADC_TSMR_TSFREQ_Pos 8
#define ADC_TSMR_TSFREQ_Msk (0xfu << ADC_TSMR_TSFREQ_Pos) /**< \brief (ADC_TSMR) Touchscreen Frequency */
#define ADC_TSMR_TSFREQ(value) ((ADC_TSMR_TSFREQ_Msk & ((value) << ADC_TSMR_TSFREQ_Pos)))
#define ADC_TSMR_TSSCTIM_Pos 16
#define ADC_TSMR_TSSCTIM_Msk (0xfu << ADC_TSMR_TSSCTIM_Pos) /**< \brief (ADC_TSMR) Touchscreen Switches Closure Time */
#define ADC_TSMR_TSSCTIM(value) ((ADC_TSMR_TSSCTIM_Msk & ((value) << ADC_TSMR_TSSCTIM_Pos)))
#define ADC_TSMR_NOTSDMA (0x1u << 22) /**< \brief (ADC_TSMR) No TouchScreen DMA */
#define ADC_TSMR_PENDET (0x1u << 24) /**< \brief (ADC_TSMR) Pen Contact Detection Enable */
#define ADC_TSMR_PENDBC_Pos 28
#define ADC_TSMR_PENDBC_Msk (0xfu << ADC_TSMR_PENDBC_Pos) /**< \brief (ADC_TSMR) Pen Detect Debouncing Period */
#define ADC_TSMR_PENDBC(value) ((ADC_TSMR_PENDBC_Msk & ((value) << ADC_TSMR_PENDBC_Pos)))
/* -------- ADC_XPOSR : (ADC Offset: 0xB4) Touchscreen X Position Register -------- */
#define ADC_XPOSR_XPOS_Pos 0
#define ADC_XPOSR_XPOS_Msk (0x3ffu << ADC_XPOSR_XPOS_Pos) /**< \brief (ADC_XPOSR) X Position */
#define ADC_XPOSR_XSCALE_Pos 16
#define ADC_XPOSR_XSCALE_Msk (0x3ffu << ADC_XPOSR_XSCALE_Pos) /**< \brief (ADC_XPOSR) Scale of XPOS */
/* -------- ADC_YPOSR : (ADC Offset: 0xB8) Touchscreen Y Position Register -------- */
#define ADC_YPOSR_YPOS_Pos 0
#define ADC_YPOSR_YPOS_Msk (0x3ffu << ADC_YPOSR_YPOS_Pos) /**< \brief (ADC_YPOSR) Y Position */
#define ADC_YPOSR_YSCALE_Pos 16
#define ADC_YPOSR_YSCALE_Msk (0x3ffu << ADC_YPOSR_YSCALE_Pos) /**< \brief (ADC_YPOSR) Scale of YPOS */
/* -------- ADC_PRESSR : (ADC Offset: 0xBC) Touchscreen Pressure Register -------- */
#define ADC_PRESSR_Z1_Pos 0
#define ADC_PRESSR_Z1_Msk (0x3ffu << ADC_PRESSR_Z1_Pos) /**< \brief (ADC_PRESSR) Data of Z1 Measurement */
#define ADC_PRESSR_Z2_Pos 16
#define ADC_PRESSR_Z2_Msk (0x3ffu << ADC_PRESSR_Z2_Pos) /**< \brief (ADC_PRESSR) Data of Z2 Measurement */
/* -------- ADC_TRGR : (ADC Offset: 0xC0) Trigger Register -------- */
#define ADC_TRGR_TRGMOD_Pos 0
#define ADC_TRGR_TRGMOD_Msk (0x7u << ADC_TRGR_TRGMOD_Pos) /**< \brief (ADC_TRGR) Trigger Mode */
#define   ADC_TRGR_TRGMOD_NO_TRIGGER (0x0u << 0) /**< \brief (ADC_TRGR) No trigger, only software trigger can start conversions */
#define   ADC_TRGR_TRGMOD_EXT_TRIG_RISE (0x1u << 0) /**< \brief (ADC_TRGR) External Trigger Rising Edge */
#define   ADC_TRGR_TRGMOD_EXT_TRIG_FALL (0x2u << 0) /**< \brief (ADC_TRGR) External Trigger Falling Edge */
#define   ADC_TRGR_TRGMOD_EXT_TRIG_ANY (0x3u << 0) /**< \brief (ADC_TRGR) External Trigger Any Edge */
#define   ADC_TRGR_TRGMOD_PEN_TRIG (0x4u << 0) /**< \brief (ADC_TRGR) Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode) */
#define   ADC_TRGR_TRGMOD_PERIOD_TRIG (0x5u << 0) /**< \brief (ADC_TRGR) Periodic Trigger (TRGPER shall be initiated appropriately) */
#define   ADC_TRGR_TRGMOD_CONTINUOUS (0x6u << 0) /**< \brief (ADC_TRGR) Continuous Mode */
#define ADC_TRGR_TRGPER_Pos 16
#define ADC_TRGR_TRGPER_Msk (0xffffu << ADC_TRGR_TRGPER_Pos) /**< \brief (ADC_TRGR) Trigger Period */
#define ADC_TRGR_TRGPER(value) ((ADC_TRGR_TRGPER_Msk & ((value) << ADC_TRGR_TRGPER_Pos)))
/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
#define ADC_WPMR_WPKEY_Pos 8
#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
#define ADC_WPSR_WPVSRC_Pos 8
#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_AES Advanced Encryption Standard */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Aes hardware registers */
typedef struct {
  WoReg AES_CR;        /**< \brief (Aes Offset: 0x00) Control Register */
  RwReg AES_MR;        /**< \brief (Aes Offset: 0x04) Mode Register */
  RoReg Reserved1[2];
  WoReg AES_IER;       /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */
  WoReg AES_IDR;       /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */
  RoReg AES_IMR;       /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */
  RoReg AES_ISR;       /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */
  WoReg AES_KEYWR[8];  /**< \brief (Aes Offset: 0x20) Key Word Register */
  WoReg AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */
  RoReg AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */
  WoReg AES_IVR[4];    /**< \brief (Aes Offset: 0x60) Initialization Vector Register */
  RwReg AES_AADLENR;   /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */
  RwReg AES_CLENR;     /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */
  RwReg AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */
  RoReg AES_TAGR[4];   /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */
  RoReg AES_CTRR;      /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */
  RwReg AES_GCMHR[4];  /**< \brief (Aes Offset: 0x9C) GCM H World Register */
} Aes;
#endif /* __ASSEMBLY__ */
/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */
#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */
#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */
#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */
/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */
#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */
#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */
#define AES_MR_PROCDLY_Pos 4
#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */
#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)))
#define AES_MR_SMOD_Pos 8
#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */
#define   AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */
#define   AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */
#define   AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode */
#define AES_MR_KEYSIZE_Pos 10
#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */
#define   AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */
#define   AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */
#define   AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */
#define AES_MR_OPMOD_Pos 12
#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */
#define   AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */
#define   AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */
#define   AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */
#define   AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */
#define   AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */
#define   AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois Counter mode */
#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */
#define AES_MR_CFBS_Pos 16
#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */
#define   AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */
#define   AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */
#define   AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */
#define   AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */
#define   AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */
#define AES_MR_CKEY_Pos 20
#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Countermeasure Key */
#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)))
#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) CounterMeasure Type 1 */
#define   AES_MR_CMTYP1_NOPROT_EXTXKEY (0x0u << 24) /**< \brief (AES_MR) Counter-Measure type 1 is disabled */
#define   AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Counter-Measure type 1 is enabled */
#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) CounterMeasure Type 2 */
#define   AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Counter-Measure type 2 is disabled */
#define   AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Counter-Measure type 2 is enabled */
#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) CounterMeasure Type 3 */
#define   AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Counter-Measure type 3 is disabled */
#define   AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Counter-Measure type 3 is enabled */
#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) CounterMeasure Type 4 */
#define   AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Counter-Measure type 4 is disabled */
#define   AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Counter-Measure type 4 is enabled */
#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) CounterMeasure Type 5 */
#define   AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Counter-Measure type 5 is disabled */
#define   AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Counter-Measure type 5 is enabled */
/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */
#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */
/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */
#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */
/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */
#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */
/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */
#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready */
#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status */
#define AES_ISR_URAT_Pos 12
#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access: */
#define   AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD=0x2 mode. */
#define   AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */
#define   AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */
#define   AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */
#define   AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */
#define   AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */
#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */
/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */
#define AES_KEYWR_KEYW_Pos 0
#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */
#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)))
/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */
#define AES_IDATAR_IDATA_Pos 0
#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */
#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)))
/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */
#define AES_ODATAR_ODATA_Pos 0
#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */
/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */
#define AES_IVR_IV_Pos 0
#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */
#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)))
/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */
#define AES_AADLENR_AADLEN_Pos 0
#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) AAD Length */
#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)))
/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */
#define AES_CLENR_CLEN_Pos 0
#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */
#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)))
/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */
#define AES_GHASHR_GHASH_Pos 0
#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */
#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)))
/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */
#define AES_TAGR_TAG_Pos 0
#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */
/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */
#define AES_CTRR_CTR_Pos 0
#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */
/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H World Register -------- */
#define AES_GCMHR_H_Pos 0
#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H word x */
#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)))

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_AIC Advanced Interrupt Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Aic hardware registers */
typedef struct {
  RwReg AIC_SSR;       /**< \brief (Aic Offset: 0x00) Source Select Register */
  RwReg AIC_SMR;       /**< \brief (Aic Offset: 0x04) Source Mode Register */
  RwReg AIC_SVR;       /**< \brief (Aic Offset: 0x08) Source Vector Register */
  RoReg Reserved1[1];
  RoReg AIC_IVR;       /**< \brief (Aic Offset: 0x10) Interrupt Vector Register */
  RoReg AIC_FVR;       /**< \brief (Aic Offset: 0x14) FIQ Interrupt Vector Register */
  RoReg AIC_ISR;       /**< \brief (Aic Offset: 0x18) Interrupt Status Register */
  RoReg Reserved2[1];
  RoReg AIC_IPR0;      /**< \brief (Aic Offset: 0x20) Interrupt Pending Register 0 */
  RoReg AIC_IPR1;      /**< \brief (Aic Offset: 0x24) Interrupt Pending Register 1 */
  RoReg AIC_IPR2;      /**< \brief (Aic Offset: 0x28) Interrupt Pending Register 2 */
  RoReg AIC_IPR3;      /**< \brief (Aic Offset: 0x2C) Interrupt Pending Register 3 */
  RoReg AIC_IMR;       /**< \brief (Aic Offset: 0x30) Interrupt Mask Register */
  RoReg AIC_CISR;      /**< \brief (Aic Offset: 0x34) Core Interrupt Status Register */
  WoReg AIC_EOICR;     /**< \brief (Aic Offset: 0x38) End of Interrupt Command Register */
  RwReg AIC_SPU;       /**< \brief (Aic Offset: 0x3C) Spurious Interrupt Vector Register */
  WoReg AIC_IECR;      /**< \brief (Aic Offset: 0x40) Interrupt Enable Command Register */
  WoReg AIC_IDCR;      /**< \brief (Aic Offset: 0x44) Interrupt Disable Command Register */
  WoReg AIC_ICCR;      /**< \brief (Aic Offset: 0x48) Interrupt Clear Command Register */
  WoReg AIC_ISCR;      /**< \brief (Aic Offset: 0x4C) Interrupt Set Command Register */
  WoReg AIC_FFER;      /**< \brief (Aic Offset: 0x50) Fast Forcing Enable Register */
  WoReg AIC_FFDR;      /**< \brief (Aic Offset: 0x54) Fast Forcing Disable Register */
  RoReg AIC_FFSR;      /**< \brief (Aic Offset: 0x58) Fast Forcing Status Register */
  RoReg Reserved3;
  WoReg AIC_SVRRER;    /**< \brief (Aic Offset: 0x60) AIC SVR Return Enable Register */
  WoReg AIC_SVRRDR;    /**< \brief (Aic Offset: 0x54) AIC SVR Return Disable Register */
  RoReg AIC_SVRRSR;    /**< \brief (Aic Offset: 0x68) AIC SVR Return status Register */
  RwReg AIC_DCR;       /**< \brief (Aic Offset: 0x6C) Debug Control Register */
  RoReg Reserved4[29];
  RwReg AIC_WPMR;      /**< \brief (Aic Offset: 0xE4) Write Protect Mode Register */
  RoReg AIC_WPSR;      /**< \brief (Aic Offset: 0xE8) Write Protect Status Register */
} Aic;
#endif /* __ASSEMBLY__ */
/* -------- AIC_SSR : (AIC Offset: 0x00) Source Select Register -------- */
#define AIC_SSR_INTSEL_Pos 0
#define AIC_SSR_INTSEL_Msk (0x7fu << AIC_SSR_INTSEL_Pos) /**< \brief (AIC_SSR) Interrupt line Selection */
#define AIC_SSR_INTSEL(value) ((AIC_SSR_INTSEL_Msk & ((value) << AIC_SSR_INTSEL_Pos)))
/* -------- AIC_SMR : (AIC Offset: 0x04) Source Mode Register -------- */
#define AIC_SMR_PRIOR_Pos 0
#define AIC_SMR_PRIOR_Msk (0x7u << AIC_SMR_PRIOR_Pos) /**< \brief (AIC_SMR) Priority Level */
#define AIC_SMR_PRIOR(value) ((AIC_SMR_PRIOR_Msk & ((value) << AIC_SMR_PRIOR_Pos)))
#define AIC_SMR_SRCTYPE_Pos 5
#define AIC_SMR_SRCTYPE_Msk (0x3u << AIC_SMR_SRCTYPE_Pos) /**< \brief (AIC_SMR) Interrupt Source Type */
#define   AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE (0x0u << 5) /**< \brief (AIC_SMR) High level Sensitive for internal sourceLow level Sensitive for external source */
#define   AIC_SMR_SRCTYPE_INT_EDGE_TRIGGERED (0x1u << 5) /**< \brief (AIC_SMR) Positive edge triggered for internal sourceNegative edge triggered for external source */
#define   AIC_SMR_SRCTYPE_EXT_HIGH_LEVEL (0x2u << 5) /**< \brief (AIC_SMR) High level Sensitive for internal sourceHigh level Sensitive for external source */
#define   AIC_SMR_SRCTYPE_EXT_POSITIVE_EDGE (0x3u << 5) /**< \brief (AIC_SMR) Positive edge triggered for internal sourcePositive edge triggered for external source */
/* -------- AIC_SVR : (AIC Offset: 0x08) Source Vector Register -------- */
#define AIC_SVR_VECTOR_Pos 0
#define AIC_SVR_VECTOR_Msk (0xffffffffu << AIC_SVR_VECTOR_Pos) /**< \brief (AIC_SVR) Source Vector */
#define AIC_SVR_VECTOR(value) ((AIC_SVR_VECTOR_Msk & ((value) << AIC_SVR_VECTOR_Pos)))
/* -------- AIC_IVR : (AIC Offset: 0x10) Interrupt Vector Register -------- */
#define AIC_IVR_IRQV_Pos 0
#define AIC_IVR_IRQV_Msk (0xffffffffu << AIC_IVR_IRQV_Pos) /**< \brief (AIC_IVR) Interrupt Vector Register */
/* -------- AIC_FVR : (AIC Offset: 0x14) FIQ Interrupt Vector Register -------- */
#define AIC_FVR_FIQV_Pos 0
#define AIC_FVR_FIQV_Msk (0xffffffffu << AIC_FVR_FIQV_Pos) /**< \brief (AIC_FVR) FIQ Vector Register */
/* -------- AIC_ISR : (AIC Offset: 0x18) Interrupt Status Register -------- */
#define AIC_ISR_IRQID_Pos 0
#define AIC_ISR_IRQID_Msk (0x7fu << AIC_ISR_IRQID_Pos) /**< \brief (AIC_ISR) Current Interrupt Identifier */
/* -------- AIC_IPR0 : (AIC Offset: 0x20) Interrupt Pending Register 0 -------- */
#define AIC_IPR0_FIQ (0x1u << 0) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_SYS (0x1u << 1) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID2 (0x1u << 2) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID3 (0x1u << 3) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID4 (0x1u << 4) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID5 (0x1u << 5) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID6 (0x1u << 6) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID7 (0x1u << 7) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID8 (0x1u << 8) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID9 (0x1u << 9) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID10 (0x1u << 10) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID11 (0x1u << 11) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID12 (0x1u << 12) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID13 (0x1u << 13) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID14 (0x1u << 14) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID15 (0x1u << 15) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID16 (0x1u << 16) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID17 (0x1u << 17) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID18 (0x1u << 18) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID19 (0x1u << 19) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID20 (0x1u << 20) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID21 (0x1u << 21) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID22 (0x1u << 22) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID23 (0x1u << 23) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID24 (0x1u << 24) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID25 (0x1u << 25) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID26 (0x1u << 26) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID27 (0x1u << 27) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID28 (0x1u << 28) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID29 (0x1u << 29) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID30 (0x1u << 30) /**< \brief (AIC_IPR0) Interrupt Pending */
#define AIC_IPR0_PID31 (0x1u << 31) /**< \brief (AIC_IPR0) Interrupt Pending */
/* -------- AIC_IPR1 : (AIC Offset: 0x24) Interrupt Pending Register 1 -------- */
#define AIC_IPR1_PID32 (0x1u << 0) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID33 (0x1u << 1) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID34 (0x1u << 2) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID35 (0x1u << 3) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID36 (0x1u << 4) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID37 (0x1u << 5) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID38 (0x1u << 6) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID39 (0x1u << 7) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID40 (0x1u << 8) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID41 (0x1u << 9) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID42 (0x1u << 10) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID43 (0x1u << 11) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID44 (0x1u << 12) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID45 (0x1u << 13) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID46 (0x1u << 14) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID47 (0x1u << 15) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID48 (0x1u << 16) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID49 (0x1u << 17) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID50 (0x1u << 18) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID51 (0x1u << 19) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID52 (0x1u << 20) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID53 (0x1u << 21) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID54 (0x1u << 22) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID55 (0x1u << 23) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID56 (0x1u << 24) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID57 (0x1u << 25) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID58 (0x1u << 26) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID59 (0x1u << 27) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID60 (0x1u << 28) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID61 (0x1u << 29) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID62 (0x1u << 30) /**< \brief (AIC_IPR1) Interrupt Pending */
#define AIC_IPR1_PID63 (0x1u << 31) /**< \brief (AIC_IPR1) Interrupt Pending */
/* -------- AIC_IPR2 : (AIC Offset: 0x28) Interrupt Pending Register 2 -------- */
#define AIC_IPR2_PID64 (0x1u << 0) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID65 (0x1u << 1) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID66 (0x1u << 2) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID67 (0x1u << 3) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID68 (0x1u << 4) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID69 (0x1u << 5) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID70 (0x1u << 6) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID71 (0x1u << 7) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID72 (0x1u << 8) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID73 (0x1u << 9) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID74 (0x1u << 10) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID75 (0x1u << 11) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID76 (0x1u << 12) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID77 (0x1u << 13) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID78 (0x1u << 14) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID79 (0x1u << 15) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID80 (0x1u << 16) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID81 (0x1u << 17) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID82 (0x1u << 18) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID83 (0x1u << 19) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID84 (0x1u << 20) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID85 (0x1u << 21) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID86 (0x1u << 22) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID87 (0x1u << 23) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID88 (0x1u << 24) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID89 (0x1u << 25) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID90 (0x1u << 26) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID91 (0x1u << 27) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID92 (0x1u << 28) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID93 (0x1u << 29) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID94 (0x1u << 30) /**< \brief (AIC_IPR2) Interrupt Pending */
#define AIC_IPR2_PID95 (0x1u << 31) /**< \brief (AIC_IPR2) Interrupt Pending */
/* -------- AIC_IPR3 : (AIC Offset: 0x2C) Interrupt Pending Register 3 -------- */
#define AIC_IPR3_PID96 (0x1u << 0) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID97 (0x1u << 1) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID98 (0x1u << 2) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID99 (0x1u << 3) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID100 (0x1u << 4) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID101 (0x1u << 5) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID102 (0x1u << 6) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID103 (0x1u << 7) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID104 (0x1u << 8) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID105 (0x1u << 9) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID106 (0x1u << 10) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID107 (0x1u << 11) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID108 (0x1u << 12) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID109 (0x1u << 13) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID110 (0x1u << 14) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID111 (0x1u << 15) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID112 (0x1u << 16) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID113 (0x1u << 17) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID114 (0x1u << 18) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID115 (0x1u << 19) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID116 (0x1u << 20) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID117 (0x1u << 21) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID118 (0x1u << 22) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID119 (0x1u << 23) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID120 (0x1u << 24) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID121 (0x1u << 25) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID122 (0x1u << 26) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID123 (0x1u << 27) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID124 (0x1u << 28) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID125 (0x1u << 29) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID126 (0x1u << 30) /**< \brief (AIC_IPR3) Interrupt Pending */
#define AIC_IPR3_PID127 (0x1u << 31) /**< \brief (AIC_IPR3) Interrupt Pending */
/* -------- AIC_IMR : (AIC Offset: 0x30) Interrupt Mask Register -------- */
#define AIC_IMR_INTM (0x1u << 0) /**< \brief (AIC_IMR) Interrupt Mask */
/* -------- AIC_CISR : (AIC Offset: 0x34) Core Interrupt Status Register -------- */
#define AIC_CISR_NFIQ (0x1u << 0) /**< \brief (AIC_CISR) NFIQ Status */
#define AIC_CISR_NIRQ (0x1u << 1) /**< \brief (AIC_CISR) NIRQ Status */
/* -------- AIC_SPU : (AIC Offset: 0x3C) Spurious Interrupt Vector Register -------- */
#define AIC_SPU_SIVR_Pos 0
#define AIC_SPU_SIVR_Msk (0xffffffffu << AIC_SPU_SIVR_Pos) /**< \brief (AIC_SPU) Spurious Interrupt Vector Register */
#define AIC_SPU_SIVR(value) ((AIC_SPU_SIVR_Msk & ((value) << AIC_SPU_SIVR_Pos)))
/* -------- AIC_IECR : (AIC Offset: 0x40) Interrupt Enable Command Register -------- */
#define AIC_IECR_INTEN (0x1u << 0) /**< \brief (AIC_IECR) Interrupt Enable */
/* -------- AIC_IDCR : (AIC Offset: 0x44) Interrupt Disable Command Register -------- */
#define AIC_IDCR_INTD (0x1u << 0) /**< \brief (AIC_IDCR) Interrupt Disable */
/* -------- AIC_ICCR : (AIC Offset: 0x48) Interrupt Clear Command Register -------- */
#define AIC_ICCR_INTCLR (0x1u << 0) /**< \brief (AIC_ICCR) Interrupt Clear */
/* -------- AIC_ISCR : (AIC Offset: 0x4C) Interrupt Set Command Register -------- */
#define AIC_ISCR_INTSET (0x1u << 0) /**< \brief (AIC_ISCR) Interrupt Set */
/* -------- AIC_FFER : (AIC Offset: 0x50) Fast Forcing Enable Register -------- */
#define AIC_FFER_FFEN (0x1u << 0) /**< \brief (AIC_FFER) Fast Forcing Enable */
/* -------- AIC_FFDR : (AIC Offset: 0x54) Fast Forcing Disable Register -------- */
#define AIC_FFDR_FFDIS (0x1u << 0) /**< \brief (AIC_FFDR) Fast Forcing Disable */
/* -------- AIC_FFSR : (AIC Offset: 0x58) Fast Forcing Status Register -------- */
#define AIC_FFSR_FFS (0x1u << 0) /**< \brief (AIC_FFSR) Fast Forcing Status */
/* -------- AIC_DCR : (AIC Offset: 0x6C) Debug Control Register -------- */
#define AIC_DCR_PROT (0x1u << 0) /**< \brief (AIC_DCR) Protection Mode */
#define AIC_DCR_GMSK (0x1u << 1) /**< \brief (AIC_DCR) General Mask */
/* -------- AIC_WPMR : (AIC Offset: 0xE4) Write Protect Mode Register -------- */
#define AIC_WPMR_WPEN (0x1u << 0) /**< \brief (AIC_WPMR) Write Protect Enable */
#define AIC_WPMR_WPKEY_Pos 8
#define AIC_WPMR_WPKEY_Msk (0xffffffu << AIC_WPMR_WPKEY_Pos) /**< \brief (AIC_WPMR) Write Protect KEY */
#define AIC_WPMR_WPKEY(value) ((AIC_WPMR_WPKEY_Msk & ((value) << AIC_WPMR_WPKEY_Pos)))
/* -------- AIC_WPSR : (AIC Offset: 0xE8) Write Protect Status Register -------- */
#define AIC_WPSR_WPVS (0x1u << 0) /**< \brief (AIC_WPSR) Write Protect Violation Status */
#define AIC_WPSR_WPVSRC_Pos 8
#define AIC_WPSR_WPVSRC_Msk (0xffffu << AIC_WPSR_WPVSRC_Pos) /**< \brief (AIC_WPSR) Write Protect Violation Source */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR AXI MATRIX */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_AXIMX AXI MATRIX */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Aximx hardware registers */
typedef struct {
  WoReg AXIMX_REMAP;               /**< \brief (Aximx Offset: 0x00) Remap Register */
  RoReg Reserved1[2035];
  RoReg AXIMX_PERIPH_ID4;          /**< \brief (Aximx Offset: 0x1FD0) Peripheral ID Register 4 */
  RoReg AXIMX_PERIPH_ID5;          /**< \brief (Aximx Offset: 0x1FD4) Peripheral ID Register 5 */
  RoReg AXIMX_PERIPH_ID6;          /**< \brief (Aximx Offset: 0x1FD8) Peripheral ID Register 6 */
  RoReg AXIMX_PERIPH_ID7;          /**< \brief (Aximx Offset: 0x1FDC) Peripheral ID Register 7 */
  RoReg AXIMX_PERIPH_ID0;          /**< \brief (Aximx Offset: 0x1FE0) Peripheral ID Register 0 */
  RoReg AXIMX_PERIPH_ID1;          /**< \brief (Aximx Offset: 0x1FE4) Peripheral ID Register 1 */
  RoReg AXIMX_PERIPH_ID2;          /**< \brief (Aximx Offset: 0x1FE8) Peripheral ID Register 2 */
  RoReg AXIMX_PERIPH_ID3;          /**< \brief (Aximx Offset: 0x1FEC) Peripheral ID Register 3 */
  RoReg AXIMX_COMP_ID[4];          /**< \brief (Aximx Offset: 0x1FF0) Component ID Register */
  RoReg Reserved2[3074];
  RwReg AXIMX_AMIB3_FN_MOD_BM_ISS; /**< \brief (Aximx Offset: 0x5008) AMIB3 Bus Matrix Functionality Modification Register */
  RoReg Reserved3[6];
  RwReg AXIMX_AMIB3_FN_MOD2;       /**< \brief (Aximx Offset: 0x5024) AMIB3 Bypass Merge */
  RoReg Reserved4[62518];
  RwReg AXIMX_ASIB0_READ_QOS;      /**< \brief (Aximx Offset: 0x42100) ASIB0 Read Channel QoS Register */
  RwReg AXIMX_ASIB0_WRITE_QOS;     /**< \brief (Aximx Offset: 0x42104) ASIB0 Write Channel QoS Register */
  RoReg Reserved5[968];
  RwReg AXIMX_ASIB1_FN_MOD_AHB;    /**< \brief (Aximx Offset: 0x43028) ASIB1 AHB Functionality Modification Register */
  RoReg Reserved6[53];
  RwReg AXIMX_ASIB1_READ_QOS;      /**< \brief (Aximx Offset: 0x43100) ASIB1 Read Channel QoS Register */
  RwReg AXIMX_ASIB1_WRITE_QOS;     /**< \brief (Aximx Offset: 0x43104) ASIB1 Write Channel QoS Register */
  RwReg AXIMX_ASIB1_FN_MOD;        /**< \brief (Aximx Offset: 0x43108) ASIB1 Issuing Functionality Modification Register */
} Aximx;
#endif /* __ASSEMBLY__ */
/* -------- AXIMX_REMAP : (AXIMX Offset: 0x00) Remap Register -------- */
#define AXIMX_REMAP_REMAP0 (0x1u << 0) /**< \brief (AXIMX_REMAP) Remap State 0 */
#define AXIMX_REMAP_REMAP1 (0x1u << 1) /**< \brief (AXIMX_REMAP) Remap State 1 */
/* -------- AXIMX_PERIPH_ID4 : (AXIMX Offset: 0x1FD0) Peripheral ID Register 4 -------- */
#define AXIMX_PERIPH_ID4_ID_Pos 0
#define AXIMX_PERIPH_ID4_ID_Msk (0xffu << AXIMX_PERIPH_ID4_ID_Pos) /**< \brief (AXIMX_PERIPH_ID4) Peripheral ID */
#define   AXIMX_PERIPH_ID4_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID4) Part Number */
#define   AXIMX_PERIPH_ID4_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID4) 4KB count, JEP106 continuation code */
#define   AXIMX_PERIPH_ID4_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID4) JEP106[3:0, part number[11:8] */
#define   AXIMX_PERIPH_ID4_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID4) Revision, JEP106 code flag, JEP106[6:4] */
/* -------- AXIMX_PERIPH_ID5 : (AXIMX Offset: 0x1FD4) Peripheral ID Register 5 -------- */
#define AXIMX_PERIPH_ID5_ID_Pos 0
#define AXIMX_PERIPH_ID5_ID_Msk (0xffu << AXIMX_PERIPH_ID5_ID_Pos) /**< \brief (AXIMX_PERIPH_ID5) Peripheral ID */
#define   AXIMX_PERIPH_ID5_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID5) Part Number */
#define   AXIMX_PERIPH_ID5_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID5) 4KB count, JEP106 continuation code */
#define   AXIMX_PERIPH_ID5_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID5) JEP106[3:0, part number[11:8] */
#define   AXIMX_PERIPH_ID5_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID5) Revision, JEP106 code flag, JEP106[6:4] */
/* -------- AXIMX_PERIPH_ID6 : (AXIMX Offset: 0x1FD8) Peripheral ID Register 6 -------- */
#define AXIMX_PERIPH_ID6_ID_Pos 0
#define AXIMX_PERIPH_ID6_ID_Msk (0xffu << AXIMX_PERIPH_ID6_ID_Pos) /**< \brief (AXIMX_PERIPH_ID6) Peripheral ID */
#define   AXIMX_PERIPH_ID6_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID6) Part Number */
#define   AXIMX_PERIPH_ID6_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID6) 4KB count, JEP106 continuation code */
#define   AXIMX_PERIPH_ID6_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID6) JEP106[3:0, part number[11:8] */
#define   AXIMX_PERIPH_ID6_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID6) Revision, JEP106 code flag, JEP106[6:4] */
/* -------- AXIMX_PERIPH_ID7 : (AXIMX Offset: 0x1FDC) Peripheral ID Register 7 -------- */
#define AXIMX_PERIPH_ID7_ID_Pos 0
#define AXIMX_PERIPH_ID7_ID_Msk (0xffu << AXIMX_PERIPH_ID7_ID_Pos) /**< \brief (AXIMX_PERIPH_ID7) Peripheral ID */
#define   AXIMX_PERIPH_ID7_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID7) Part Number */
#define   AXIMX_PERIPH_ID7_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID7) 4KB count, JEP106 continuation code */
#define   AXIMX_PERIPH_ID7_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID7) JEP106[3:0, part number[11:8] */
#define   AXIMX_PERIPH_ID7_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID7) Revision, JEP106 code flag, JEP106[6:4] */
/* -------- AXIMX_PERIPH_ID0 : (AXIMX Offset: 0x1FE0) Peripheral ID Register 0 -------- */
#define AXIMX_PERIPH_ID0_ID_Pos 0
#define AXIMX_PERIPH_ID0_ID_Msk (0xffu << AXIMX_PERIPH_ID0_ID_Pos) /**< \brief (AXIMX_PERIPH_ID0) Peripheral ID */
#define   AXIMX_PERIPH_ID0_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID0) Part Number */
#define   AXIMX_PERIPH_ID0_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID0) 4KB count, JEP106 continuation code */
#define   AXIMX_PERIPH_ID0_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID0) JEP106[3:0, part number[11:8] */
#define   AXIMX_PERIPH_ID0_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID0) Revision, JEP106 code flag, JEP106[6:4] */
/* -------- AXIMX_PERIPH_ID1 : (AXIMX Offset: 0x1FE4) Peripheral ID Register 1 -------- */
#define AXIMX_PERIPH_ID1_ID_Pos 0
#define AXIMX_PERIPH_ID1_ID_Msk (0xffu << AXIMX_PERIPH_ID1_ID_Pos) /**< \brief (AXIMX_PERIPH_ID1) Peripheral ID */
#define   AXIMX_PERIPH_ID1_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID1) Part Number */
#define   AXIMX_PERIPH_ID1_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID1) 4KB count, JEP106 continuation code */
#define   AXIMX_PERIPH_ID1_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID1) JEP106[3:0, part number[11:8] */
#define   AXIMX_PERIPH_ID1_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID1) Revision, JEP106 code flag, JEP106[6:4] */
/* -------- AXIMX_PERIPH_ID2 : (AXIMX Offset: 0x1FE8) Peripheral ID Register 2 -------- */
#define AXIMX_PERIPH_ID2_ID_Pos 0
#define AXIMX_PERIPH_ID2_ID_Msk (0xffu << AXIMX_PERIPH_ID2_ID_Pos) /**< \brief (AXIMX_PERIPH_ID2) Peripheral ID */
#define   AXIMX_PERIPH_ID2_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID2) Part Number */
#define   AXIMX_PERIPH_ID2_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID2) 4KB count, JEP106 continuation code */
#define   AXIMX_PERIPH_ID2_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID2) JEP106[3:0, part number[11:8] */
#define   AXIMX_PERIPH_ID2_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID2) Revision, JEP106 code flag, JEP106[6:4] */
/* -------- AXIMX_PERIPH_ID3 : (AXIMX Offset: 0x1FEC) Peripheral ID Register 3 -------- */
#define AXIMX_PERIPH_ID3_ID_Pos 0
#define AXIMX_PERIPH_ID3_ID_Msk (0xffu << AXIMX_PERIPH_ID3_ID_Pos) /**< \brief (AXIMX_PERIPH_ID3) Peripheral ID */
#define   AXIMX_PERIPH_ID3_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID3) Part Number */
#define   AXIMX_PERIPH_ID3_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID3) 4KB count, JEP106 continuation code */
#define   AXIMX_PERIPH_ID3_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID3) JEP106[3:0, part number[11:8] */
#define   AXIMX_PERIPH_ID3_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID3) Revision, JEP106 code flag, JEP106[6:4] */
/* -------- AXIMX_COMP_ID[4] : (AXIMX Offset: 0x1FF0) Component ID Register -------- */
#define AXIMX_COMP_ID_ID_Pos 0
#define AXIMX_COMP_ID_ID_Msk (0xffu << AXIMX_COMP_ID_ID_Pos) /**< \brief (AXIMX_COMP_ID[4]) Component ID */
/* -------- AXIMX_AMIB3_FN_MOD_BM_ISS : (AXIMX Offset: 0x5008) AMIB3 Bus Matrix Functionality Modification Register -------- */
#define AXIMX_AMIB3_FN_MOD_BM_ISS_RD_ISS (0x1u << 0) /**< \brief (AXIMX_AMIB3_FN_MOD_BM_ISS) Read Issuing */
#define AXIMX_AMIB3_FN_MOD_BM_ISS_WR_ISS (0x1u << 1) /**< \brief (AXIMX_AMIB3_FN_MOD_BM_ISS) Write Issuing */
/* -------- AXIMX_AMIB3_FN_MOD2 : (AXIMX Offset: 0x5024) AMIB3 Bypass Merge -------- */
#define AXIMX_AMIB3_FN_MOD2_BP_MRG (0x1u << 0) /**< \brief (AXIMX_AMIB3_FN_MOD2) Bypass Merge */
/* -------- AXIMX_ASIB0_READ_QOS : (AXIMX Offset: 0x42100) ASIB0 Read Channel QoS Register -------- */
#define AXIMX_ASIB0_READ_QOS_RD_QOS_Pos 0
#define AXIMX_ASIB0_READ_QOS_RD_QOS_Msk (0xfu << AXIMX_ASIB0_READ_QOS_RD_QOS_Pos) /**< \brief (AXIMX_ASIB0_READ_QOS) Read QoS */
#define AXIMX_ASIB0_READ_QOS_RD_QOS(value) ((AXIMX_ASIB0_READ_QOS_RD_QOS_Msk & ((value) << AXIMX_ASIB0_READ_QOS_RD_QOS_Pos)))
/* -------- AXIMX_ASIB0_WRITE_QOS : (AXIMX Offset: 0x42104) ASIB0 Write Channel QoS Register -------- */
#define AXIMX_ASIB0_WRITE_QOS_WR_QOS_Pos 0
#define AXIMX_ASIB0_WRITE_QOS_WR_QOS_Msk (0xfu << AXIMX_ASIB0_WRITE_QOS_WR_QOS_Pos) /**< \brief (AXIMX_ASIB0_WRITE_QOS) Write QoS */
#define AXIMX_ASIB0_WRITE_QOS_WR_QOS(value) ((AXIMX_ASIB0_WRITE_QOS_WR_QOS_Msk & ((value) << AXIMX_ASIB0_WRITE_QOS_WR_QOS_Pos)))
/* -------- AXIMX_ASIB1_FN_MOD_AHB : (AXIMX Offset: 0x43028) ASIB1 AHB Functionality Modification Register -------- */
#define AXIMX_ASIB1_FN_MOD_AHB_RD_INCR_OVR (0x1u << 0) /**< \brief (AXIMX_ASIB1_FN_MOD_AHB) Read INCR Override */
#define AXIMX_ASIB1_FN_MOD_AHB_WR_INCR_OVR (0x1u << 1) /**< \brief (AXIMX_ASIB1_FN_MOD_AHB) Write INCR override */
#define AXIMX_ASIB1_FN_MOD_AHB_LOCK_OVR (0x1u << 2) /**< \brief (AXIMX_ASIB1_FN_MOD_AHB) Lock Override */
/* -------- AXIMX_ASIB1_READ_QOS : (AXIMX Offset: 0x43100) ASIB1 Read Channel QoS Register -------- */
#define AXIMX_ASIB1_READ_QOS_RD_QOS_Pos 0
#define AXIMX_ASIB1_READ_QOS_RD_QOS_Msk (0xfu << AXIMX_ASIB1_READ_QOS_RD_QOS_Pos) /**< \brief (AXIMX_ASIB1_READ_QOS) Read QoS */
#define AXIMX_ASIB1_READ_QOS_RD_QOS(value) ((AXIMX_ASIB1_READ_QOS_RD_QOS_Msk & ((value) << AXIMX_ASIB1_READ_QOS_RD_QOS_Pos)))
/* -------- AXIMX_ASIB1_WRITE_QOS : (AXIMX Offset: 0x43104) ASIB1 Write Channel QoS Register -------- */
#define AXIMX_ASIB1_WRITE_QOS_WR_QOS_Pos 0
#define AXIMX_ASIB1_WRITE_QOS_WR_QOS_Msk (0xfu << AXIMX_ASIB1_WRITE_QOS_WR_QOS_Pos) /**< \brief (AXIMX_ASIB1_WRITE_QOS) Write QoS */
#define AXIMX_ASIB1_WRITE_QOS_WR_QOS(value) ((AXIMX_ASIB1_WRITE_QOS_WR_QOS_Msk & ((value) << AXIMX_ASIB1_WRITE_QOS_WR_QOS_Pos)))
/* -------- AXIMX_ASIB1_FN_MOD : (AXIMX Offset: 0x43108) ASIB1 Issuing Functionality Modification Register -------- */
#define AXIMX_ASIB1_FN_MOD_RD_ISS (0x1u << 0) /**< \brief (AXIMX_ASIB1_FN_MOD) Read Issuing */
#define AXIMX_ASIB1_FN_MOD_WR_ISS (0x1u << 1) /**< \brief (AXIMX_ASIB1_FN_MOD) Write Issuing */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Boot Sequence Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_BSC Boot Sequence Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Bsc hardware registers */
typedef struct {
  RwReg BSC_CR; /**< \brief (Bsc Offset: 0x0) Boot Sequence Configuration Register */
} Bsc;
#endif /* __ASSEMBLY__ */
/* -------- BSC_CR : (BSC Offset: 0x0) Boot Sequence Configuration Register -------- */
#define BSC_CR_BOOT_Pos 0
#define BSC_CR_BOOT_Msk (0xffffffu << BSC_CR_BOOT_Pos) /**< \brief (BSC_CR)  */
#define BSC_CR_BOOT(value) ((BSC_CR_BOOT_Msk & ((value) << BSC_CR_BOOT_Pos)))
#define BSC_CR_BOOTKEY_Pos 24
#define BSC_CR_BOOTKEY_Msk (0xffu << BSC_CR_BOOTKEY_Pos) /**< \brief (BSC_CR)  */
#define   BSC_CR_BOOTKEY_VALID (0xB5u << 24) /**< \brief (BSC_CR) valid boot key */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Controller Area Network */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_CAN Controller Area Network */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief CanMb hardware registers */
typedef struct {
  RwReg  CAN_MMR;        /**< \brief (CanMb Offset: 0x0) Mailbox Mode Register */
  RwReg  CAN_MAM;        /**< \brief (CanMb Offset: 0x4) Mailbox Acceptance Mask Register */
  RwReg  CAN_MID;        /**< \brief (CanMb Offset: 0x8) Mailbox ID Register */
  RwReg  CAN_MFID;       /**< \brief (CanMb Offset: 0xC) Mailbox Family ID Register */
  RwReg  CAN_MSR;        /**< \brief (CanMb Offset: 0x10) Mailbox Status Register */
  RwReg  CAN_MDL;        /**< \brief (CanMb Offset: 0x14) Mailbox Data Low Register */
  RwReg  CAN_MDH;        /**< \brief (CanMb Offset: 0x18) Mailbox Data High Register */
  RwReg  CAN_MCR;        /**< \brief (CanMb Offset: 0x1C) Mailbox Control Register */
} CanMb;
/** \brief Can hardware registers */
#define CANMB_NUMBER 8
typedef struct {
  RwReg  CAN_MR;         /**< \brief (Can Offset: 0x0000) Mode Register */
  WoReg  CAN_IER;        /**< \brief (Can Offset: 0x0004) Interrupt Enable Register */
  WoReg  CAN_IDR;        /**< \brief (Can Offset: 0x0008) Interrupt Disable Register */
  RoReg  CAN_IMR;        /**< \brief (Can Offset: 0x000C) Interrupt Mask Register */
  RoReg  CAN_SR;         /**< \brief (Can Offset: 0x0010) Status Register */
  RwReg  CAN_BR;         /**< \brief (Can Offset: 0x0014) Baudrate Register */
  RoReg  CAN_TIM;        /**< \brief (Can Offset: 0x0018) Timer Register */
  RoReg  CAN_TIMESTP;    /**< \brief (Can Offset: 0x001C) Timestamp Register */
  RoReg  CAN_ECR;        /**< \brief (Can Offset: 0x0020) Error Counter Register */
  WoReg  CAN_TCR;        /**< \brief (Can Offset: 0x0024) Transfer Command Register */
  WoReg  CAN_ACR;        /**< \brief (Can Offset: 0x0028) Abort Command Register */
  RoReg  Reserved1[117];
  CanMb  CAN_MB[CANMB_NUMBER]; /**< \brief (Can Offset: 0x200) MB = 0 .. 7 */
} Can;
#endif /* __ASSEMBLY__ */
/* -------- CAN_MR : (CAN Offset: 0x0000) Mode Register -------- */
#define CAN_MR_CANEN (0x1u << 0) /**< \brief (CAN_MR) CAN Controller Enable */
#define CAN_MR_LPM (0x1u << 1) /**< \brief (CAN_MR) Disable/Enable Low Power Mode */
#define CAN_MR_ABM (0x1u << 2) /**< \brief (CAN_MR) Disable/Enable Autobaud/Listen mode */
#define CAN_MR_OVL (0x1u << 3) /**< \brief (CAN_MR) Disable/Enable Overload Frame */
#define CAN_MR_TEOF (0x1u << 4) /**< \brief (CAN_MR) Timestamp messages at each end of Frame */
#define CAN_MR_TTM (0x1u << 5) /**< \brief (CAN_MR) Disable/Enable Time Triggered Mode */
#define CAN_MR_TIMFRZ (0x1u << 6) /**< \brief (CAN_MR) Enable Timer Freeze */
#define CAN_MR_DRPT (0x1u << 7) /**< \brief (CAN_MR) Disable Repeat */
/* -------- CAN_IER : (CAN Offset: 0x0004) Interrupt Enable Register -------- */
#define CAN_IER_MB0 (0x1u << 0) /**< \brief (CAN_IER) Mailbox 0 Interrupt Enable */
#define CAN_IER_MB1 (0x1u << 1) /**< \brief (CAN_IER) Mailbox 1 Interrupt Enable */
#define CAN_IER_MB2 (0x1u << 2) /**< \brief (CAN_IER) Mailbox 2 Interrupt Enable */
#define CAN_IER_MB3 (0x1u << 3) /**< \brief (CAN_IER) Mailbox 3 Interrupt Enable */
#define CAN_IER_MB4 (0x1u << 4) /**< \brief (CAN_IER) Mailbox 4 Interrupt Enable */
#define CAN_IER_MB5 (0x1u << 5) /**< \brief (CAN_IER) Mailbox 5 Interrupt Enable */
#define CAN_IER_MB6 (0x1u << 6) /**< \brief (CAN_IER) Mailbox 6 Interrupt Enable */
#define CAN_IER_MB7 (0x1u << 7) /**< \brief (CAN_IER) Mailbox 7 Interrupt Enable */
#define CAN_IER_ERRA (0x1u << 16) /**< \brief (CAN_IER) Error Active Mode Interrupt Enable */
#define CAN_IER_WARN (0x1u << 17) /**< \brief (CAN_IER) Warning Limit Interrupt Enable */
#define CAN_IER_ERRP (0x1u << 18) /**< \brief (CAN_IER) Error Passive Mode Interrupt Enable */
#define CAN_IER_BOFF (0x1u << 19) /**< \brief (CAN_IER) Bus Off Mode Interrupt Enable */
#define CAN_IER_SLEEP (0x1u << 20) /**< \brief (CAN_IER) Sleep Interrupt Enable */
#define CAN_IER_WAKEUP (0x1u << 21) /**< \brief (CAN_IER) Wakeup Interrupt Enable */
#define CAN_IER_TOVF (0x1u << 22) /**< \brief (CAN_IER) Timer Overflow Interrupt Enable */
#define CAN_IER_TSTP (0x1u << 23) /**< \brief (CAN_IER) TimeStamp Interrupt Enable */
#define CAN_IER_CERR (0x1u << 24) /**< \brief (CAN_IER) CRC Error Interrupt Enable */
#define CAN_IER_SERR (0x1u << 25) /**< \brief (CAN_IER) Stuffing Error Interrupt Enable */
#define CAN_IER_AERR (0x1u << 26) /**< \brief (CAN_IER) Acknowledgment Error Interrupt Enable */
#define CAN_IER_FERR (0x1u << 27) /**< \brief (CAN_IER) Form Error Interrupt Enable */
#define CAN_IER_BERR (0x1u << 28) /**< \brief (CAN_IER) Bit Error Interrupt Enable */
/* -------- CAN_IDR : (CAN Offset: 0x0008) Interrupt Disable Register -------- */
#define CAN_IDR_MB0 (0x1u << 0) /**< \brief (CAN_IDR) Mailbox 0 Interrupt Disable */
#define CAN_IDR_MB1 (0x1u << 1) /**< \brief (CAN_IDR) Mailbox 1 Interrupt Disable */
#define CAN_IDR_MB2 (0x1u << 2) /**< \brief (CAN_IDR) Mailbox 2 Interrupt Disable */
#define CAN_IDR_MB3 (0x1u << 3) /**< \brief (CAN_IDR) Mailbox 3 Interrupt Disable */
#define CAN_IDR_MB4 (0x1u << 4) /**< \brief (CAN_IDR) Mailbox 4 Interrupt Disable */
#define CAN_IDR_MB5 (0x1u << 5) /**< \brief (CAN_IDR) Mailbox 5 Interrupt Disable */
#define CAN_IDR_MB6 (0x1u << 6) /**< \brief (CAN_IDR) Mailbox 6 Interrupt Disable */
#define CAN_IDR_MB7 (0x1u << 7) /**< \brief (CAN_IDR) Mailbox 7 Interrupt Disable */
#define CAN_IDR_ERRA (0x1u << 16) /**< \brief (CAN_IDR) Error Active Mode Interrupt Disable */
#define CAN_IDR_WARN (0x1u << 17) /**< \brief (CAN_IDR) Warning Limit Interrupt Disable */
#define CAN_IDR_ERRP (0x1u << 18) /**< \brief (CAN_IDR) Error Passive Mode Interrupt Disable */
#define CAN_IDR_BOFF (0x1u << 19) /**< \brief (CAN_IDR) Bus Off Mode Interrupt Disable */
#define CAN_IDR_SLEEP (0x1u << 20) /**< \brief (CAN_IDR) Sleep Interrupt Disable */
#define CAN_IDR_WAKEUP (0x1u << 21) /**< \brief (CAN_IDR) Wakeup Interrupt Disable */
#define CAN_IDR_TOVF (0x1u << 22) /**< \brief (CAN_IDR) Timer Overflow Interrupt */
#define CAN_IDR_TSTP (0x1u << 23) /**< \brief (CAN_IDR) TimeStamp Interrupt Disable */
#define CAN_IDR_CERR (0x1u << 24) /**< \brief (CAN_IDR) CRC Error Interrupt Disable */
#define CAN_IDR_SERR (0x1u << 25) /**< \brief (CAN_IDR) Stuffing Error Interrupt Disable */
#define CAN_IDR_AERR (0x1u << 26) /**< \brief (CAN_IDR) Acknowledgment Error Interrupt Disable */
#define CAN_IDR_FERR (0x1u << 27) /**< \brief (CAN_IDR) Form Error Interrupt Disable */
#define CAN_IDR_BERR (0x1u << 28) /**< \brief (CAN_IDR) Bit Error Interrupt Disable */
/* -------- CAN_IMR : (CAN Offset: 0x000C) Interrupt Mask Register -------- */
#define CAN_IMR_MB0 (0x1u << 0) /**< \brief (CAN_IMR) Mailbox 0 Interrupt Mask */
#define CAN_IMR_MB1 (0x1u << 1) /**< \brief (CAN_IMR) Mailbox 1 Interrupt Mask */
#define CAN_IMR_MB2 (0x1u << 2) /**< \brief (CAN_IMR) Mailbox 2 Interrupt Mask */
#define CAN_IMR_MB3 (0x1u << 3) /**< \brief (CAN_IMR) Mailbox 3 Interrupt Mask */
#define CAN_IMR_MB4 (0x1u << 4) /**< \brief (CAN_IMR) Mailbox 4 Interrupt Mask */
#define CAN_IMR_MB5 (0x1u << 5) /**< \brief (CAN_IMR) Mailbox 5 Interrupt Mask */
#define CAN_IMR_MB6 (0x1u << 6) /**< \brief (CAN_IMR) Mailbox 6 Interrupt Mask */
#define CAN_IMR_MB7 (0x1u << 7) /**< \brief (CAN_IMR) Mailbox 7 Interrupt Mask */
#define CAN_IMR_ERRA (0x1u << 16) /**< \brief (CAN_IMR) Error Active Mode Interrupt Mask */
#define CAN_IMR_WARN (0x1u << 17) /**< \brief (CAN_IMR) Warning Limit Interrupt Mask */
#define CAN_IMR_ERRP (0x1u << 18) /**< \brief (CAN_IMR) Error Passive Mode Interrupt Mask */
#define CAN_IMR_BOFF (0x1u << 19) /**< \brief (CAN_IMR) Bus Off Mode Interrupt Mask */
#define CAN_IMR_SLEEP (0x1u << 20) /**< \brief (CAN_IMR) Sleep Interrupt Mask */
#define CAN_IMR_WAKEUP (0x1u << 21) /**< \brief (CAN_IMR) Wakeup Interrupt Mask */
#define CAN_IMR_TOVF (0x1u << 22) /**< \brief (CAN_IMR) Timer Overflow Interrupt Mask */
#define CAN_IMR_TSTP (0x1u << 23) /**< \brief (CAN_IMR) Timestamp Interrupt Mask */
#define CAN_IMR_CERR (0x1u << 24) /**< \brief (CAN_IMR) CRC Error Interrupt Mask */
#define CAN_IMR_SERR (0x1u << 25) /**< \brief (CAN_IMR) Stuffing Error Interrupt Mask */
#define CAN_IMR_AERR (0x1u << 26) /**< \brief (CAN_IMR) Acknowledgment Error Interrupt Mask */
#define CAN_IMR_FERR (0x1u << 27) /**< \brief (CAN_IMR) Form Error Interrupt Mask */
#define CAN_IMR_BERR (0x1u << 28) /**< \brief (CAN_IMR) Bit Error Interrupt Mask */
/* -------- CAN_SR : (CAN Offset: 0x0010) Status Register -------- */
#define CAN_SR_MB0 (0x1u << 0) /**< \brief (CAN_SR) Mailbox 0 Event */
#define CAN_SR_MB1 (0x1u << 1) /**< \brief (CAN_SR) Mailbox 1 Event */
#define CAN_SR_MB2 (0x1u << 2) /**< \brief (CAN_SR) Mailbox 2 Event */
#define CAN_SR_MB3 (0x1u << 3) /**< \brief (CAN_SR) Mailbox 3 Event */
#define CAN_SR_MB4 (0x1u << 4) /**< \brief (CAN_SR) Mailbox 4 Event */
#define CAN_SR_MB5 (0x1u << 5) /**< \brief (CAN_SR) Mailbox 5 Event */
#define CAN_SR_MB6 (0x1u << 6) /**< \brief (CAN_SR) Mailbox 6 Event */
#define CAN_SR_MB7 (0x1u << 7) /**< \brief (CAN_SR) Mailbox 7 Event */
#define CAN_SR_ERRA (0x1u << 16) /**< \brief (CAN_SR) Error Active Mode */
#define CAN_SR_WARN (0x1u << 17) /**< \brief (CAN_SR) Warning Limit */
#define CAN_SR_ERRP (0x1u << 18) /**< \brief (CAN_SR) Error Passive Mode */
#define CAN_SR_BOFF (0x1u << 19) /**< \brief (CAN_SR) Bus Off Mode */
#define CAN_SR_SLEEP (0x1u << 20) /**< \brief (CAN_SR) CAN controller in Low power Mode */
#define CAN_SR_WAKEUP (0x1u << 21) /**< \brief (CAN_SR) CAN controller is not in Low power Mode */
#define CAN_SR_TOVF (0x1u << 22) /**< \brief (CAN_SR) Timer Overflow */
#define CAN_SR_TSTP (0x1u << 23) /**< \brief (CAN_SR)  */
#define CAN_SR_CERR (0x1u << 24) /**< \brief (CAN_SR) Mailbox CRC Error */
#define CAN_SR_SERR (0x1u << 25) /**< \brief (CAN_SR) Mailbox Stuffing Error */
#define CAN_SR_AERR (0x1u << 26) /**< \brief (CAN_SR) Acknowledgment Error */
#define CAN_SR_FERR (0x1u << 27) /**< \brief (CAN_SR) Form Error */
#define CAN_SR_BERR (0x1u << 28) /**< \brief (CAN_SR) Bit Error */
#define CAN_SR_RBSY (0x1u << 29) /**< \brief (CAN_SR) Receiver busy */
#define CAN_SR_TBSY (0x1u << 30) /**< \brief (CAN_SR) Transmitter busy */
#define CAN_SR_OVLSY (0x1u << 31) /**< \brief (CAN_SR) Overload busy */
/* -------- CAN_BR : (CAN Offset: 0x0014) Baudrate Register -------- */
#define CAN_BR_PHASE2_Pos 0
#define CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) /**< \brief (CAN_BR) Phase 2 segment */
#define CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos)))
#define CAN_BR_PHASE1_Pos 4
#define CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) /**< \brief (CAN_BR) Phase 1 segment */
#define CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos)))
#define CAN_BR_PROPAG_Pos 8
#define CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) /**< \brief (CAN_BR) Programming time segment */
#define CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos)))
#define CAN_BR_SJW_Pos 12
#define CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) /**< \brief (CAN_BR) Re-synchronization jump width */
#define CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos)))
#define CAN_BR_BRP_Pos 16
#define CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) /**< \brief (CAN_BR) Baudrate Prescaler. */
#define CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos)))
#define CAN_BR_SMP (0x1u << 24) /**< \brief (CAN_BR) Sampling Mode */
#define   CAN_BR_SMP_ONCE (0x0u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled once at sample point. */
#define   CAN_BR_SMP_THREE (0x1u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. */
/* -------- CAN_TIM : (CAN Offset: 0x0018) Timer Register -------- */
#define CAN_TIM_TIMER0 (0x1u << 0) /**< \brief (CAN_TIM) Timer */
#define CAN_TIM_TIMER1 (0x1u << 1) /**< \brief (CAN_TIM) Timer */
#define CAN_TIM_TIMER2 (0x1u << 2) /**< \brief (CAN_TIM) Timer */
#define CAN_TIM_TIMER3 (0x1u << 3) /**< \brief (CAN_TIM) Timer */
#define CAN_TIM_TIMER4 (0x1u << 4) /**< \brief (CAN_TIM) Timer */
#define CAN_TIM_TIMER5 (0x1u << 5) /**< \brief (CAN_TIM) Timer */
#define CAN_TIM_TIMER6 (0x1u << 6) /**< \brief (CAN_TIM) Timer */
#define CAN_TIM_TIMER7 (0x1u << 7) /**< \brief (CAN_TIM) Timer */
/* -------- CAN_TIMESTP : (CAN Offset: 0x001C) Timestamp Register -------- */
#define CAN_TIMESTP_MTIMESTAMP0 (0x1u << 0) /**< \brief (CAN_TIMESTP) Timestamp */
#define CAN_TIMESTP_MTIMESTAMP1 (0x1u << 1) /**< \brief (CAN_TIMESTP) Timestamp */
#define CAN_TIMESTP_MTIMESTAMP2 (0x1u << 2) /**< \brief (CAN_TIMESTP) Timestamp */
#define CAN_TIMESTP_MTIMESTAMP3 (0x1u << 3) /**< \brief (CAN_TIMESTP) Timestamp */
#define CAN_TIMESTP_MTIMEMARK4 (0x1u << 4) /**< \brief (CAN_TIMESTP)  */
#define CAN_TIMESTP_MTIMESTAMP5 (0x1u << 5) /**< \brief (CAN_TIMESTP) Timestamp */
#define CAN_TIMESTP_MTIMESTAMP6 (0x1u << 6) /**< \brief (CAN_TIMESTP) Timestamp */
#define CAN_TIMESTP_MTIMESTAMP7 (0x1u << 7) /**< \brief (CAN_TIMESTP) Timestamp */
/* -------- CAN_ECR : (CAN Offset: 0x0020) Error Counter Register -------- */
#define CAN_ECR_REC_Pos 0
#define CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) /**< \brief (CAN_ECR) Receive Error Counter */
#define CAN_ECR_TEC_Pos 16
#define CAN_ECR_TEC_Msk (0x1ffu << CAN_ECR_TEC_Pos) /**< \brief (CAN_ECR) Transmit Error Counter */
/* -------- CAN_TCR : (CAN Offset: 0x0024) Transfer Command Register -------- */
#define CAN_TCR_MB0 (0x1u << 0) /**< \brief (CAN_TCR) Transfer Request for Mailbox 0 */
#define CAN_TCR_MB1 (0x1u << 1) /**< \brief (CAN_TCR) Transfer Request for Mailbox 1 */
#define CAN_TCR_MB2 (0x1u << 2) /**< \brief (CAN_TCR) Transfer Request for Mailbox 2 */
#define CAN_TCR_MB3 (0x1u << 3) /**< \brief (CAN_TCR) Transfer Request for Mailbox 3 */
#define CAN_TCR_MB4 (0x1u << 4) /**< \brief (CAN_TCR) Transfer Request for Mailbox 4 */
#define CAN_TCR_MB5 (0x1u << 5) /**< \brief (CAN_TCR) Transfer Request for Mailbox 5 */
#define CAN_TCR_MB6 (0x1u << 6) /**< \brief (CAN_TCR) Transfer Request for Mailbox 6 */
#define CAN_TCR_MB7 (0x1u << 7) /**< \brief (CAN_TCR) Transfer Request for Mailbox 7 */
#define CAN_TCR_TIMRST (0x1u << 31) /**< \brief (CAN_TCR) Timer Reset */
/* -------- CAN_ACR : (CAN Offset: 0x0028) Abort Command Register -------- */
#define CAN_ACR_MB0 (0x1u << 0) /**< \brief (CAN_ACR) Abort Request for Mailbox 0 */
#define CAN_ACR_MB1 (0x1u << 1) /**< \brief (CAN_ACR) Abort Request for Mailbox 1 */
#define CAN_ACR_MB2 (0x1u << 2) /**< \brief (CAN_ACR) Abort Request for Mailbox 2 */
#define CAN_ACR_MB3 (0x1u << 3) /**< \brief (CAN_ACR) Abort Request for Mailbox 3 */
#define CAN_ACR_MB4 (0x1u << 4) /**< \brief (CAN_ACR) Abort Request for Mailbox 4 */
#define CAN_ACR_MB5 (0x1u << 5) /**< \brief (CAN_ACR) Abort Request for Mailbox 5 */
#define CAN_ACR_MB6 (0x1u << 6) /**< \brief (CAN_ACR) Abort Request for Mailbox 6 */
#define CAN_ACR_MB7 (0x1u << 7) /**< \brief (CAN_ACR) Abort Request for Mailbox 7 */
/* -------- CAN_MMR : (CAN Offset: N/A) Mailbox Mode Register -------- */
#define CAN_MMR_MTIMEMARK0 (0x1u << 0) /**< \brief (CAN_MMR) Mailbox Timemark */
#define CAN_MMR_MTIMEMARK1 (0x1u << 1) /**< \brief (CAN_MMR) Mailbox Timemark */
#define CAN_MMR_MTIMEMARK2 (0x1u << 2) /**< \brief (CAN_MMR) Mailbox Timemark */
#define CAN_MMR_MTIMEMARK3 (0x1u << 3) /**< \brief (CAN_MMR) Mailbox Timemark */
#define CAN_MMR_MTIMEMARK4 (0x1u << 4) /**< \brief (CAN_MMR) Mailbox Timemark */
#define CAN_MMR_MTIMEMARK5 (0x1u << 5) /**< \brief (CAN_MMR) Mailbox Timemark */
#define CAN_MMR_MTIMEMARK6 (0x1u << 6) /**< \brief (CAN_MMR) Mailbox Timemark */
#define CAN_MMR_MTIMEMARK7 (0x1u << 7) /**< \brief (CAN_MMR) Mailbox Timemark */
#define CAN_MMR_PRIOR_Pos 16
#define CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) /**< \brief (CAN_MMR) Mailbox Priority */
#define CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos)))
#define CAN_MMR_MOT_Pos 24
#define CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) /**< \brief (CAN_MMR) Mailbox Object Type */
#define   CAN_MMR_MOT_MB_DISABLED (0x0u << 24) /**< \brief (CAN_MMR) Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. */
#define   CAN_MMR_MOT_MB_RX (0x1u << 24) /**< \brief (CAN_MMR) Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. */
#define   CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) /**< \brief (CAN_MMR) Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. */
#define   CAN_MMR_MOT_MB_TX (0x3u << 24) /**< \brief (CAN_MMR) Transmit mailbox. Mailbox is configured for transmission. */
#define   CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) /**< \brief (CAN_MMR) Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. */
#define   CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) /**< \brief (CAN_MMR) Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. */
/* -------- CAN_MAM : (CAN Offset: N/A) Mailbox Acceptance Mask Register -------- */
#define CAN_MAM_MIDvB_Pos 0
#define CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) /**< \brief (CAN_MAM) Complementary bits for identifier in extended frame mode */
#define CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos)))
#define CAN_MAM_MIDvA_Pos 18
#define CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) /**< \brief (CAN_MAM) Identifier for standard frame mode */
#define CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos)))
#define CAN_MAM_MIDE (0x1u << 29) /**< \brief (CAN_MAM) Identifier Version */
/* -------- CAN_MID : (CAN Offset: N/A) Mailbox ID Register -------- */
#define CAN_MID_MIDvB_Pos 0
#define CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) /**< \brief (CAN_MID) Complementary bits for identifier in extended frame mode */
#define CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos)))
#define CAN_MID_MIDvA_Pos 18
#define CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) /**< \brief (CAN_MID) Identifier for standard frame mode */
#define CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos)))
#define CAN_MID_MIDE (0x1u << 29) /**< \brief (CAN_MID) Identifier Version */
/* -------- CAN_MFID : (CAN Offset: N/A) Mailbox Family ID Register -------- */
#define CAN_MFID_MFID_Pos 0
#define CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) /**< \brief (CAN_MFID) Family ID */
/* -------- CAN_MSR : (CAN Offset: N/A) Mailbox Status Register -------- */
#define CAN_MSR_MTIMESTAMP0 (0x1u << 0) /**< \brief (CAN_MSR) Timer value */
#define CAN_MSR_MTIMESTAMP1 (0x1u << 1) /**< \brief (CAN_MSR) Timer value */
#define CAN_MSR_MTIMESTAMP2 (0x1u << 2) /**< \brief (CAN_MSR) Timer value */
#define CAN_MSR_MTIMESTAMP3 (0x1u << 3) /**< \brief (CAN_MSR) Timer value */
#define CAN_MSR_MTIMEMARK4 (0x1u << 4) /**< \brief (CAN_MSR)  */
#define CAN_MSR_MTIMESTAMP5 (0x1u << 5) /**< \brief (CAN_MSR) Timer value */
#define CAN_MSR_MTIMESTAMP6 (0x1u << 6) /**< \brief (CAN_MSR) Timer value */
#define CAN_MSR_MTIMESTAMP7 (0x1u << 7) /**< \brief (CAN_MSR) Timer value */
#define CAN_MSR_MDLC_Pos 16
#define CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) /**< \brief (CAN_MSR) Mailbox Data Length Code */
#define CAN_MSR_MRTR (0x1u << 20) /**< \brief (CAN_MSR) Mailbox Remote Transmission Request */
#define CAN_MSR_MABT (0x1u << 22) /**< \brief (CAN_MSR) Mailbox Message Abort */
#define CAN_MSR_MRDY (0x1u << 23) /**< \brief (CAN_MSR) Mailbox Ready */
#define CAN_MSR_MMI (0x1u << 24) /**< \brief (CAN_MSR) Mailbox Message Ignored */
/* -------- CAN_MDL : (CAN Offset: N/A) Mailbox Data Low Register -------- */
#define CAN_MDL_MDL_Pos 0
#define CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) /**< \brief (CAN_MDL) Message Data Low Value */
#define CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos)))
/* -------- CAN_MDH : (CAN Offset: N/A) Mailbox Data High Register -------- */
#define CAN_MDH_MDH_Pos 0
#define CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) /**< \brief (CAN_MDH) Message Data High Value */
#define CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos)))
/* -------- CAN_MCR : (CAN Offset: N/A) Mailbox Control Register -------- */
#define CAN_MCR_MDLC_Pos 16
#define CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) /**< \brief (CAN_MCR) Mailbox Data Length Code */
#define CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos)))
#define CAN_MCR_MRTR (0x1u << 20) /**< \brief (CAN_MCR) Mailbox Remote Transmission Request */
#define CAN_MCR_MACR (0x1u << 22) /**< \brief (CAN_MCR) Abort Request for Mailbox x */
#define CAN_MCR_MTCR (0x1u << 23) /**< \brief (CAN_MCR) Mailbox Transfer Command */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Debug Unit */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_DBGU Debug Unit */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Dbgu hardware registers */
typedef struct {
  WoReg DBGU_CR;      /**< \brief (Dbgu Offset: 0x0000) Control Register */
  RwReg DBGU_MR;      /**< \brief (Dbgu Offset: 0x0004) Mode Register */
  WoReg DBGU_IER;     /**< \brief (Dbgu Offset: 0x0008) Interrupt Enable Register */
  WoReg DBGU_IDR;     /**< \brief (Dbgu Offset: 0x000C) Interrupt Disable Register */
  RoReg DBGU_IMR;     /**< \brief (Dbgu Offset: 0x0010) Interrupt Mask Register */
  RoReg DBGU_SR;      /**< \brief (Dbgu Offset: 0x0014) Status Register */
  RoReg DBGU_RHR;     /**< \brief (Dbgu Offset: 0x0018) Receive Holding Register */
  WoReg DBGU_THR;     /**< \brief (Dbgu Offset: 0x001C) Transmit Holding Register */
  RwReg DBGU_BRGR;    /**< \brief (Dbgu Offset: 0x0020) Baud Rate Generator Register */
  RoReg Reserved1[7];
  RoReg DBGU_CIDR;    /**< \brief (Dbgu Offset: 0x0040) Chip ID Register */
  RoReg DBGU_EXID;    /**< \brief (Dbgu Offset: 0x0044) Chip ID Extension Register */
  RwReg DBGU_FNR;     /**< \brief (Dbgu Offset: 0x0048) Force NTRST Register */
} Dbgu;
#endif /* __ASSEMBLY__ */
/* -------- DBGU_CR : (DBGU Offset: 0x0000) Control Register -------- */
#define DBGU_CR_RSTRX (0x1u << 2) /**< \brief (DBGU_CR) Reset Receiver */
#define DBGU_CR_RSTTX (0x1u << 3) /**< \brief (DBGU_CR) Reset Transmitter */
#define DBGU_CR_RXEN (0x1u << 4) /**< \brief (DBGU_CR) Receiver Enable */
#define DBGU_CR_RXDIS (0x1u << 5) /**< \brief (DBGU_CR) Receiver Disable */
#define DBGU_CR_TXEN (0x1u << 6) /**< \brief (DBGU_CR) Transmitter Enable */
#define DBGU_CR_TXDIS (0x1u << 7) /**< \brief (DBGU_CR) Transmitter Disable */
#define DBGU_CR_RSTSTA (0x1u << 8) /**< \brief (DBGU_CR) Reset Status Bits */
/* -------- DBGU_MR : (DBGU Offset: 0x0004) Mode Register -------- */
#define DBGU_MR_PAR_Pos 9
#define DBGU_MR_PAR_Msk (0x7u << DBGU_MR_PAR_Pos) /**< \brief (DBGU_MR) Parity Type */
#define   DBGU_MR_PAR_EVEN (0x0u << 9) /**< \brief (DBGU_MR) Even Parity */
#define   DBGU_MR_PAR_ODD (0x1u << 9) /**< \brief (DBGU_MR) Odd Parity */
#define   DBGU_MR_PAR_SPACE (0x2u << 9) /**< \brief (DBGU_MR) Space: Parity forced to 0 */
#define   DBGU_MR_PAR_MARK (0x3u << 9) /**< \brief (DBGU_MR) Mark: Parity forced to 1 */
#define   DBGU_MR_PAR_NONE (0x4u << 9) /**< \brief (DBGU_MR) No Parity */
#define DBGU_MR_CHMODE_Pos 14
#define DBGU_MR_CHMODE_Msk (0x3u << DBGU_MR_CHMODE_Pos) /**< \brief (DBGU_MR) Channel Mode */
#define   DBGU_MR_CHMODE_NORM (0x0u << 14) /**< \brief (DBGU_MR) Normal Mode */
#define   DBGU_MR_CHMODE_AUTO (0x1u << 14) /**< \brief (DBGU_MR) Automatic Echo */
#define   DBGU_MR_CHMODE_LOCLOOP (0x2u << 14) /**< \brief (DBGU_MR) Local Loopback */
#define   DBGU_MR_CHMODE_REMLOOP (0x3u << 14) /**< \brief (DBGU_MR) Remote Loopback */
/* -------- DBGU_IER : (DBGU Offset: 0x0008) Interrupt Enable Register -------- */
#define DBGU_IER_RXRDY (0x1u << 0) /**< \brief (DBGU_IER) Enable RXRDY Interrupt */
#define DBGU_IER_TXRDY (0x1u << 1) /**< \brief (DBGU_IER) Enable TXRDY Interrupt */
#define DBGU_IER_OVRE (0x1u << 5) /**< \brief (DBGU_IER) Enable Overrun Error Interrupt */
#define DBGU_IER_FRAME (0x1u << 6) /**< \brief (DBGU_IER) Enable Framing Error Interrupt */
#define DBGU_IER_PARE (0x1u << 7) /**< \brief (DBGU_IER) Enable Parity Error Interrupt */
#define DBGU_IER_TXEMPTY (0x1u << 9) /**< \brief (DBGU_IER) Enable TXEMPTY Interrupt */
#define DBGU_IER_COMMTX (0x1u << 30) /**< \brief (DBGU_IER) Enable COMMTX (from ARM) Interrupt */
#define DBGU_IER_COMMRX (0x1u << 31) /**< \brief (DBGU_IER) Enable COMMRX (from ARM) Interrupt */
/* -------- DBGU_IDR : (DBGU Offset: 0x000C) Interrupt Disable Register -------- */
#define DBGU_IDR_RXRDY (0x1u << 0) /**< \brief (DBGU_IDR) Disable RXRDY Interrupt */
#define DBGU_IDR_TXRDY (0x1u << 1) /**< \brief (DBGU_IDR) Disable TXRDY Interrupt */
#define DBGU_IDR_OVRE (0x1u << 5) /**< \brief (DBGU_IDR) Disable Overrun Error Interrupt */
#define DBGU_IDR_FRAME (0x1u << 6) /**< \brief (DBGU_IDR) Disable Framing Error Interrupt */
#define DBGU_IDR_PARE (0x1u << 7) /**< \brief (DBGU_IDR) Disable Parity Error Interrupt */
#define DBGU_IDR_TXEMPTY (0x1u << 9) /**< \brief (DBGU_IDR) Disable TXEMPTY Interrupt */
#define DBGU_IDR_COMMTX (0x1u << 30) /**< \brief (DBGU_IDR) Disable COMMTX (from ARM) Interrupt */
#define DBGU_IDR_COMMRX (0x1u << 31) /**< \brief (DBGU_IDR) Disable COMMRX (from ARM) Interrupt */
/* -------- DBGU_IMR : (DBGU Offset: 0x0010) Interrupt Mask Register -------- */
#define DBGU_IMR_RXRDY (0x1u << 0) /**< \brief (DBGU_IMR) Mask RXRDY Interrupt */
#define DBGU_IMR_TXRDY (0x1u << 1) /**< \brief (DBGU_IMR) Disable TXRDY Interrupt */
#define DBGU_IMR_OVRE (0x1u << 5) /**< \brief (DBGU_IMR) Mask Overrun Error Interrupt */
#define DBGU_IMR_FRAME (0x1u << 6) /**< \brief (DBGU_IMR) Mask Framing Error Interrupt */
#define DBGU_IMR_PARE (0x1u << 7) /**< \brief (DBGU_IMR) Mask Parity Error Interrupt */
#define DBGU_IMR_TXEMPTY (0x1u << 9) /**< \brief (DBGU_IMR) Mask TXEMPTY Interrupt */
#define DBGU_IMR_COMMTX (0x1u << 30) /**< \brief (DBGU_IMR) Mask COMMTX Interrupt */
#define DBGU_IMR_COMMRX (0x1u << 31) /**< \brief (DBGU_IMR) Mask COMMRX Interrupt */
/* -------- DBGU_SR : (DBGU Offset: 0x0014) Status Register -------- */
#define DBGU_SR_RXRDY (0x1u << 0) /**< \brief (DBGU_SR) Receiver Ready */
#define DBGU_SR_TXRDY (0x1u << 1) /**< \brief (DBGU_SR) Transmitter Ready */
#define DBGU_SR_OVRE (0x1u << 5) /**< \brief (DBGU_SR) Overrun Error */
#define DBGU_SR_FRAME (0x1u << 6) /**< \brief (DBGU_SR) Framing Error */
#define DBGU_SR_PARE (0x1u << 7) /**< \brief (DBGU_SR) Parity Error */
#define DBGU_SR_TXEMPTY (0x1u << 9) /**< \brief (DBGU_SR) Transmitter Empty */
#define DBGU_SR_COMMTX (0x1u << 30) /**< \brief (DBGU_SR) Debug Communication Channel Write Status */
#define DBGU_SR_COMMRX (0x1u << 31) /**< \brief (DBGU_SR) Debug Communication Channel Read Status */
/* -------- DBGU_RHR : (DBGU Offset: 0x0018) Receive Holding Register -------- */
#define DBGU_RHR_RXCHR_Pos 0
#define DBGU_RHR_RXCHR_Msk (0xffu << DBGU_RHR_RXCHR_Pos) /**< \brief (DBGU_RHR) Received Character */
/* -------- DBGU_THR : (DBGU Offset: 0x001C) Transmit Holding Register -------- */
#define DBGU_THR_TXCHR_Pos 0
#define DBGU_THR_TXCHR_Msk (0xffu << DBGU_THR_TXCHR_Pos) /**< \brief (DBGU_THR) Character to be Transmitted */
#define DBGU_THR_TXCHR(value) ((DBGU_THR_TXCHR_Msk & ((value) << DBGU_THR_TXCHR_Pos)))
/* -------- DBGU_BRGR : (DBGU Offset: 0x0020) Baud Rate Generator Register -------- */
#define DBGU_BRGR_CD_Pos 0
#define DBGU_BRGR_CD_Msk (0xffffu << DBGU_BRGR_CD_Pos) /**< \brief (DBGU_BRGR) Clock Divisor */
#define   DBGU_BRGR_CD_DISABLED (0x0u << 0) /**< \brief (DBGU_BRGR) DBGU Disabled */
#define   DBGU_BRGR_CD_MCK (0x1u << 0) /**< \brief (DBGU_BRGR) MCK */
/* -------- DBGU_CIDR : (DBGU Offset: 0x0040) Chip ID Register -------- */
#define DBGU_CIDR_VERSION_Pos 0
#define DBGU_CIDR_VERSION_Msk (0x1fu << DBGU_CIDR_VERSION_Pos) /**< \brief (DBGU_CIDR) Version of the Device */
#define DBGU_CIDR_EPROC_Pos 5
#define DBGU_CIDR_EPROC_Msk (0x7u << DBGU_CIDR_EPROC_Pos) /**< \brief (DBGU_CIDR) Embedded Processor */
#define   DBGU_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (DBGU_CIDR) ARM946ES */
#define   DBGU_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (DBGU_CIDR) ARM7TDMI */
#define   DBGU_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (DBGU_CIDR) Cortex-M3 */
#define   DBGU_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (DBGU_CIDR) ARM920T */
#define   DBGU_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (DBGU_CIDR) ARM926EJS */
#define   DBGU_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (DBGU_CIDR) Cortex-A5 */
#define DBGU_CIDR_NVPSIZ_Pos 8
#define DBGU_CIDR_NVPSIZ_Msk (0xfu << DBGU_CIDR_NVPSIZ_Pos) /**< \brief (DBGU_CIDR) Nonvolatile Program Memory Size */
#define   DBGU_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (DBGU_CIDR) None */
#define   DBGU_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (DBGU_CIDR) 8K bytes */
#define   DBGU_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (DBGU_CIDR) 16K bytes */
#define   DBGU_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (DBGU_CIDR) 32K bytes */
#define   DBGU_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (DBGU_CIDR) 64K bytes */
#define   DBGU_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (DBGU_CIDR) 128K bytes */
#define   DBGU_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (DBGU_CIDR) 256K bytes */
#define   DBGU_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (DBGU_CIDR) 512K bytes */
#define   DBGU_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (DBGU_CIDR) 1024K bytes */
#define   DBGU_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (DBGU_CIDR) 2048K bytes */
#define DBGU_CIDR_NVPSIZ2_Pos 12
#define DBGU_CIDR_NVPSIZ2_Msk (0xfu << DBGU_CIDR_NVPSIZ2_Pos) /**< \brief (DBGU_CIDR)  */
#define   DBGU_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (DBGU_CIDR) None */
#define   DBGU_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (DBGU_CIDR) 8K bytes */
#define   DBGU_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (DBGU_CIDR) 16K bytes */
#define   DBGU_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (DBGU_CIDR) 32K bytes */
#define   DBGU_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (DBGU_CIDR) 64K bytes */
#define   DBGU_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (DBGU_CIDR) 128K bytes */
#define   DBGU_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (DBGU_CIDR) 256K bytes */
#define   DBGU_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (DBGU_CIDR) 512K bytes */
#define   DBGU_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (DBGU_CIDR) 1024K bytes */
#define   DBGU_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (DBGU_CIDR) 2048K bytes */
#define DBGU_CIDR_SRAMSIZ_Pos 16
#define DBGU_CIDR_SRAMSIZ_Msk (0xfu << DBGU_CIDR_SRAMSIZ_Pos) /**< \brief (DBGU_CIDR) Internal SRAM Size */
#define   DBGU_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (DBGU_CIDR) 1K bytes */
#define   DBGU_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (DBGU_CIDR) 2K bytes */
#define   DBGU_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (DBGU_CIDR) 6K bytes */
#define   DBGU_CIDR_SRAMSIZ_112K (0x4u << 16) /**< \brief (DBGU_CIDR) 112K bytes */
#define   DBGU_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (DBGU_CIDR) 4K bytes */
#define   DBGU_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (DBGU_CIDR) 80K bytes */
#define   DBGU_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (DBGU_CIDR) 160K bytes */
#define   DBGU_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (DBGU_CIDR) 8K bytes */
#define   DBGU_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (DBGU_CIDR) 16K bytes */
#define   DBGU_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (DBGU_CIDR) 32K bytes */
#define   DBGU_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (DBGU_CIDR) 64K bytes */
#define   DBGU_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (DBGU_CIDR) 128K bytes */
#define   DBGU_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (DBGU_CIDR) 256K bytes */
#define   DBGU_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (DBGU_CIDR) 96K bytes */
#define   DBGU_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (DBGU_CIDR) 512K bytes */
#define DBGU_CIDR_ARCH_Pos 20
#define DBGU_CIDR_ARCH_Msk (0xffu << DBGU_CIDR_ARCH_Pos) /**< \brief (DBGU_CIDR) Architecture Identifier */
#define   DBGU_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (DBGU_CIDR) AT91SAM9xx Series */
#define   DBGU_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (DBGU_CIDR) AT91SAM9XExx Series */
#define   DBGU_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (DBGU_CIDR) AT91x34 Series */
#define   DBGU_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (DBGU_CIDR) CAP7 Series */
#define   DBGU_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (DBGU_CIDR) CAP9 Series */
#define   DBGU_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (DBGU_CIDR) CAP11 Series */
#define   DBGU_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (DBGU_CIDR) AT91x40 Series */
#define   DBGU_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (DBGU_CIDR) AT91x42 Series */
#define   DBGU_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (DBGU_CIDR) AT91x55 Series */
#define   DBGU_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (DBGU_CIDR) AT91SAM7Axx Series */
#define   DBGU_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (DBGU_CIDR) AT91SAM7AQxx Series */
#define   DBGU_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (DBGU_CIDR) AT91x63 Series */
#define   DBGU_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (DBGU_CIDR) AT91SAM7Sxx Series */
#define   DBGU_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (DBGU_CIDR) AT91SAM7XCxx Series */
#define   DBGU_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (DBGU_CIDR) AT91SAM7SExx Series */
#define   DBGU_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (DBGU_CIDR) AT91SAM7Lxx Series */
#define   DBGU_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (DBGU_CIDR) AT91SAM7Xxx Series */
#define   DBGU_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (DBGU_CIDR) AT91SAM7SLxx Series */
#define   DBGU_CIDR_ARCH_ATSAM3UxC (0x80u << 20) /**< \brief (DBGU_CIDR) ATSAM3UxC Series (100-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3UxE (0x81u << 20) /**< \brief (DBGU_CIDR) ATSAM3UxE Series (144-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3AxC (0x83u << 20) /**< \brief (DBGU_CIDR) ATSAM3AxC Series (100-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3XxC (0x84u << 20) /**< \brief (DBGU_CIDR) ATSAM3XxC Series (100-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3XxE (0x85u << 20) /**< \brief (DBGU_CIDR) ATSAM3XxE Series (144-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3XxG (0x86u << 20) /**< \brief (DBGU_CIDR) ATSAM3XxG Series (208/217-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3SxA (0x88u << 20) /**< \brief (DBGU_CIDR) ATSAM3SxA Series (48-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3SxB (0x89u << 20) /**< \brief (DBGU_CIDR) ATSAM3SxB Series (64-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3SxC (0x8Au << 20) /**< \brief (DBGU_CIDR) ATSAM3SxC Series (100-pin version) */
#define   DBGU_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (DBGU_CIDR) AT91x92 Series */
#define   DBGU_CIDR_ARCH_ATSAM3NxA (0x93u << 20) /**< \brief (DBGU_CIDR) ATSAM3NxA Series (48-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3NxB (0x94u << 20) /**< \brief (DBGU_CIDR) ATSAM3NxB Series (64-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3NxC (0x95u << 20) /**< \brief (DBGU_CIDR) ATSAM3NxC Series (100-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3SDxA (0x98u << 20) /**< \brief (DBGU_CIDR) ATSAM3SDxA Series (48-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3SDxB (0x99u << 20) /**< \brief (DBGU_CIDR) ATSAM3SDxB Series (64-pin version) */
#define   DBGU_CIDR_ARCH_ATSAM3SDxC (0x9Au << 20) /**< \brief (DBGU_CIDR) ATSAM3SDxC Series (100-pin version) */
#define   DBGU_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (DBGU_CIDR) AT75Cxx Series */
#define DBGU_CIDR_NVPTYP_Pos 28
#define DBGU_CIDR_NVPTYP_Msk (0x7u << DBGU_CIDR_NVPTYP_Pos) /**< \brief (DBGU_CIDR) Nonvolatile Program Memory Type */
#define   DBGU_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (DBGU_CIDR) ROM */
#define   DBGU_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (DBGU_CIDR) ROMless or on-chip Flash */
#define   DBGU_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (DBGU_CIDR) Embedded Flash Memory */
#define   DBGU_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (DBGU_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
#define   DBGU_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (DBGU_CIDR) SRAM emulating ROM */
#define DBGU_CIDR_EXT (0x1u << 31) /**< \brief (DBGU_CIDR) Extension Flag */
/* -------- DBGU_EXID : (DBGU Offset: 0x0044) Chip ID Extension Register -------- */
#define DBGU_EXID_EXID_Pos 0
#define DBGU_EXID_EXID_Msk (0xffffffffu << DBGU_EXID_EXID_Pos) /**< \brief (DBGU_EXID) Chip ID Extension */
/* -------- DBGU_FNR : (DBGU Offset: 0x0048) Force NTRST Register -------- */
#define DBGU_FNR_FNTRST (0x1u << 0) /**< \brief (DBGU_FNR) Force NTRST */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR DMA Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_DMAC DMA Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief DmacCh_num hardware registers */
typedef struct {
  RwReg       DMAC_SADDR;     /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */
  RwReg       DMAC_DADDR;     /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */
  RwReg       DMAC_DSCR;      /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */
  RwReg       DMAC_CTRLA;     /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
  RwReg       DMAC_CTRLB;     /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
  RwReg       DMAC_CFG;       /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
  RwReg       DMAC_SPIP;      /**< \brief (DmacCh_num Offset: 0x18) DMAC Channel Source Picture-in-Picture Configuration Register */
  RwReg       DMAC_DPIP;      /**< \brief (DmacCh_num Offset: 0x1C) DMAC Channel Destination Picture-in-Picture Configuration Register */
  RoReg       Reserved1[2];
} DmacCh_num;
/** \brief Dmac hardware registers */
#define DMACCH_NUM_NUMBER 8
typedef struct {
  RwReg       DMAC_GCFG;      /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */
  RwReg       DMAC_EN;        /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */
  RwReg       DMAC_SREQ;      /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
  RwReg       DMAC_CREQ;      /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
  RwReg       DMAC_LAST;      /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
  RoReg       Reserved1[1];
  WoReg       DMAC_EBCIER;    /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
  WoReg       DMAC_EBCIDR;    /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
  RoReg       DMAC_EBCIMR;    /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
  RoReg       DMAC_EBCISR;    /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
  WoReg       DMAC_CHER;      /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
  WoReg       DMAC_CHDR;      /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
  RoReg       DMAC_CHSR;      /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
  RoReg       Reserved2[2];
  DmacCh_num  DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 7 */
  RoReg       Reserved3[26];
  RwReg       DMAC_WPMR;      /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */
  RoReg       DMAC_WPSR;      /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */
} Dmac;
#endif /* __ASSEMBLY__ */
/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */
#define   DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */
#define   DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */
#define DMAC_GCFG_DICEN (0x1u << 8) /**< \brief (DMAC_GCFG) Descriptor Integrity Check */
/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN)  */
/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */
#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */
#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */
#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */
#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */
#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */
#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */
#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */
#define DMAC_SREQ_SSREQ4 (0x1u << 8) /**< \brief (DMAC_SREQ) Source Request */
#define DMAC_SREQ_DSREQ4 (0x1u << 9) /**< \brief (DMAC_SREQ) Destination Request */
#define DMAC_SREQ_SSREQ5 (0x1u << 10) /**< \brief (DMAC_SREQ) Source Request */
#define DMAC_SREQ_DSREQ5 (0x1u << 11) /**< \brief (DMAC_SREQ) Destination Request */
#define DMAC_SREQ_SSREQ6 (0x1u << 12) /**< \brief (DMAC_SREQ) Source Request */
#define DMAC_SREQ_DSREQ6 (0x1u << 13) /**< \brief (DMAC_SREQ) Destination Request */
#define DMAC_SREQ_SSREQ7 (0x1u << 14) /**< \brief (DMAC_SREQ) Source Request */
#define DMAC_SREQ_DSREQ7 (0x1u << 15) /**< \brief (DMAC_SREQ) Destination Request */
/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */
#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */
#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */
#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */
#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */
#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */
#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */
#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */
#define DMAC_CREQ_SCREQ4 (0x1u << 8) /**< \brief (DMAC_CREQ) Source Chunk Request */
#define DMAC_CREQ_DCREQ4 (0x1u << 9) /**< \brief (DMAC_CREQ) Destination Chunk Request */
#define DMAC_CREQ_SCREQ5 (0x1u << 10) /**< \brief (DMAC_CREQ) Source Chunk Request */
#define DMAC_CREQ_DCREQ5 (0x1u << 11) /**< \brief (DMAC_CREQ) Destination Chunk Request */
#define DMAC_CREQ_SCREQ6 (0x1u << 12) /**< \brief (DMAC_CREQ) Source Chunk Request */
#define DMAC_CREQ_DCREQ6 (0x1u << 13) /**< \brief (DMAC_CREQ) Destination Chunk Request */
#define DMAC_CREQ_SCREQ7 (0x1u << 14) /**< \brief (DMAC_CREQ) Source Chunk Request */
#define DMAC_CREQ_DCREQ7 (0x1u << 15) /**< \brief (DMAC_CREQ) Destination Chunk Request */
/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */
#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */
#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */
#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */
#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */
#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */
#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */
#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */
#define DMAC_LAST_SLAST4 (0x1u << 8) /**< \brief (DMAC_LAST) Source Last */
#define DMAC_LAST_DLAST4 (0x1u << 9) /**< \brief (DMAC_LAST) Destination Last */
#define DMAC_LAST_SLAST5 (0x1u << 10) /**< \brief (DMAC_LAST) Source Last */
#define DMAC_LAST_DLAST5 (0x1u << 11) /**< \brief (DMAC_LAST) Destination Last */
#define DMAC_LAST_SLAST6 (0x1u << 12) /**< \brief (DMAC_LAST) Source Last */
#define DMAC_LAST_DLAST6 (0x1u << 13) /**< \brief (DMAC_LAST) Destination Last */
#define DMAC_LAST_SLAST7 (0x1u << 14) /**< \brief (DMAC_LAST) Source Last */
#define DMAC_LAST_DLAST7 (0x1u << 15) /**< \brief (DMAC_LAST) Destination Last */
/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */
#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_BTC6 (0x1u << 6) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_BTC7 (0x1u << 7) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_CBTC6 (0x1u << 14) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_CBTC7 (0x1u << 15) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [7:0] */
#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [7:0] */
#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [7:0] */
#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [7:0] */
#define DMAC_EBCIER_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIER) Access Error [7:0] */
#define DMAC_EBCIER_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIER) Access Error [7:0] */
#define DMAC_EBCIER_ERR6 (0x1u << 22) /**< \brief (DMAC_EBCIER) Access Error [7:0] */
#define DMAC_EBCIER_ERR7 (0x1u << 23) /**< \brief (DMAC_EBCIER) Access Error [7:0] */
#define DMAC_EBCIER_DICERR0 (0x1u << 24) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIER_DICERR1 (0x1u << 25) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIER_DICERR2 (0x1u << 26) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIER_DICERR3 (0x1u << 27) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIER_DICERR4 (0x1u << 28) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIER_DICERR5 (0x1u << 29) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIER_DICERR6 (0x1u << 30) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIER_DICERR7 (0x1u << 31) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */
/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */
#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_BTC6 (0x1u << 6) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_BTC7 (0x1u << 7) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_CBTC6 (0x1u << 14) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_CBTC7 (0x1u << 15) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */
#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */
#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */
#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */
#define DMAC_EBCIDR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */
#define DMAC_EBCIDR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */
#define DMAC_EBCIDR_ERR6 (0x1u << 22) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */
#define DMAC_EBCIDR_ERR7 (0x1u << 23) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */
#define DMAC_EBCIDR_DICERR0 (0x1u << 24) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIDR_DICERR1 (0x1u << 25) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIDR_DICERR2 (0x1u << 26) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIDR_DICERR3 (0x1u << 27) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIDR_DICERR4 (0x1u << 28) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIDR_DICERR5 (0x1u << 29) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIDR_DICERR6 (0x1u << 30) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIDR_DICERR7 (0x1u << 31) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */
/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */
#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_BTC6 (0x1u << 6) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_BTC7 (0x1u << 7) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_CBTC6 (0x1u << 14) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_CBTC7 (0x1u << 15) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */
#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */
#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */
#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */
#define DMAC_EBCIMR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */
#define DMAC_EBCIMR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */
#define DMAC_EBCIMR_ERR6 (0x1u << 22) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */
#define DMAC_EBCIMR_ERR7 (0x1u << 23) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */
#define DMAC_EBCIMR_DICERR0 (0x1u << 24) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIMR_DICERR1 (0x1u << 25) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIMR_DICERR2 (0x1u << 26) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIMR_DICERR3 (0x1u << 27) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIMR_DICERR4 (0x1u << 28) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIMR_DICERR5 (0x1u << 29) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIMR_DICERR6 (0x1u << 30) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCIMR_DICERR7 (0x1u << 31) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */
/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */
#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_BTC6 (0x1u << 6) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_BTC7 (0x1u << 7) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_CBTC6 (0x1u << 14) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_CBTC7 (0x1u << 15) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */
#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [7:0] */
#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [7:0] */
#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [7:0] */
#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [7:0] */
#define DMAC_EBCISR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCISR) Access Error [7:0] */
#define DMAC_EBCISR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCISR) Access Error [7:0] */
#define DMAC_EBCISR_ERR6 (0x1u << 22) /**< \brief (DMAC_EBCISR) Access Error [7:0] */
#define DMAC_EBCISR_ERR7 (0x1u << 23) /**< \brief (DMAC_EBCISR) Access Error [7:0] */
#define DMAC_EBCISR_DICERR0 (0x1u << 24) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCISR_DICERR1 (0x1u << 25) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCISR_DICERR2 (0x1u << 26) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCISR_DICERR3 (0x1u << 27) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCISR_DICERR4 (0x1u << 28) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCISR_DICERR5 (0x1u << 29) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCISR_DICERR6 (0x1u << 30) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */
#define DMAC_EBCISR_DICERR7 (0x1u << 31) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */
/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [7:0] */
#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [7:0] */
#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [7:0] */
#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [7:0] */
#define DMAC_CHER_ENA4 (0x1u << 4) /**< \brief (DMAC_CHER) Enable [7:0] */
#define DMAC_CHER_ENA5 (0x1u << 5) /**< \brief (DMAC_CHER) Enable [7:0] */
#define DMAC_CHER_ENA6 (0x1u << 6) /**< \brief (DMAC_CHER) Enable [7:0] */
#define DMAC_CHER_ENA7 (0x1u << 7) /**< \brief (DMAC_CHER) Enable [7:0] */
#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [7:0] */
#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [7:0] */
#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [7:0] */
#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [7:0] */
#define DMAC_CHER_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHER) Suspend [7:0] */
#define DMAC_CHER_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHER) Suspend [7:0] */
#define DMAC_CHER_SUSP6 (0x1u << 14) /**< \brief (DMAC_CHER) Suspend [7:0] */
#define DMAC_CHER_SUSP7 (0x1u << 15) /**< \brief (DMAC_CHER) Suspend [7:0] */
#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [7:0] */
#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [7:0] */
#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [7:0] */
#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [7:0] */
#define DMAC_CHER_KEEP4 (0x1u << 28) /**< \brief (DMAC_CHER) Keep on [7:0] */
#define DMAC_CHER_KEEP5 (0x1u << 29) /**< \brief (DMAC_CHER) Keep on [7:0] */
#define DMAC_CHER_KEEP6 (0x1u << 30) /**< \brief (DMAC_CHER) Keep on [7:0] */
#define DMAC_CHER_KEEP7 (0x1u << 31) /**< \brief (DMAC_CHER) Keep on [7:0] */
/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [7:0] */
#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [7:0] */
#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [7:0] */
#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [7:0] */
#define DMAC_CHDR_DIS4 (0x1u << 4) /**< \brief (DMAC_CHDR) Disable [7:0] */
#define DMAC_CHDR_DIS5 (0x1u << 5) /**< \brief (DMAC_CHDR) Disable [7:0] */
#define DMAC_CHDR_DIS6 (0x1u << 6) /**< \brief (DMAC_CHDR) Disable [7:0] */
#define DMAC_CHDR_DIS7 (0x1u << 7) /**< \brief (DMAC_CHDR) Disable [7:0] */
#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [7:0] */
#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [7:0] */
#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [7:0] */
#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [7:0] */
#define DMAC_CHDR_RES4 (0x1u << 12) /**< \brief (DMAC_CHDR) Resume [7:0] */
#define DMAC_CHDR_RES5 (0x1u << 13) /**< \brief (DMAC_CHDR) Resume [7:0] */
#define DMAC_CHDR_RES6 (0x1u << 14) /**< \brief (DMAC_CHDR) Resume [7:0] */
#define DMAC_CHDR_RES7 (0x1u << 15) /**< \brief (DMAC_CHDR) Resume [7:0] */
/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [7:0] */
#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [7:0] */
#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [7:0] */
#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [7:0] */
#define DMAC_CHSR_ENA4 (0x1u << 4) /**< \brief (DMAC_CHSR) Enable [7:0] */
#define DMAC_CHSR_ENA5 (0x1u << 5) /**< \brief (DMAC_CHSR) Enable [7:0] */
#define DMAC_CHSR_ENA6 (0x1u << 6) /**< \brief (DMAC_CHSR) Enable [7:0] */
#define DMAC_CHSR_ENA7 (0x1u << 7) /**< \brief (DMAC_CHSR) Enable [7:0] */
#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [7:0] */
#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [7:0] */
#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [7:0] */
#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [7:0] */
#define DMAC_CHSR_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHSR) Suspend [7:0] */
#define DMAC_CHSR_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHSR) Suspend [7:0] */
#define DMAC_CHSR_SUSP6 (0x1u << 14) /**< \brief (DMAC_CHSR) Suspend [7:0] */
#define DMAC_CHSR_SUSP7 (0x1u << 15) /**< \brief (DMAC_CHSR) Suspend [7:0] */
#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [7:0] */
#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [7:0] */
#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [7:0] */
#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [7:0] */
#define DMAC_CHSR_EMPT4 (0x1u << 20) /**< \brief (DMAC_CHSR) Empty [7:0] */
#define DMAC_CHSR_EMPT5 (0x1u << 21) /**< \brief (DMAC_CHSR) Empty [7:0] */
#define DMAC_CHSR_EMPT6 (0x1u << 22) /**< \brief (DMAC_CHSR) Empty [7:0] */
#define DMAC_CHSR_EMPT7 (0x1u << 23) /**< \brief (DMAC_CHSR) Empty [7:0] */
#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [7:0] */
#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [7:0] */
#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [7:0] */
#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [7:0] */
#define DMAC_CHSR_STAL4 (0x1u << 28) /**< \brief (DMAC_CHSR) Stalled [7:0] */
#define DMAC_CHSR_STAL5 (0x1u << 29) /**< \brief (DMAC_CHSR) Stalled [7:0] */
#define DMAC_CHSR_STAL6 (0x1u << 30) /**< \brief (DMAC_CHSR) Stalled [7:0] */
#define DMAC_CHSR_STAL7 (0x1u << 31) /**< \brief (DMAC_CHSR) Stalled [7:0] */
/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */
#define DMAC_SADDR_SADDR_Pos 0
#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */
#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos)))
/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */
#define DMAC_DADDR_DADDR_Pos 0
#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */
#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos)))
/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
#define DMAC_DSCR_DSCR_IF_Pos 0
#define DMAC_DSCR_DSCR_IF_Msk (0x3u << DMAC_DSCR_DSCR_IF_Pos) /**< \brief (DMAC_DSCR)  */
#define   DMAC_DSCR_DSCR_IF_AHB_IF0 (0x0u << 0) /**< \brief (DMAC_DSCR) The buffer transfer descriptor is fetched via AHB-Lite Interface 0 */
#define   DMAC_DSCR_DSCR_IF_AHB_IF1 (0x1u << 0) /**< \brief (DMAC_DSCR) The buffer transfer descriptor is fetched via AHB-Lite Interface 1 */
#define   DMAC_DSCR_DSCR_IF_AHB_IF2 (0x2u << 0) /**< \brief (DMAC_DSCR) The buffer transfer descriptor is fetched via AHB-Lite Interface 2 */
#define DMAC_DSCR_DSCR_Pos 2
#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */
#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos)))
/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
#define DMAC_CTRLA_BTSIZE_Pos 0
#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */
#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
#define DMAC_CTRLA_SCSIZE_Pos 16
#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) Source Chunk Transfer Size. */
#define   DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) /**< \brief (DMAC_CTRLA) 1 data transferred */
#define   DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) /**< \brief (DMAC_CTRLA) 4 data transferred */
#define   DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) /**< \brief (DMAC_CTRLA) 8 data transferred */
#define   DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) /**< \brief (DMAC_CTRLA) 16 data transferred */
#define   DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) /**< \brief (DMAC_CTRLA) 32 data transferred */
#define   DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) /**< \brief (DMAC_CTRLA) 64 data transferred */
#define   DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) /**< \brief (DMAC_CTRLA) 128 data transferred */
#define   DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) /**< \brief (DMAC_CTRLA) 256 data transferred */
#define DMAC_CTRLA_DCSIZE_Pos 20
#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) Destination Chunk Transfer Size */
#define   DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) /**< \brief (DMAC_CTRLA) 1 data transferred */
#define   DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) /**< \brief (DMAC_CTRLA) 4 data transferred */
#define   DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) /**< \brief (DMAC_CTRLA) 8 data transferred */
#define   DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) /**< \brief (DMAC_CTRLA) 16 data transferred */
#define   DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) /**< \brief (DMAC_CTRLA) 32 data transferred */
#define   DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) /**< \brief (DMAC_CTRLA) 64 data transferred */
#define   DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) /**< \brief (DMAC_CTRLA) 128 data transferred */
#define   DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) /**< \brief (DMAC_CTRLA) 256 data transferred */
#define DMAC_CTRLA_SRC_WIDTH_Pos 24
#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */
#define   DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
#define   DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
#define   DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
#define   DMAC_CTRLA_SRC_WIDTH_DWORD (0x3u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 64-bit width */
#define DMAC_CTRLA_DST_WIDTH_Pos 28
#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */
#define   DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
#define   DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
#define   DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
#define   DMAC_CTRLA_DST_WIDTH_DWORD (0x3u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 64-bit width */
#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA)  */
/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
#define DMAC_CTRLB_SIF_Pos 0
#define DMAC_CTRLB_SIF_Msk (0x3u << DMAC_CTRLB_SIF_Pos) /**< \brief (DMAC_CTRLB) Source Interface Selection Field */
#define   DMAC_CTRLB_SIF_AHB_IF0 (0x0u << 0) /**< \brief (DMAC_CTRLB) The source transfer is done via AHB-Lite Interface 0 */
#define   DMAC_CTRLB_SIF_AHB_IF1 (0x1u << 0) /**< \brief (DMAC_CTRLB) The source transfer is done via AHB-Lite Interface 1 */
#define   DMAC_CTRLB_SIF_AHB_IF2 (0x2u << 0) /**< \brief (DMAC_CTRLB) The source transfer is done via AHB-Lite Interface 2 */
#define DMAC_CTRLB_DIF_Pos 4
#define DMAC_CTRLB_DIF_Msk (0x3u << DMAC_CTRLB_DIF_Pos) /**< \brief (DMAC_CTRLB) Destination Interface Selection Field */
#define   DMAC_CTRLB_DIF_AHB_IF0 (0x0u << 4) /**< \brief (DMAC_CTRLB) The destination transfer is done via AHB-Lite Interface 0 */
#define   DMAC_CTRLB_DIF_AHB_IF1 (0x1u << 4) /**< \brief (DMAC_CTRLB) The destination transfer is done via AHB-Lite Interface 1 */
#define   DMAC_CTRLB_DIF_AHB_IF2 (0x2u << 4) /**< \brief (DMAC_CTRLB) The destination transfer is done via AHB-Lite Interface 2 */
#define DMAC_CTRLB_SRC_PIP (0x1u << 8) /**< \brief (DMAC_CTRLB) Source Picture-in-Picture Mode */
#define   DMAC_CTRLB_SRC_PIP_DISABLE (0x0u << 8) /**< \brief (DMAC_CTRLB) Picture-in-Picture mode is disabled. The source data area is contiguous. */
#define   DMAC_CTRLB_SRC_PIP_ENABLE (0x1u << 8) /**< \brief (DMAC_CTRLB) Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount. */
#define DMAC_CTRLB_DST_PIP (0x1u << 12) /**< \brief (DMAC_CTRLB) Destination Picture-in-Picture Mode */
#define   DMAC_CTRLB_DST_PIP_DISABLE (0x0u << 12) /**< \brief (DMAC_CTRLB) Picture-in-Picture mode is disabled. The Destination data area is contiguous. */
#define   DMAC_CTRLB_DST_PIP_ENABLE (0x1u << 12) /**< \brief (DMAC_CTRLB) Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount. */
#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */
#define   DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */
#define   DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */
#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */
#define   DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */
#define   DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */
#define DMAC_CTRLB_FC_Pos 21
#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */
#define   DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */
#define   DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */
#define   DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */
#define   DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */
#define DMAC_CTRLB_SRC_INCR_Pos 24
#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */
#define   DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */
#define   DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */
#define   DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */
#define DMAC_CTRLB_DST_INCR_Pos 28
#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */
#define   DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */
#define   DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */
#define   DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */
#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB)  */
#define DMAC_CTRLB_AUTO (0x1u << 31) /**< \brief (DMAC_CTRLB) Automatic Multiple Buffer Transfer */
#define   DMAC_CTRLB_AUTO_DISABLE (0x0u << 31) /**< \brief (DMAC_CTRLB) Automatic multiple buffer transfer is disabled. */
#define   DMAC_CTRLB_AUTO_ENABLE (0x1u << 31) /**< \brief (DMAC_CTRLB) Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred. */
/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
#define DMAC_CFG_SRC_PER_Pos 0
#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */
#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
#define DMAC_CFG_DST_PER_Pos 4
#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */
#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
#define DMAC_CFG_SRC_REP (0x1u << 8) /**< \brief (DMAC_CFG) Source Reloaded from Previous */
#define   DMAC_CFG_SRC_REP_CONTIGUOUS_ADDR (0x0u << 8) /**< \brief (DMAC_CFG) When automatic mode is activated, source address is contiguous between two buffers. */
#define   DMAC_CFG_SRC_REP_RELOAD_ADDR (0x1u << 8) /**< \brief (DMAC_CFG) When automatic mode is activated, the source address and the control register are reloaded from previous transfer. */
#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */
#define   DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
#define   DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
#define DMAC_CFG_SRC_PER_MSB_Pos 10
#define DMAC_CFG_SRC_PER_MSB_Msk (0x3u << DMAC_CFG_SRC_PER_MSB_Pos) /**< \brief (DMAC_CFG) SRC_PER Most Significant Bits */
#define DMAC_CFG_SRC_PER_MSB(value) ((DMAC_CFG_SRC_PER_MSB_Msk & ((value) << DMAC_CFG_SRC_PER_MSB_Pos)))
#define DMAC_CFG_DST_REP (0x1u << 12) /**< \brief (DMAC_CFG) Destination Reloaded from Previous */
#define   DMAC_CFG_DST_REP_CONTIGUOUS_ADDR (0x0u << 12) /**< \brief (DMAC_CFG) When automatic mode is activated, destination address is contiguous between two buffers. */
#define   DMAC_CFG_DST_REP_RELOAD_ADDR (0x1u << 12) /**< \brief (DMAC_CFG) When automatic mode is activated, the destination and the control register are reloaded from the pre-vious transfer. */
#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */
#define   DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
#define   DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
#define DMAC_CFG_DST_PER_MSB_Pos 14
#define DMAC_CFG_DST_PER_MSB_Msk (0x3u << DMAC_CFG_DST_PER_MSB_Pos) /**< \brief (DMAC_CFG) DST_PER Most Significant Bits */
#define DMAC_CFG_DST_PER_MSB(value) ((DMAC_CFG_DST_PER_MSB_Msk & ((value) << DMAC_CFG_DST_PER_MSB_Pos)))
#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */
#define   DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */
#define   DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */
#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */
#define   DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */
#define   DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */
#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */
#define   DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */
#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */
#define   DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */
#define   DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */
#define DMAC_CFG_AHB_PROT_Pos 24
#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */
#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
#define DMAC_CFG_FIFOCFG_Pos 28
#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */
#define   DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */
#define   DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */
#define   DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */
/* -------- DMAC_SPIP : (DMAC Offset: N/A) DMAC Channel Source Picture-in-Picture Configuration Register -------- */
#define DMAC_SPIP_SPIP_HOLE_Pos 0
#define DMAC_SPIP_SPIP_HOLE_Msk (0xffffu << DMAC_SPIP_SPIP_HOLE_Pos) /**< \brief (DMAC_SPIP) Source Picture-in-Picture Hole */
#define DMAC_SPIP_SPIP_HOLE(value) ((DMAC_SPIP_SPIP_HOLE_Msk & ((value) << DMAC_SPIP_SPIP_HOLE_Pos)))
#define DMAC_SPIP_SPIP_BOUNDARY_Pos 16
#define DMAC_SPIP_SPIP_BOUNDARY_Msk (0x3ffu << DMAC_SPIP_SPIP_BOUNDARY_Pos) /**< \brief (DMAC_SPIP) Source Picture-in-Picture Boundary */
#define DMAC_SPIP_SPIP_BOUNDARY(value) ((DMAC_SPIP_SPIP_BOUNDARY_Msk & ((value) << DMAC_SPIP_SPIP_BOUNDARY_Pos)))
/* -------- DMAC_DPIP : (DMAC Offset: N/A) DMAC Channel Destination Picture-in-Picture Configuration Register -------- */
#define DMAC_DPIP_DPIP_HOLE_Pos 0
#define DMAC_DPIP_DPIP_HOLE_Msk (0xffffu << DMAC_DPIP_DPIP_HOLE_Pos) /**< \brief (DMAC_DPIP) Destination Picture-in-Picture Hole */
#define DMAC_DPIP_DPIP_HOLE(value) ((DMAC_DPIP_DPIP_HOLE_Msk & ((value) << DMAC_DPIP_DPIP_HOLE_Pos)))
#define DMAC_DPIP_DPIP_BOUNDARY_Pos 16
#define DMAC_DPIP_DPIP_BOUNDARY_Msk (0x3ffu << DMAC_DPIP_DPIP_BOUNDARY_Pos) /**< \brief (DMAC_DPIP) Destination Picture-in-Picture Boundary */
#define DMAC_DPIP_DPIP_BOUNDARY(value) ((DMAC_DPIP_DPIP_BOUNDARY_Msk & ((value) << DMAC_DPIP_DPIP_BOUNDARY_Pos)))
/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */
#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */
#define DMAC_WPMR_WPKEY_Pos 8
#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */
#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos)))
/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */
#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */
#define DMAC_WPSR_WPVSRC_Pos 8
#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_EMAC Ethernet MAC 10/100 */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief EmacSa hardware registers */
typedef struct {
  RwReg   EMAC_SAxB;    /**< \brief (EmacSa Offset: 0x0) Specific Address 1 Bottom Register */
  RwReg   EMAC_SAxT;    /**< \brief (EmacSa Offset: 0x4) Specific Address 1 Top Register */
} EmacSa;
/** \brief Emac hardware registers */
#define EMACSA_NUMBER 4
typedef struct {
  RwReg   EMAC_NCR;     /**< \brief (Emac Offset: 0x00) Network Control Register */
  RwReg   EMAC_NCFGR;   /**< \brief (Emac Offset: 0x04) Network Configuration Register */
  RoReg   EMAC_NSR;     /**< \brief (Emac Offset: 0x08) Network Status Register */
  RoReg   Reserved1[2];
  RwReg   EMAC_TSR;     /**< \brief (Emac Offset: 0x14) Transmit Status Register */
  RwReg   EMAC_RBQP;    /**< \brief (Emac Offset: 0x18) Receive Buffer Queue Pointer Register */
  RwReg   EMAC_TBQP;    /**< \brief (Emac Offset: 0x1C) Transmit Buffer Queue Pointer Register */
  RwReg   EMAC_RSR;     /**< \brief (Emac Offset: 0x20) Receive Status Register */
  RwReg   EMAC_ISR;     /**< \brief (Emac Offset: 0x24) Interrupt Status Register */
  WoReg   EMAC_IER;     /**< \brief (Emac Offset: 0x28) Interrupt Enable Register */
  WoReg   EMAC_IDR;     /**< \brief (Emac Offset: 0x2C) Interrupt Disable Register */
  RoReg   EMAC_IMR;     /**< \brief (Emac Offset: 0x30) Interrupt Mask Register */
  RwReg   EMAC_MAN;     /**< \brief (Emac Offset: 0x34) Phy Maintenance Register */
  RwReg   EMAC_PTR;     /**< \brief (Emac Offset: 0x38) Pause Time Register */
  RwReg   EMAC_PFR;     /**< \brief (Emac Offset: 0x3C) Pause Frames Received Register */
  RwReg   EMAC_FTO;     /**< \brief (Emac Offset: 0x40) Frames Transmitted Ok Register */
  RwReg   EMAC_SCF;     /**< \brief (Emac Offset: 0x44) Single Collision Frames Register */
  RwReg   EMAC_MCF;     /**< \brief (Emac Offset: 0x48) Multiple Collision Frames Register */
  RwReg   EMAC_FRO;     /**< \brief (Emac Offset: 0x4C) Frames Received Ok Register */
  RwReg   EMAC_FCSE;    /**< \brief (Emac Offset: 0x50) Frame Check Sequence Errors Register */
  RwReg   EMAC_ALE;     /**< \brief (Emac Offset: 0x54) Alignment Errors Register */
  RwReg   EMAC_DTF;     /**< \brief (Emac Offset: 0x58) Deferred Transmission Frames Register */
  RwReg   EMAC_LCOL;    /**< \brief (Emac Offset: 0x5C) Late Collisions Register */
  RwReg   EMAC_ECOL;    /**< \brief (Emac Offset: 0x60) Excessive Collisions Register */
  RwReg   EMAC_TUND;    /**< \brief (Emac Offset: 0x64) Transmit Underrun Errors Register */
  RwReg   EMAC_CSE;     /**< \brief (Emac Offset: 0x68) Carrier Sense Errors Register */
  RwReg   EMAC_RRE;     /**< \brief (Emac Offset: 0x6C) Receive Resource Errors Register */
  RwReg   EMAC_ROV;     /**< \brief (Emac Offset: 0x70) Receive Overrun Errors Register */
  RwReg   EMAC_RSE;     /**< \brief (Emac Offset: 0x74) Receive Symbol Errors Register */
  RwReg   EMAC_ELE;     /**< \brief (Emac Offset: 0x78) Excessive Length Errors Register */
  RwReg   EMAC_RJA;     /**< \brief (Emac Offset: 0x7C) Receive Jabbers Register */
  RwReg   EMAC_USF;     /**< \brief (Emac Offset: 0x80) Undersize Frames Register */
  RwReg   EMAC_STE;     /**< \brief (Emac Offset: 0x84) SQE Test Errors Register */
  RwReg   EMAC_RLE;     /**< \brief (Emac Offset: 0x88) Received Length Field Mismatch Register */
  RoReg   Reserved2[1];
  RwReg   EMAC_HRB;     /**< \brief (Emac Offset: 0x90) Hash Register Bottom [31:0] Register */
  RwReg   EMAC_HRT;     /**< \brief (Emac Offset: 0x94) Hash Register Top [63:32] Register */
  EmacSa  EMAC_SA[EMACSA_NUMBER]; /**< \brief (Emac Offset: 0x98) sa = 1 .. 4 */
  RwReg   EMAC_TID;     /**< \brief (Emac Offset: 0xB8) Type ID Checking Register */
  RoReg   Reserved3[1];
  RwReg   EMAC_USRIO;   /**< \brief (Emac Offset: 0xC0) User Input/Output Register */
} Emac;
#endif /* __ASSEMBLY__ */
/* -------- EMAC_NCR : (EMAC Offset: 0x00) Network Control Register -------- */
#define EMAC_NCR_LB (0x1u << 0) /**< \brief (EMAC_NCR) LoopBack */
#define EMAC_NCR_LLB (0x1u << 1) /**< \brief (EMAC_NCR) Loopback local */
#define EMAC_NCR_RE (0x1u << 2) /**< \brief (EMAC_NCR) Receive enable */
#define EMAC_NCR_TE (0x1u << 3) /**< \brief (EMAC_NCR) Transmit enable */
#define EMAC_NCR_MPE (0x1u << 4) /**< \brief (EMAC_NCR) Management port enable */
#define EMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (EMAC_NCR) Clear statistics registers */
#define EMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (EMAC_NCR) Increment statistics registers */
#define EMAC_NCR_WESTAT (0x1u << 7) /**< \brief (EMAC_NCR) Write enable for statistics registers */
#define EMAC_NCR_BP (0x1u << 8) /**< \brief (EMAC_NCR) Back pressure */
#define EMAC_NCR_TSTART (0x1u << 9) /**< \brief (EMAC_NCR) Start transmission */
#define EMAC_NCR_THALT (0x1u << 10) /**< \brief (EMAC_NCR) Transmit halt */
/* -------- EMAC_NCFGR : (EMAC Offset: 0x04) Network Configuration Register -------- */
#define EMAC_NCFGR_SPD (0x1u << 0) /**< \brief (EMAC_NCFGR) Speed */
#define EMAC_NCFGR_FD (0x1u << 1) /**< \brief (EMAC_NCFGR) Full Duplex */
#define EMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (EMAC_NCFGR) Jumbo Frames */
#define EMAC_NCFGR_CAF (0x1u << 4) /**< \brief (EMAC_NCFGR) Copy All Frames */
#define EMAC_NCFGR_NBC (0x1u << 5) /**< \brief (EMAC_NCFGR) No Broadcast */
#define EMAC_NCFGR_MTI (0x1u << 6) /**< \brief (EMAC_NCFGR) Multicast Hash Enable */
#define EMAC_NCFGR_UNI (0x1u << 7) /**< \brief (EMAC_NCFGR) Unicast Hash Enable */
#define EMAC_NCFGR_BIG (0x1u << 8) /**< \brief (EMAC_NCFGR) Receive 1536 bytes frames */
#define EMAC_NCFGR_CLK_Pos 10
#define EMAC_NCFGR_CLK_Msk (0x3u << EMAC_NCFGR_CLK_Pos) /**< \brief (EMAC_NCFGR) MDC clock divider */
#define   EMAC_NCFGR_CLK_MCK_8 (0x0u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz). */
#define   EMAC_NCFGR_CLK_MCK_16 (0x1u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz). */
#define   EMAC_NCFGR_CLK_MCK_32 (0x2u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz). */
#define   EMAC_NCFGR_CLK_MCK_64 (0x3u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz). */
#define EMAC_NCFGR_RTY (0x1u << 12) /**< \brief (EMAC_NCFGR) Retry test */
#define EMAC_NCFGR_PAE (0x1u << 13) /**< \brief (EMAC_NCFGR) Pause Enable */
#define EMAC_NCFGR_RBOF_Pos 14
#define EMAC_NCFGR_RBOF_Msk (0x3u << EMAC_NCFGR_RBOF_Pos) /**< \brief (EMAC_NCFGR) Receive Buffer Offset */
#define   EMAC_NCFGR_RBOF_OFFSET_0 (0x0u << 14) /**< \brief (EMAC_NCFGR) No offset from start of receive buffer. */
#define   EMAC_NCFGR_RBOF_OFFSET_1 (0x1u << 14) /**< \brief (EMAC_NCFGR) One-byte offset from start of receive buffer. */
#define   EMAC_NCFGR_RBOF_OFFSET_2 (0x2u << 14) /**< \brief (EMAC_NCFGR) Two-byte offset from start of receive buffer. */
#define   EMAC_NCFGR_RBOF_OFFSET_3 (0x3u << 14) /**< \brief (EMAC_NCFGR) Three-byte offset from start of receive buffer. */
#define EMAC_NCFGR_RLCE (0x1u << 16) /**< \brief (EMAC_NCFGR) Receive Length field Checking Enable */
#define EMAC_NCFGR_DRFCS (0x1u << 17) /**< \brief (EMAC_NCFGR) Discard Receive FCS */
#define EMAC_NCFGR_EFRHD (0x1u << 18) /**< \brief (EMAC_NCFGR)  */
#define EMAC_NCFGR_IRXFCS (0x1u << 19) /**< \brief (EMAC_NCFGR) Ignore RX FCS */
/* -------- EMAC_NSR : (EMAC Offset: 0x08) Network Status Register -------- */
#define EMAC_NSR_MDIO (0x1u << 1) /**< \brief (EMAC_NSR)  */
#define EMAC_NSR_IDLE (0x1u << 2) /**< \brief (EMAC_NSR)  */
/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
#define EMAC_TSR_UBR (0x1u << 0) /**< \brief (EMAC_TSR) Used Bit Read */
#define EMAC_TSR_COL (0x1u << 1) /**< \brief (EMAC_TSR) Collision Occurred */
#define EMAC_TSR_RLES (0x1u << 2) /**< \brief (EMAC_TSR) Retry Limit exceeded */
#define EMAC_TSR_TGO (0x1u << 3) /**< \brief (EMAC_TSR) Transmit Go */
#define EMAC_TSR_BEX (0x1u << 4) /**< \brief (EMAC_TSR) Buffers exhausted mid frame */
#define EMAC_TSR_COMP (0x1u << 5) /**< \brief (EMAC_TSR) Transmit Complete */
#define EMAC_TSR_UND (0x1u << 6) /**< \brief (EMAC_TSR) Transmit Underrun */
/* -------- EMAC_RBQP : (EMAC Offset: 0x18) Receive Buffer Queue Pointer Register -------- */
#define EMAC_RBQP_ADDR_Pos 2
#define EMAC_RBQP_ADDR_Msk (0x3fffffffu << EMAC_RBQP_ADDR_Pos) /**< \brief (EMAC_RBQP) Receive buffer queue pointer address */
#define EMAC_RBQP_ADDR(value) ((EMAC_RBQP_ADDR_Msk & ((value) << EMAC_RBQP_ADDR_Pos)))
/* -------- EMAC_TBQP : (EMAC Offset: 0x1C) Transmit Buffer Queue Pointer Register -------- */
#define EMAC_TBQP_ADDR_Pos 2
#define EMAC_TBQP_ADDR_Msk (0x3fffffffu << EMAC_TBQP_ADDR_Pos) /**< \brief (EMAC_TBQP) Transmit buffer queue pointer address */
#define EMAC_TBQP_ADDR(value) ((EMAC_TBQP_ADDR_Msk & ((value) << EMAC_TBQP_ADDR_Pos)))
/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
#define EMAC_RSR_BNA (0x1u << 0) /**< \brief (EMAC_RSR) Buffer Not Available */
#define EMAC_RSR_REC (0x1u << 1) /**< \brief (EMAC_RSR) Frame Received */
#define EMAC_RSR_OVR (0x1u << 2) /**< \brief (EMAC_RSR) Receive Overrun */
/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
#define EMAC_ISR_MFD (0x1u << 0) /**< \brief (EMAC_ISR) Management Frame Done */
#define EMAC_ISR_RCOMP (0x1u << 1) /**< \brief (EMAC_ISR) Receive Complete */
#define EMAC_ISR_RXUBR (0x1u << 2) /**< \brief (EMAC_ISR) Receive Used Bit Read */
#define EMAC_ISR_TXUBR (0x1u << 3) /**< \brief (EMAC_ISR) Transmit Used Bit Read */
#define EMAC_ISR_TUND (0x1u << 4) /**< \brief (EMAC_ISR) Ethernet Transmit Buffer Underrun */
#define EMAC_ISR_RLEX (0x1u << 5) /**< \brief (EMAC_ISR) Retry Limit Exceeded */
#define EMAC_ISR_TXERR (0x1u << 6) /**< \brief (EMAC_ISR) Transmit Error */
#define EMAC_ISR_TCOMP (0x1u << 7) /**< \brief (EMAC_ISR) Transmit Complete */
#define EMAC_ISR_ROVR (0x1u << 10) /**< \brief (EMAC_ISR) Receive Overrun */
#define EMAC_ISR_HRESP (0x1u << 11) /**< \brief (EMAC_ISR) Hresp not OK */
#define EMAC_ISR_PFRE (0x1u << 12) /**< \brief (EMAC_ISR) Pause Frame Received */
#define EMAC_ISR_PTZ (0x1u << 13) /**< \brief (EMAC_ISR) Pause Time Zero */
#define EMAC_ISR_WOL (0x1u << 14) /**< \brief (EMAC_ISR) Wake On LAN */
/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
#define EMAC_IER_MFD (0x1u << 0) /**< \brief (EMAC_IER) Management Frame sent */
#define EMAC_IER_RCOMP (0x1u << 1) /**< \brief (EMAC_IER) Receive Complete */
#define EMAC_IER_RXUBR (0x1u << 2) /**< \brief (EMAC_IER) Receive Used Bit Read */
#define EMAC_IER_TXUBR (0x1u << 3) /**< \brief (EMAC_IER) Transmit Used Bit Read */
#define EMAC_IER_TUND (0x1u << 4) /**< \brief (EMAC_IER) Ethernet Transmit Buffer Underrun */
#define EMAC_IER_RLE (0x1u << 5) /**< \brief (EMAC_IER) Retry Limit Exceeded */
#define EMAC_IER_TXERR (0x1u << 6) /**< \brief (EMAC_IER)  */
#define EMAC_IER_TCOMP (0x1u << 7) /**< \brief (EMAC_IER) Transmit Complete */
#define EMAC_IER_ROVR (0x1u << 10) /**< \brief (EMAC_IER) Receive Overrun */
#define EMAC_IER_HRESP (0x1u << 11) /**< \brief (EMAC_IER) Hresp not OK */
#define EMAC_IER_PFR (0x1u << 12) /**< \brief (EMAC_IER) Pause Frame Received */
#define EMAC_IER_PTZ (0x1u << 13) /**< \brief (EMAC_IER) Pause Time Zero */
#define EMAC_IER_WOL (0x1u << 14) /**< \brief (EMAC_IER) Wake On LAN */
/* -------- EMAC_IDR : (EMAC Offset: 0x2C) Interrupt Disable Register -------- */
#define EMAC_IDR_MFD (0x1u << 0) /**< \brief (EMAC_IDR) Management Frame sent */
#define EMAC_IDR_RCOMP (0x1u << 1) /**< \brief (EMAC_IDR) Receive Complete */
#define EMAC_IDR_RXUBR (0x1u << 2) /**< \brief (EMAC_IDR) Receive Used Bit Read */
#define EMAC_IDR_TXUBR (0x1u << 3) /**< \brief (EMAC_IDR) Transmit Used Bit Read */
#define EMAC_IDR_TUND (0x1u << 4) /**< \brief (EMAC_IDR) Ethernet Transmit Buffer Underrun */
#define EMAC_IDR_RLE (0x1u << 5) /**< \brief (EMAC_IDR) Retry Limit Exceeded */
#define EMAC_IDR_TXERR (0x1u << 6) /**< \brief (EMAC_IDR)  */
#define EMAC_IDR_TCOMP (0x1u << 7) /**< \brief (EMAC_IDR) Transmit Complete */
#define EMAC_IDR_ROVR (0x1u << 10) /**< \brief (EMAC_IDR) Receive Overrun */
#define EMAC_IDR_HRESP (0x1u << 11) /**< \brief (EMAC_IDR) Hresp not OK */
#define EMAC_IDR_PFR (0x1u << 12) /**< \brief (EMAC_IDR) Pause Frame Received */
#define EMAC_IDR_PTZ (0x1u << 13) /**< \brief (EMAC_IDR) Pause Time Zero */
#define EMAC_IDR_WOL (0x1u << 14) /**< \brief (EMAC_IDR) Wake On LAN */
/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
#define EMAC_IMR_MFD (0x1u << 0) /**< \brief (EMAC_IMR) Management Frame sent */
#define EMAC_IMR_RCOMP (0x1u << 1) /**< \brief (EMAC_IMR) Receive Complete */
#define EMAC_IMR_RXUBR (0x1u << 2) /**< \brief (EMAC_IMR) Receive Used Bit Read */
#define EMAC_IMR_TXUBR (0x1u << 3) /**< \brief (EMAC_IMR) Transmit Used Bit Read */
#define EMAC_IMR_TUND (0x1u << 4) /**< \brief (EMAC_IMR) Ethernet Transmit Buffer Underrun */
#define EMAC_IMR_RLE (0x1u << 5) /**< \brief (EMAC_IMR) Retry Limit Exceeded */
#define EMAC_IMR_TXERR (0x1u << 6) /**< \brief (EMAC_IMR)  */
#define EMAC_IMR_TCOMP (0x1u << 7) /**< \brief (EMAC_IMR) Transmit Complete */
#define EMAC_IMR_ROVR (0x1u << 10) /**< \brief (EMAC_IMR) Receive Overrun */
#define EMAC_IMR_HRESP (0x1u << 11) /**< \brief (EMAC_IMR) Hresp not OK */
#define EMAC_IMR_PFR (0x1u << 12) /**< \brief (EMAC_IMR) Pause Frame Received */
#define EMAC_IMR_PTZ (0x1u << 13) /**< \brief (EMAC_IMR) Pause Time Zero */
#define EMAC_IMR_WOL (0x1u << 14) /**< \brief (EMAC_IMR) Wake On LAN */
/* -------- EMAC_MAN : (EMAC Offset: 0x34) Phy Maintenance Register -------- */
#define EMAC_MAN_DATA_Pos 0
#define EMAC_MAN_DATA_Msk (0xffffu << EMAC_MAN_DATA_Pos) /**< \brief (EMAC_MAN)  */
#define EMAC_MAN_DATA(value) ((EMAC_MAN_DATA_Msk & ((value) << EMAC_MAN_DATA_Pos)))
#define EMAC_MAN_CODE_Pos 16
#define EMAC_MAN_CODE_Msk (0x3u << EMAC_MAN_CODE_Pos) /**< \brief (EMAC_MAN)  */
#define EMAC_MAN_CODE(value) ((EMAC_MAN_CODE_Msk & ((value) << EMAC_MAN_CODE_Pos)))
#define EMAC_MAN_REGA_Pos 18
#define EMAC_MAN_REGA_Msk (0x1fu << EMAC_MAN_REGA_Pos) /**< \brief (EMAC_MAN) Register Address */
#define EMAC_MAN_REGA(value) ((EMAC_MAN_REGA_Msk & ((value) << EMAC_MAN_REGA_Pos)))
#define EMAC_MAN_PHYA_Pos 23
#define EMAC_MAN_PHYA_Msk (0x1fu << EMAC_MAN_PHYA_Pos) /**< \brief (EMAC_MAN) PHY Address */
#define EMAC_MAN_PHYA(value) ((EMAC_MAN_PHYA_Msk & ((value) << EMAC_MAN_PHYA_Pos)))
#define EMAC_MAN_RW_Pos 28
#define EMAC_MAN_RW_Msk (0x3u << EMAC_MAN_RW_Pos) /**< \brief (EMAC_MAN) Read-write */
#define EMAC_MAN_RW(value) ((EMAC_MAN_RW_Msk & ((value) << EMAC_MAN_RW_Pos)))
#define EMAC_MAN_SOF_Pos 30
#define EMAC_MAN_SOF_Msk (0x3u << EMAC_MAN_SOF_Pos) /**< \brief (EMAC_MAN) Start of frame */
#define EMAC_MAN_SOF(value) ((EMAC_MAN_SOF_Msk & ((value) << EMAC_MAN_SOF_Pos)))
/* -------- EMAC_PTR : (EMAC Offset: 0x38) Pause Time Register -------- */
#define EMAC_PTR_PTIME_Pos 0
#define EMAC_PTR_PTIME_Msk (0xffffu << EMAC_PTR_PTIME_Pos) /**< \brief (EMAC_PTR) Pause Time */
#define EMAC_PTR_PTIME(value) ((EMAC_PTR_PTIME_Msk & ((value) << EMAC_PTR_PTIME_Pos)))
/* -------- EMAC_PFR : (EMAC Offset: 0x3C) Pause Frames Received Register -------- */
#define EMAC_PFR_FROK_Pos 0
#define EMAC_PFR_FROK_Msk (0xffffu << EMAC_PFR_FROK_Pos) /**< \brief (EMAC_PFR) Pause Frames received OK */
#define EMAC_PFR_FROK(value) ((EMAC_PFR_FROK_Msk & ((value) << EMAC_PFR_FROK_Pos)))
/* -------- EMAC_FTO : (EMAC Offset: 0x40) Frames Transmitted Ok Register -------- */
#define EMAC_FTO_FTOK_Pos 0
#define EMAC_FTO_FTOK_Msk (0xffffffu << EMAC_FTO_FTOK_Pos) /**< \brief (EMAC_FTO) Frames Transmitted OK */
#define EMAC_FTO_FTOK(value) ((EMAC_FTO_FTOK_Msk & ((value) << EMAC_FTO_FTOK_Pos)))
/* -------- EMAC_SCF : (EMAC Offset: 0x44) Single Collision Frames Register -------- */
#define EMAC_SCF_SCF_Pos 0
#define EMAC_SCF_SCF_Msk (0xffffu << EMAC_SCF_SCF_Pos) /**< \brief (EMAC_SCF) Single Collision Frames */
#define EMAC_SCF_SCF(value) ((EMAC_SCF_SCF_Msk & ((value) << EMAC_SCF_SCF_Pos)))
/* -------- EMAC_MCF : (EMAC Offset: 0x48) Multiple Collision Frames Register -------- */
#define EMAC_MCF_MCF_Pos 0
#define EMAC_MCF_MCF_Msk (0xffffu << EMAC_MCF_MCF_Pos) /**< \brief (EMAC_MCF) Multicollision Frames */
#define EMAC_MCF_MCF(value) ((EMAC_MCF_MCF_Msk & ((value) << EMAC_MCF_MCF_Pos)))
/* -------- EMAC_FRO : (EMAC Offset: 0x4C) Frames Received Ok Register -------- */
#define EMAC_FRO_FROK_Pos 0
#define EMAC_FRO_FROK_Msk (0xffffffu << EMAC_FRO_FROK_Pos) /**< \brief (EMAC_FRO) Frames Received OK */
#define EMAC_FRO_FROK(value) ((EMAC_FRO_FROK_Msk & ((value) << EMAC_FRO_FROK_Pos)))
/* -------- EMAC_FCSE : (EMAC Offset: 0x50) Frame Check Sequence Errors Register -------- */
#define EMAC_FCSE_FCSE_Pos 0
#define EMAC_FCSE_FCSE_Msk (0xffu << EMAC_FCSE_FCSE_Pos) /**< \brief (EMAC_FCSE) Frame Check Sequence Errors */
#define EMAC_FCSE_FCSE(value) ((EMAC_FCSE_FCSE_Msk & ((value) << EMAC_FCSE_FCSE_Pos)))
/* -------- EMAC_ALE : (EMAC Offset: 0x54) Alignment Errors Register -------- */
#define EMAC_ALE_ALE_Pos 0
#define EMAC_ALE_ALE_Msk (0xffu << EMAC_ALE_ALE_Pos) /**< \brief (EMAC_ALE) Alignment Errors */
#define EMAC_ALE_ALE(value) ((EMAC_ALE_ALE_Msk & ((value) << EMAC_ALE_ALE_Pos)))
/* -------- EMAC_DTF : (EMAC Offset: 0x58) Deferred Transmission Frames Register -------- */
#define EMAC_DTF_DTF_Pos 0
#define EMAC_DTF_DTF_Msk (0xffffu << EMAC_DTF_DTF_Pos) /**< \brief (EMAC_DTF) Deferred Transmission Frames */
#define EMAC_DTF_DTF(value) ((EMAC_DTF_DTF_Msk & ((value) << EMAC_DTF_DTF_Pos)))
/* -------- EMAC_LCOL : (EMAC Offset: 0x5C) Late Collisions Register -------- */
#define EMAC_LCOL_LCOL_Pos 0
#define EMAC_LCOL_LCOL_Msk (0xffu << EMAC_LCOL_LCOL_Pos) /**< \brief (EMAC_LCOL) Late Collisions */
#define EMAC_LCOL_LCOL(value) ((EMAC_LCOL_LCOL_Msk & ((value) << EMAC_LCOL_LCOL_Pos)))
/* -------- EMAC_ECOL : (EMAC Offset: 0x60) Excessive Collisions Register -------- */
#define EMAC_ECOL_EXCOL_Pos 0
#define EMAC_ECOL_EXCOL_Msk (0xffu << EMAC_ECOL_EXCOL_Pos) /**< \brief (EMAC_ECOL) Excessive Collisions */
#define EMAC_ECOL_EXCOL(value) ((EMAC_ECOL_EXCOL_Msk & ((value) << EMAC_ECOL_EXCOL_Pos)))
/* -------- EMAC_TUND : (EMAC Offset: 0x64) Transmit Underrun Errors Register -------- */
#define EMAC_TUND_TUND_Pos 0
#define EMAC_TUND_TUND_Msk (0xffu << EMAC_TUND_TUND_Pos) /**< \brief (EMAC_TUND) Transmit Underruns */
#define EMAC_TUND_TUND(value) ((EMAC_TUND_TUND_Msk & ((value) << EMAC_TUND_TUND_Pos)))
/* -------- EMAC_CSE : (EMAC Offset: 0x68) Carrier Sense Errors Register -------- */
#define EMAC_CSE_CSE_Pos 0
#define EMAC_CSE_CSE_Msk (0xffu << EMAC_CSE_CSE_Pos) /**< \brief (EMAC_CSE) Carrier Sense Errors */
#define EMAC_CSE_CSE(value) ((EMAC_CSE_CSE_Msk & ((value) << EMAC_CSE_CSE_Pos)))
/* -------- EMAC_RRE : (EMAC Offset: 0x6C) Receive Resource Errors Register -------- */
#define EMAC_RRE_RRE_Pos 0
#define EMAC_RRE_RRE_Msk (0xffffu << EMAC_RRE_RRE_Pos) /**< \brief (EMAC_RRE) Receive Resource Errors */
#define EMAC_RRE_RRE(value) ((EMAC_RRE_RRE_Msk & ((value) << EMAC_RRE_RRE_Pos)))
/* -------- EMAC_ROV : (EMAC Offset: 0x70) Receive Overrun Errors Register -------- */
#define EMAC_ROV_ROVR_Pos 0
#define EMAC_ROV_ROVR_Msk (0xffu << EMAC_ROV_ROVR_Pos) /**< \brief (EMAC_ROV) Receive Overrun */
#define EMAC_ROV_ROVR(value) ((EMAC_ROV_ROVR_Msk & ((value) << EMAC_ROV_ROVR_Pos)))
/* -------- EMAC_RSE : (EMAC Offset: 0x74) Receive Symbol Errors Register -------- */
#define EMAC_RSE_RSE_Pos 0
#define EMAC_RSE_RSE_Msk (0xffu << EMAC_RSE_RSE_Pos) /**< \brief (EMAC_RSE) Receive Symbol Errors */
#define EMAC_RSE_RSE(value) ((EMAC_RSE_RSE_Msk & ((value) << EMAC_RSE_RSE_Pos)))
/* -------- EMAC_ELE : (EMAC Offset: 0x78) Excessive Length Errors Register -------- */
#define EMAC_ELE_EXL_Pos 0
#define EMAC_ELE_EXL_Msk (0xffu << EMAC_ELE_EXL_Pos) /**< \brief (EMAC_ELE) Excessive Length Errors */
#define EMAC_ELE_EXL(value) ((EMAC_ELE_EXL_Msk & ((value) << EMAC_ELE_EXL_Pos)))
/* -------- EMAC_RJA : (EMAC Offset: 0x7C) Receive Jabbers Register -------- */
#define EMAC_RJA_RJB_Pos 0
#define EMAC_RJA_RJB_Msk (0xffu << EMAC_RJA_RJB_Pos) /**< \brief (EMAC_RJA) Receive Jabbers */
#define EMAC_RJA_RJB(value) ((EMAC_RJA_RJB_Msk & ((value) << EMAC_RJA_RJB_Pos)))
/* -------- EMAC_USF : (EMAC Offset: 0x80) Undersize Frames Register -------- */
#define EMAC_USF_USF_Pos 0
#define EMAC_USF_USF_Msk (0xffu << EMAC_USF_USF_Pos) /**< \brief (EMAC_USF) Undersize frames */
#define EMAC_USF_USF(value) ((EMAC_USF_USF_Msk & ((value) << EMAC_USF_USF_Pos)))
/* -------- EMAC_STE : (EMAC Offset: 0x84) SQE Test Errors Register -------- */
#define EMAC_STE_SQER_Pos 0
#define EMAC_STE_SQER_Msk (0xffu << EMAC_STE_SQER_Pos) /**< \brief (EMAC_STE) SQE test errors */
#define EMAC_STE_SQER(value) ((EMAC_STE_SQER_Msk & ((value) << EMAC_STE_SQER_Pos)))
/* -------- EMAC_RLE : (EMAC Offset: 0x88) Received Length Field Mismatch Register -------- */
#define EMAC_RLE_RLFM_Pos 0
#define EMAC_RLE_RLFM_Msk (0xffu << EMAC_RLE_RLFM_Pos) /**< \brief (EMAC_RLE) Receive Length Field Mismatch */
#define EMAC_RLE_RLFM(value) ((EMAC_RLE_RLFM_Msk & ((value) << EMAC_RLE_RLFM_Pos)))
/* -------- EMAC_HRB : (EMAC Offset: 0x90) Hash Register Bottom [31:0] Register -------- */
#define EMAC_HRB_ADDR_Pos 0
#define EMAC_HRB_ADDR_Msk (0xffffffffu << EMAC_HRB_ADDR_Pos) /**< \brief (EMAC_HRB)  */
#define EMAC_HRB_ADDR(value) ((EMAC_HRB_ADDR_Msk & ((value) << EMAC_HRB_ADDR_Pos)))
/* -------- EMAC_HRT : (EMAC Offset: 0x94) Hash Register Top [63:32] Register -------- */
#define EMAC_HRT_ADDR_Pos 0
#define EMAC_HRT_ADDR_Msk (0xffffffffu << EMAC_HRT_ADDR_Pos) /**< \brief (EMAC_HRT)  */
#define EMAC_HRT_ADDR(value) ((EMAC_HRT_ADDR_Msk & ((value) << EMAC_HRT_ADDR_Pos)))
/* -------- EMAC_SAxB : (EMAC Offset: N/A) Specific Address 1 Bottom Register -------- */
#define EMAC_SAxB_ADDR_Pos 0
#define EMAC_SAxB_ADDR_Msk (0xffffffffu << EMAC_SAxB_ADDR_Pos) /**< \brief (EMAC_SAxB)  */
#define EMAC_SAxB_ADDR(value) ((EMAC_SAxB_ADDR_Msk & ((value) << EMAC_SAxB_ADDR_Pos)))
/* -------- EMAC_SAxT : (EMAC Offset: N/A) Specific Address 1 Top Register -------- */
#define EMAC_SAxT_ADDR_Pos 0
#define EMAC_SAxT_ADDR_Msk (0xffffu << EMAC_SAxT_ADDR_Pos) /**< \brief (EMAC_SAxT)  */
#define EMAC_SAxT_ADDR(value) ((EMAC_SAxT_ADDR_Msk & ((value) << EMAC_SAxT_ADDR_Pos)))
/* -------- EMAC_TID : (EMAC Offset: 0xB8) Type ID Checking Register -------- */
#define EMAC_TID_TID_Pos 0
#define EMAC_TID_TID_Msk (0xffffu << EMAC_TID_TID_Pos) /**< \brief (EMAC_TID) Type ID checking */
#define EMAC_TID_TID(value) ((EMAC_TID_TID_Msk & ((value) << EMAC_TID_TID_Pos)))
/* -------- EMAC_USRIO : (EMAC Offset: 0xC0) User Input/Output Register -------- */
#define EMAC_USRIO_RMII (0x1u << 0) /**< \brief (EMAC_USRIO) Reduce MII */
#define EMAC_USRIO_CLKEN (0x1u << 1) /**< \brief (EMAC_USRIO) Clock Enable */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Fuse Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_FUSE Fuse Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Fuse hardware registers */
typedef struct {
  WoReg FUSE_CR;    /**< \brief (Fuse Offset: 0x00) Fuse Control Register */
  WoReg FUSE_MR;    /**< \brief (Fuse Offset: 0x04) Fuse Mode Register */
  RwReg FUSE_IR;    /**< \brief (Fuse Offset: 0x08) Fuse Index Register */
  WoReg FUSE_DR;    /**< \brief (Fuse Offset: 0x0C) Fuse Data Register */
  RoReg FUSE_SR[8]; /**< \brief (Fuse Offset: 0x10) Fuse Status Register */
} Fuse;
#endif /* __ASSEMBLY__ */
/* -------- FUSE_CR : (FUSE Offset: 0x00) Fuse Control Register -------- */
#define FUSE_CR_WRQ (0x1u << 0) /**< \brief (FUSE_CR) Write Request */
#define FUSE_CR_RRQ (0x1u << 1) /**< \brief (FUSE_CR) Read Request */
#define FUSE_CR_KEY_Pos 8
#define FUSE_CR_KEY_Msk (0xffu << FUSE_CR_KEY_Pos) /**< \brief (FUSE_CR) Key code */
#define   FUSE_CR_KEY_VALID (0xFBu << 8) /**< \brief (FUSE_CR) valid key. */
/* -------- FUSE_MR : (FUSE Offset: 0x04) Fuse Mode Register -------- */
#define FUSE_MR_MSK (0x1u << 0) /**< \brief (FUSE_MR) Mask Fuse Status Registers */
/* -------- FUSE_IR : (FUSE Offset: 0x08) Fuse Index Register -------- */
#define FUSE_IR_WS (0x1u << 0) /**< \brief (FUSE_IR) Write Status */
#define FUSE_IR_RS (0x1u << 1) /**< \brief (FUSE_IR) Read Status */
#define FUSE_IR_WSEL_Pos 8
#define FUSE_IR_WSEL_Msk (0xfu << FUSE_IR_WSEL_Pos) /**< \brief (FUSE_IR) Word Selection */
#define FUSE_IR_WSEL(value) ((FUSE_IR_WSEL_Msk & ((value) << FUSE_IR_WSEL_Pos)))
/* -------- FUSE_DR : (FUSE Offset: 0x0C) Fuse Data Register -------- */
#define FUSE_DR_DATA_Pos 0
#define FUSE_DR_DATA_Msk (0xffffffffu << FUSE_DR_DATA_Pos) /**< \brief (FUSE_DR) Data to Program */
#define FUSE_DR_DATA(value) ((FUSE_DR_DATA_Msk & ((value) << FUSE_DR_DATA_Pos)))
/* -------- FUSE_SR[8] : (FUSE Offset: 0x10) Fuse Status Register -------- */
#define FUSE_SR_FUSE_Pos 0
#define FUSE_SR_FUSE_Msk (0xffffffffu << FUSE_SR_FUSE_Pos) /**< \brief (FUSE_SR[8]) Fuse Status */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_GMAC Gigabit Ethernet MAC */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief GmacSa hardware registers */
typedef struct {
  RwReg   GMAC_SAB;        /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom [31:0] Register */
  RwReg   GMAC_SAT;        /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top [47:32] Register */
} GmacSa;
/** \brief Gmac hardware registers */
#define GMACSA_NUMBER 4
typedef struct {
  RwReg   GMAC_NCR;        /**< \brief (Gmac Offset: 0x000) Network Control Register */
  RwReg   GMAC_NCFGR;      /**< \brief (Gmac Offset: 0x004) Network Configuration Register */
  RoReg   GMAC_NSR;        /**< \brief (Gmac Offset: 0x008) Network Status Register */
  RwReg   GMAC_UR;         /**< \brief (Gmac Offset: 0x00C) User Register */
  RwReg   GMAC_DCFGR;      /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */
  RwReg   GMAC_TSR;        /**< \brief (Gmac Offset: 0x014) Transmit Status Register */
  RwReg   GMAC_RBQB;       /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address */
  RwReg   GMAC_TBQB;       /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address */
  RwReg   GMAC_RSR;        /**< \brief (Gmac Offset: 0x020) Receive Status Register */
  RoReg   GMAC_ISR;        /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */
  WoReg   GMAC_IER;        /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */
  WoReg   GMAC_IDR;        /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */
  RoReg   GMAC_IMR;        /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */
  RwReg   GMAC_MAN;        /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */
  RoReg   GMAC_RPQ;        /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */
  RwReg   GMAC_TPQ;        /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */
  RwReg   GMAC_TPSF;       /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */
  RwReg   GMAC_RPSF;       /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */
  RoReg   Reserved1[14];
  RwReg   GMAC_HRB;        /**< \brief (Gmac Offset: 0x080) Hash Register Bottom [31:0] */
  RwReg   GMAC_HRT;        /**< \brief (Gmac Offset: 0x084) Hash Register Top [63:32] */
  GmacSa  GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */
  RwReg   GMAC_TIDM[4];    /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */
  RwReg   GMAC_WOL;        /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */
  RwReg   GMAC_IPGS;       /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */
  RwReg   GMAC_SVLAN;      /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */
  RwReg   GMAC_TPFCP;      /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */
  RwReg   GMAC_SAMB1;      /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register */
  RwReg   GMAC_SAMT1;      /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register */
  RoReg   Reserved2[12];
  RoReg   GMAC_OTLO;       /**< \brief (Gmac Offset: 0x100) Octets Transmitted [31:0] Register */
  RoReg   GMAC_OTHI;       /**< \brief (Gmac Offset: 0x104) Octets Transmitted [47:32] Register */
  RoReg   GMAC_FT;         /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */
  RoReg   GMAC_BCFT;       /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */
  RoReg   GMAC_MFT;        /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */
  RoReg   GMAC_PFT;        /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */
  RoReg   GMAC_BFT64;      /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */
  RoReg   GMAC_TBFT127;    /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */
  RoReg   GMAC_TBFT255;    /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */
  RoReg   GMAC_TBFT511;    /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */
  RoReg   GMAC_TBFT1023;   /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */
  RoReg   GMAC_TBFT1518;   /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */
  RoReg   GMAC_GTBFT1518;  /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */
  RoReg   GMAC_TUR;        /**< \brief (Gmac Offset: 0x134) Transmit Under Runs Register */
  RoReg   GMAC_SCF;        /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */
  RoReg   GMAC_MCF;        /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */
  RoReg   GMAC_EC;         /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */
  RoReg   GMAC_LC;         /**< \brief (Gmac Offset: 0x144) Late Collisions Register */
  RoReg   GMAC_DTF;        /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */
  RoReg   GMAC_CSE;        /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */
  RoReg   GMAC_ORLO;       /**< \brief (Gmac Offset: 0x150) Octets Received [31:0] Received */
  RoReg   GMAC_ORHI;       /**< \brief (Gmac Offset: 0x154) Octets Received [47:32] Received */
  RoReg   GMAC_FR;         /**< \brief (Gmac Offset: 0x158) Frames Received Register */
  RoReg   GMAC_BCFR;       /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */
  RoReg   GMAC_MFR;        /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */
  RoReg   GMAC_PFR;        /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */
  RoReg   GMAC_BFR64;      /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */
  RoReg   GMAC_TBFR127;    /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */
  RoReg   GMAC_TBFR255;    /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */
  RoReg   GMAC_TBFR511;    /**< \brief (Gmac Offset: 0x174) 256 to 511Byte Frames Received Register */
  RoReg   GMAC_TBFR1023;   /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */
  RoReg   GMAC_TBFR1518;   /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */
  RoReg   GMAC_TMXBFR;     /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */
  RoReg   GMAC_UFR;        /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */
  RoReg   GMAC_OFR;        /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */
  RoReg   GMAC_JR;         /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */
  RoReg   GMAC_FCSE;       /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */
  RoReg   GMAC_LFFE;       /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */
  RoReg   GMAC_RSE;        /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */
  RoReg   GMAC_AE;         /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */
  RoReg   GMAC_RRE;        /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */
  RoReg   GMAC_ROE;        /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */
  RoReg   GMAC_IHCE;       /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */
  RoReg   GMAC_TCE;        /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */
  RoReg   GMAC_UCE;        /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */
  RoReg   Reserved3[5];
  RwReg   GMAC_TSSS;       /**< \brief (Gmac Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register */
  RwReg   GMAC_TSSN;       /**< \brief (Gmac Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register */
  RwReg   GMAC_TS;         /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Register */
  RwReg   GMAC_TN;         /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */
  WoReg   GMAC_TA;         /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */
  RwReg   GMAC_TI;         /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */
  RoReg   GMAC_EFTS;       /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds */
  RoReg   GMAC_EFTN;       /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds */
  RoReg   GMAC_EFRS;       /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds */
  RoReg   GMAC_EFRN;       /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds */
  RoReg   GMAC_PEFTS;      /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds */
  RoReg   GMAC_PEFTN;      /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds */
  RoReg   GMAC_PEFRS;      /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds */
  RoReg   GMAC_PEFRN;      /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds */
  RoReg   Reserved4[128];
  RoReg   GMAC_ISRPQ[7];   /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue */
  RoReg   Reserved5[9];
  RwReg   GMAC_TBQBAPQ[7]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Priority Queue */
  RoReg   Reserved6[9];
  RwReg   GMAC_RBQBAPQ[7]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Priority Queue */
  RoReg   Reserved7[1];
  RwReg   GMAC_RBSRPQ[7];  /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue */
  RoReg   Reserved8[17];
  RwReg   GMAC_ST1RPQ[16]; /**< \brief (Gmac Offset: 0x500) Screening Type1 Register Priority Queue */
  RwReg   GMAC_ST2RPQ[16]; /**< \brief (Gmac Offset: 0x540) Screening Type2 Register Priority Queue */
  RoReg   Reserved9[32];
  WoReg   GMAC_IERPQ[7];   /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue */
  RoReg   Reserved10[1];
  WoReg   GMAC_IDRPQ[7];   /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue */
  RoReg   Reserved11[1];
  RwReg   GMAC_IMRPQ[7];   /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue */
} Gmac;
#endif /* __ASSEMBLY__ */
/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */
#define GMAC_NCR_LB (0x1u << 0) /**< \brief (GMAC_NCR) Loop Back */
#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */
#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */
#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */
#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */
#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */
#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */
#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */
#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */
#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */
#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */
#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */
#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */
#define GMAC_NCR_RDS (0x1u << 14) /**< \brief (GMAC_NCR) Read Snapshot */
#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */
#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */
#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */
#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */
/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */
#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */
#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */
#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */
#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */
#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */
#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */
#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */
#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */
#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */
#define GMAC_NCFGR_GBE (0x1u << 10) /**< \brief (GMAC_NCFGR) Gigabit Mode Enable */
#define GMAC_NCFGR_PIS (0x1u << 11) /**< \brief (GMAC_NCFGR) Physical Interface Select */
#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */
#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */
#define GMAC_NCFGR_RXBUFO_Pos 14
#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */
#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)))
#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */
#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */
#define GMAC_NCFGR_CLK_Pos 18
#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */
#define   GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */
#define   GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */
#define   GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */
#define   GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120MHz) */
#define   GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */
#define   GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */
#define   GMAC_NCFGR_CLK_MCK_128 (0x6u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 128 (MCK up to 320 MHz) */
#define   GMAC_NCFGR_CLK_MCK_224 (0x7u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 224 (MCK up to 540 MHz) */
#define GMAC_NCFGR_DBW_Pos 21
#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */
#define   GMAC_NCFGR_DBW_DBW32 (0x0u << 21) /**< \brief (GMAC_NCFGR) 32-bit data bus width */
#define   GMAC_NCFGR_DBW_DBW64 (0x1u << 21) /**< \brief (GMAC_NCFGR) 64-bit data bus width */
#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */
#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */
#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */
#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */
#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */
#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */
#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG rx_er */
/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */
#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */
#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */
/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */
#define GMAC_UR_RGMII (0x1u << 0) /**< \brief (GMAC_UR) RGMII Mode */
#define GMAC_UR_HDFC (0x1u << 6) /**< \brief (GMAC_UR) Half Duplex Flow Control */
#define GMAC_UR_BPDG (0x1u << 7) /**< \brief (GMAC_UR) BPDG Bypass Deglitchers */
/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */
#define GMAC_DCFGR_FBLDO_Pos 0
#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */
#define   GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */
#define   GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */
#define   GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */
#define   GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */
#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */
#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */
#define GMAC_DCFGR_RXBMS_Pos 8
#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */
#define   GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 1 Kbyte Memory Size */
#define   GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 2 Kbytes Memory Size */
#define   GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */
#define   GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 8 Kbytes Memory Size */
#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */
#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */
#define GMAC_DCFGR_DRBS_Pos 16
#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */
#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)))
#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */
/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */
#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */
#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */
#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */
#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */
#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption due to AHB error */
#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */
#define GMAC_TSR_UND (0x1u << 6) /**< \brief (GMAC_TSR) Transmit Under Run */
#define GMAC_TSR_LCO (0x1u << 7) /**< \brief (GMAC_TSR) Late Collision Occurred */
#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */
/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address -------- */
#define GMAC_RBQB_ADDR_Pos 2
#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive buffer queue base address */
#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)))
/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address -------- */
#define GMAC_TBQB_ADDR_Pos 2
#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */
#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)))
/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */
#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */
#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */
#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */
#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */
/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */
#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */
#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */
#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */
#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */
#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Under Run */
#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded or Late Collision */
#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption due to AHB error */
#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */
#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */
#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */
#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */
#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */
#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */
#define GMAC_ISR_EXINT (0x1u << 15) /**< \brief (GMAC_ISR) External Interrupt */
#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */
#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */
#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */
#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */
#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */
#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */
#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */
#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */
#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */
/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */
#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */
#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */
#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */
#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */
#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Under Run */
#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */
#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption due to AHB error */
#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */
#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */
#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */
#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */
#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */
#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */
#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */
#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */
#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */
#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */
#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */
#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */
#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */
#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */
#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */
#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */
/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */
#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */
#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */
#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */
#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */
#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Under Run */
#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */
#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption due to AHB error */
#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */
#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */
#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */
#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */
#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */
#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */
#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */
#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */
#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */
#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */
#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */
#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */
#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */
#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */
#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */
#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */
/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */
#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */
#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */
#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */
#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */
#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Under Run */
#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded or Late Collision */
#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption due to AHB error */
#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */
#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */
#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */
#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */
#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */
#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */
#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */
#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */
#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */
#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */
#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */
#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */
#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */
#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */
#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */
/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */
#define GMAC_MAN_DATA_Pos 0
#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */
#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)))
#define GMAC_MAN_WTN_Pos 16
#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */
#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)))
#define GMAC_MAN_REGA_Pos 18
#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */
#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)))
#define GMAC_MAN_PHYA_Pos 23
#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */
#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)))
#define GMAC_MAN_OP_Pos 28
#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */
#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)))
#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */
#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */
/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */
#define GMAC_RPQ_RPQ_Pos 0
#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */
/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */
#define GMAC_TPQ_TPQ_Pos 0
#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */
#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)))
/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */
#define GMAC_TPSF_TPB1ADR_Pos 0
#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) tx_pbuf_addr-1:0 */
#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos)))
#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */
/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */
#define GMAC_RPSF_RPB1ADR_Pos 0
#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) rx_pbuf_addr-1:0 */
#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos)))
#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */
/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom [31:0] -------- */
#define GMAC_HRB_ADDR_Pos 0
#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */
#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)))
/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top [63:32] -------- */
#define GMAC_HRT_ADDR_Pos 0
#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */
#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)))
/* -------- GMAC_SAB1 : (GMAC Offset: 0x088) Specific Address 1 Bottom [31:0] Register -------- */
#define GMAC_SAB1_ADDR_Pos 0
#define GMAC_SAB1_ADDR_Msk (0xffffffffu << GMAC_SAB1_ADDR_Pos) /**< \brief (GMAC_SAB1) Specific Address 1 */
#define GMAC_SAB1_ADDR(value) ((GMAC_SAB1_ADDR_Msk & ((value) << GMAC_SAB1_ADDR_Pos)))
/* -------- GMAC_SAT1 : (GMAC Offset: 0x08C) Specific Address 1 Top [47:32] Register -------- */
#define GMAC_SAT1_ADDR_Pos 0
#define GMAC_SAT1_ADDR_Msk (0xffffu << GMAC_SAT1_ADDR_Pos) /**< \brief (GMAC_SAT1) Specific Address 1 */
#define GMAC_SAT1_ADDR(value) ((GMAC_SAT1_ADDR_Msk & ((value) << GMAC_SAT1_ADDR_Pos)))
/* -------- GMAC_SAB2 : (GMAC Offset: 0x090) Specific Address 2 Bottom [31:0] Register -------- */
#define GMAC_SAB2_ADDR_Pos 0
#define GMAC_SAB2_ADDR_Msk (0xffffffffu << GMAC_SAB2_ADDR_Pos) /**< \brief (GMAC_SAB2) Specific Address 2 */
#define GMAC_SAB2_ADDR(value) ((GMAC_SAB2_ADDR_Msk & ((value) << GMAC_SAB2_ADDR_Pos)))
/* -------- GMAC_SAT2 : (GMAC Offset: 0x094) Specific Address 2 Top [47:32] Register -------- */
#define GMAC_SAT2_ADDR_Pos 0
#define GMAC_SAT2_ADDR_Msk (0xffffu << GMAC_SAT2_ADDR_Pos) /**< \brief (GMAC_SAT2) Specific Address 2 */
#define GMAC_SAT2_ADDR(value) ((GMAC_SAT2_ADDR_Msk & ((value) << GMAC_SAT2_ADDR_Pos)))
/* -------- GMAC_SAB3 : (GMAC Offset: 0x098) Specific Address 3 Bottom [31:0] Register -------- */
#define GMAC_SAB3_ADDR_Pos 0
#define GMAC_SAB3_ADDR_Msk (0xffffffffu << GMAC_SAB3_ADDR_Pos) /**< \brief (GMAC_SAB3) Specific Address 3 */
#define GMAC_SAB3_ADDR(value) ((GMAC_SAB3_ADDR_Msk & ((value) << GMAC_SAB3_ADDR_Pos)))
/* -------- GMAC_SAT3 : (GMAC Offset: 0x09C) Specific Address 3 Top [47:32] Register -------- */
#define GMAC_SAT3_ADDR_Pos 0
#define GMAC_SAT3_ADDR_Msk (0xffffu << GMAC_SAT3_ADDR_Pos) /**< \brief (GMAC_SAT3) Specific Address 3 */
#define GMAC_SAT3_ADDR(value) ((GMAC_SAT3_ADDR_Msk & ((value) << GMAC_SAT3_ADDR_Pos)))
/* -------- GMAC_SAB4 : (GMAC Offset: 0x0A0) Specific Address 4 Bottom [31:0] Register -------- */
#define GMAC_SAB4_ADDR_Pos 0
#define GMAC_SAB4_ADDR_Msk (0xffffffffu << GMAC_SAB4_ADDR_Pos) /**< \brief (GMAC_SAB4) Specific Address 4 */
#define GMAC_SAB4_ADDR(value) ((GMAC_SAB4_ADDR_Msk & ((value) << GMAC_SAB4_ADDR_Pos)))
/* -------- GMAC_SAT4 : (GMAC Offset: 0x0A4) Specific Address 4 Top [47:32] Register -------- */
#define GMAC_SAT4_ADDR_Pos 0
#define GMAC_SAT4_ADDR_Msk (0xffffu << GMAC_SAT4_ADDR_Pos) /**< \brief (GMAC_SAT4) Specific Address 4 */
#define GMAC_SAT4_ADDR(value) ((GMAC_SAT4_ADDR_Msk & ((value) << GMAC_SAT4_ADDR_Pos)))
/* -------- GMAC_TIDM[4] : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */
#define GMAC_TIDM_TID_Pos 0
#define GMAC_TIDM_TID_Msk (0xffffu << GMAC_TIDM_TID_Pos) /**< \brief (GMAC_TIDM[4]) Type ID Match 1 */
#define GMAC_TIDM_TID(value) ((GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos)))
/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */
#define GMAC_WOL_IP_Pos 0
#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */
#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)))
#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */
#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */
#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */
#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */
/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */
#define GMAC_IPGS_FL_Pos 0
#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */
#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)))
/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */
#define GMAC_SVLAN_VLAN_TYPE_Pos 0
#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */
#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)))
#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */
/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */
#define GMAC_TPFCP_PEV_Pos 0
#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */
#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)))
#define GMAC_TPFCP_PQ_Pos 8
#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */
#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)))
/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register -------- */
#define GMAC_SAMB1_ADDR_Pos 0
#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */
#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)))
/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register -------- */
#define GMAC_SAMT1_ADDR_Pos 0
#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */
#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)))
/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted [31:0] Register -------- */
#define GMAC_OTLO_TXO_Pos 0
#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */
/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted [47:32] Register -------- */
#define GMAC_OTHI_TXO_Pos 0
#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */
/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */
#define GMAC_FT_FTX_Pos 0
#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */
/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */
#define GMAC_BCFT_BFTX_Pos 0
#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */
/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */
#define GMAC_MFT_MFTX_Pos 0
#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */
/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */
#define GMAC_PFT_PFTX_Pos 0
#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */
/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */
#define GMAC_BFT64_NFTX_Pos 0
#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */
/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */
#define GMAC_TBFT127_NFTX_Pos 0
#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */
/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */
#define GMAC_TBFT255_NFTX_Pos 0
#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */
/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */
#define GMAC_TBFT511_NFTX_Pos 0
#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */
/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */
#define GMAC_TBFT1023_NFTX_Pos 0
#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */
/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */
#define GMAC_TBFT1518_NFTX_Pos 0
#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */
/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */
#define GMAC_GTBFT1518_NFTX_Pos 0
#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */
/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Under Runs Register -------- */
#define GMAC_TUR_TXUNR_Pos 0
#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Under Runs */
/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */
#define GMAC_SCF_SCOL_Pos 0
#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */
/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */
#define GMAC_MCF_MCOL_Pos 0
#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */
/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */
#define GMAC_EC_XCOL_Pos 0
#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */
/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */
#define GMAC_LC_LCOL_Pos 0
#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */
/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */
#define GMAC_DTF_DEFT_Pos 0
#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */
/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */
#define GMAC_CSE_CSR_Pos 0
#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */
/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received [31:0] Received -------- */
#define GMAC_ORLO_RXO_Pos 0
#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */
/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received [47:32] Received -------- */
#define GMAC_ORHI_RXO_Pos 0
#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */
/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */
#define GMAC_FR_FRX_Pos 0
#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */
/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */
#define GMAC_BCFR_BFRX_Pos 0
#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */
/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */
#define GMAC_MFR_MFRX_Pos 0
#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */
/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */
#define GMAC_PFR_PFRX_Pos 0
#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */
/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */
#define GMAC_BFR64_NFRX_Pos 0
#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */
/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */
#define GMAC_TBFR127_NFRX_Pos 0
#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */
/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */
#define GMAC_TBFR255_NFRX_Pos 0
#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */
/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511Byte Frames Received Register -------- */
#define GMAC_TBFR511_NFRX_Pos 0
#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */
/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */
#define GMAC_TBFR1023_NFRX_Pos 0
#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */
/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */
#define GMAC_TBFR1518_NFRX_Pos 0
#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */
/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */
#define GMAC_TMXBFR_NFRX_Pos 0
#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */
/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */
#define GMAC_UFR_UFRX_Pos 0
#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */
/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */
#define GMAC_OFR_OFRX_Pos 0
#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */
/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */
#define GMAC_JR_JRX_Pos 0
#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */
/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */
#define GMAC_FCSE_FCKR_Pos 0
#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */
/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */
#define GMAC_LFFE_LFER_Pos 0
#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */
/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */
#define GMAC_RSE_RXSE_Pos 0
#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */
/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */
#define GMAC_AE_AER_Pos 0
#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */
/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */
#define GMAC_RRE_RXRER_Pos 0
#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */
/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */
#define GMAC_ROE_RXOVR_Pos 0
#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */
/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */
#define GMAC_IHCE_HCKER_Pos 0
#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */
/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */
#define GMAC_TCE_TCKER_Pos 0
#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */
/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */
#define GMAC_UCE_UCKER_Pos 0
#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */
/* -------- GMAC_TSSS : (GMAC Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register -------- */
#define GMAC_TSSS_VTS_Pos 0
#define GMAC_TSSS_VTS_Msk (0xffffffffu << GMAC_TSSS_VTS_Pos) /**< \brief (GMAC_TSSS) Value of Timer Seconds Register Capture */
#define GMAC_TSSS_VTS(value) ((GMAC_TSSS_VTS_Msk & ((value) << GMAC_TSSS_VTS_Pos)))
/* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register -------- */
#define GMAC_TSSN_VTN_Pos 0
#define GMAC_TSSN_VTN_Msk (0x3fffffffu << GMAC_TSSN_VTN_Pos) /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */
#define GMAC_TSSN_VTN(value) ((GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos)))
/* -------- GMAC_TS : (GMAC Offset: 0x1D0) 1588 Timer Seconds Register -------- */
#define GMAC_TS_TCS_Pos 0
#define GMAC_TS_TCS_Msk (0xffffffffu << GMAC_TS_TCS_Pos) /**< \brief (GMAC_TS) Timer Count in Seconds */
#define GMAC_TS_TCS(value) ((GMAC_TS_TCS_Msk & ((value) << GMAC_TS_TCS_Pos)))
/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */
#define GMAC_TN_TNS_Pos 0
#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */
#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)))
/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */
#define GMAC_TA_ITDT_Pos 0
#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */
#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)))
#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */
/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */
#define GMAC_TI_CNS_Pos 0
#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */
#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)))
#define GMAC_TI_ACNS_Pos 8
#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */
#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)))
#define GMAC_TI_NIT_Pos 16
#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */
#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)))
/* -------- GMAC_EFTS : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds -------- */
#define GMAC_EFTS_RUD_Pos 0
#define GMAC_EFTS_RUD_Msk (0xffffffffu << GMAC_EFTS_RUD_Pos) /**< \brief (GMAC_EFTS) Register Update */
/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds -------- */
#define GMAC_EFTN_RUD_Pos 0
#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */
/* -------- GMAC_EFRS : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds -------- */
#define GMAC_EFRS_RUD_Pos 0
#define GMAC_EFRS_RUD_Msk (0xffffffffu << GMAC_EFRS_RUD_Pos) /**< \brief (GMAC_EFRS) Register Update */
/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds -------- */
#define GMAC_EFRN_RUD_Pos 0
#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */
/* -------- GMAC_PEFTS : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds -------- */
#define GMAC_PEFTS_RUD_Pos 0
#define GMAC_PEFTS_RUD_Msk (0xffffffffu << GMAC_PEFTS_RUD_Pos) /**< \brief (GMAC_PEFTS) Register Update */
/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds -------- */
#define GMAC_PEFTN_RUD_Pos 0
#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */
/* -------- GMAC_PEFRS : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds -------- */
#define GMAC_PEFRS_RUD_Pos 0
#define GMAC_PEFRS_RUD_Msk (0xffffffffu << GMAC_PEFRS_RUD_Pos) /**< \brief (GMAC_PEFRS) Register Update */
/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds -------- */
#define GMAC_PEFRN_RUD_Pos 0
#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */
/* -------- GMAC_ISRPQ[7] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue -------- */
#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[7]) Receive Complete */
#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[7]) RX Used Bit Read */
#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[7]) Retry Limit Exceeded or Late Collision */
#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[7]) Transmit Frame Corruption due to AHB error */
#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[7]) Transmit Complete */
#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[7]) Receive Overrun */
#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[7]) HRESP Not OK */
/* -------- GMAC_TBQBAPQ[7] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Priority Queue -------- */
#define GMAC_TBQBAPQ_TXBQBA_Pos 2
#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[7]) Transmit Buffer Queue Base Address */
#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)))
/* -------- GMAC_RBQBAPQ[7] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Priority Queue -------- */
#define GMAC_RBQBAPQ_RXBQBA_Pos 2
#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[7]) Receive Buffer Queue Base Address */
#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)))
/* -------- GMAC_RBSRPQ[7] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue -------- */
#define GMAC_RBSRPQ_RBS_Pos 0
#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[7]) Receive Buffer Size */
#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)))
/* -------- GMAC_ST1RPQ[16] : (GMAC Offset: 0x500) Screening Type1 Register Priority Queue -------- */
#define GMAC_ST1RPQ_QNB_Pos 0
#define GMAC_ST1RPQ_QNB_Msk (0xfu << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[16]) Que Number (0-\>7) */
#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)))
#define GMAC_ST1RPQ_DSTCM_Pos 4
#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[16]) Differentiated Services or Traffic Class Match */
#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)))
#define GMAC_ST1RPQ_UDPM_Pos 12
#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[16]) UDP Port Match */
#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)))
#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[16]) Differentiated Services or Traffic Class Match Enable */
#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[16]) UDP Port Match Enable */
/* -------- GMAC_ST2RPQ[16] : (GMAC Offset: 0x540) Screening Type2 Register Priority Queue -------- */
#define GMAC_ST2RPQ_QNB_Pos 0
#define GMAC_ST2RPQ_QNB_Msk (0xfu << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[16]) Que Number (0-\>7) */
#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)))
#define GMAC_ST2RPQ_VLANP_Pos 4
#define GMAC_ST2RPQ_VLANP_Msk (0xfu << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[16]) VLAN Priority */
#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)))
#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[16]) VLAN Enable */
/* -------- GMAC_IERPQ[7] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue -------- */
#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[7]) Receive Complete */
#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[7]) RX Used Bit Read */
#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[7]) Retry Limit Exceeded or Late Collision */
#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[7]) Transmit Frame Corruption due to AHB error */
#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[7]) Transmit Complete */
#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[7]) Receive Overrun */
#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[7]) HRESP Not OK */
/* -------- GMAC_IDRPQ[7] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue -------- */
#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[7]) Receive Complete */
#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[7]) RX Used Bit Read */
#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[7]) Retry Limit Exceeded or Late Collision */
#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[7]) Transmit Frame Corruption due to AHB error */
#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[7]) Transmit Complete */
#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[7]) Receive Overrun */
#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[7]) HRESP Not OK */
/* -------- GMAC_IMRPQ[7] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue -------- */
#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[7]) Receive Complete */
#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[7]) RX Used Bit Read */
#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[7]) Retry Limit Exceeded or Late Collision */
#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[7]) AHB Error */
#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[7]) Transmit Complete */
#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[7]) Receive Overrun */
#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[7]) HRESP Not OK */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_GPBR General Purpose Backup Register */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Gpbr hardware registers */
typedef struct {
  RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */
  RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */
  RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */
  RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */
} Gpbr;
#endif /* __ASSEMBLY__ */
/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */
#define SYS_GPBR0_GPBR_VALUE0_Pos 0
#define SYS_GPBR0_GPBR_VALUE0_Msk (0xffffffffu << SYS_GPBR0_GPBR_VALUE0_Pos) /**< \brief (SYS_GPBR0) Value of GPBR x */
#define SYS_GPBR0_GPBR_VALUE0(value) ((SYS_GPBR0_GPBR_VALUE0_Msk & ((value) << SYS_GPBR0_GPBR_VALUE0_Pos)))
/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */
#define SYS_GPBR1_GPBR_VALUE1_Pos 0
#define SYS_GPBR1_GPBR_VALUE1_Msk (0xffffffffu << SYS_GPBR1_GPBR_VALUE1_Pos) /**< \brief (SYS_GPBR1) Value of GPBR x */
#define SYS_GPBR1_GPBR_VALUE1(value) ((SYS_GPBR1_GPBR_VALUE1_Msk & ((value) << SYS_GPBR1_GPBR_VALUE1_Pos)))
/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */
#define SYS_GPBR2_GPBR_VALUE2_Pos 0
#define SYS_GPBR2_GPBR_VALUE2_Msk (0xffffffffu << SYS_GPBR2_GPBR_VALUE2_Pos) /**< \brief (SYS_GPBR2) Value of GPBR x */
#define SYS_GPBR2_GPBR_VALUE2(value) ((SYS_GPBR2_GPBR_VALUE2_Msk & ((value) << SYS_GPBR2_GPBR_VALUE2_Pos)))
/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */
#define SYS_GPBR3_GPBR_VALUE3_Pos 0
#define SYS_GPBR3_GPBR_VALUE3_Msk (0xffffffffu << SYS_GPBR3_GPBR_VALUE3_Pos) /**< \brief (SYS_GPBR3) Value of GPBR x */
#define SYS_GPBR3_GPBR_VALUE3(value) ((SYS_GPBR3_GPBR_VALUE3_Msk & ((value) << SYS_GPBR3_GPBR_VALUE3_Pos)))

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_HSMCI High Speed MultiMedia Card Interface */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Hsmci hardware registers */
typedef struct {
  WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
  RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
  RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
  RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
  RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
  WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
  RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
  RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
  RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
  RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
  WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
  RoReg Reserved1[2];
  RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
  WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
  WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
  RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
  RwReg HSMCI_DMA;       /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
  RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
  RoReg Reserved2[35];
  RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
  RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
  RoReg Reserved3[69];
  RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
} Hsmci;
#endif /* __ASSEMBLY__ */
/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
#define HSMCI_MR_CLKDIV_Pos 0
#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
#define HSMCI_MR_PWSDIV_Pos 8
#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */
/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
#define HSMCI_DTOR_DTOCYC_Pos 0
#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
#define HSMCI_DTOR_DTOMUL_Pos 4
#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
#define HSMCI_SDCR_SDCSEL_Pos 0
#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
#define HSMCI_SDCR_SDCBUS_Pos 6
#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
#define HSMCI_ARGR_ARG_Pos 0
#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
#define HSMCI_CMDR_CMDNB_Pos 0
#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
#define HSMCI_CMDR_RSPTYP_Pos 6
#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
#define HSMCI_CMDR_SPCMD_Pos 8
#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
#define HSMCI_CMDR_TRCMD_Pos 16
#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
#define HSMCI_CMDR_TRTYP_Pos 19
#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
#define HSMCI_CMDR_IOSPCMD_Pos 24
#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
#define HSMCI_BLKR_BCNT_Pos 0
#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 1: Value 0 corresponds to an infinite block transfer. */
#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
#define HSMCI_BLKR_BLKLEN_Pos 16
#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
#define HSMCI_CSTOR_CSTOCYC_Pos 0
#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
#define HSMCI_CSTOR_CSTOMUL_Pos 4
#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
#define HSMCI_RSPR_RSP_Pos 0
#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
#define HSMCI_RDR_DATA_Pos 0
#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
#define HSMCI_TDR_DATA_Pos 0
#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */
#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */
#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */
#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */
#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */
#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */
#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */
#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */
#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */
#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
#define HSMCI_DMA_OFFSET_Pos 0
#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */
#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos)))
#define HSMCI_DMA_CHKSIZE_Pos 4
#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
#define   HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */
#define   HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */
#define   HSMCI_DMA_CHKSIZE_8 (0x2u << 4) /**< \brief (HSMCI_DMA) 8 data available */
#define   HSMCI_DMA_CHKSIZE_16 (0x3u << 4) /**< \brief (HSMCI_DMA) 16 data available */
#define   HSMCI_DMA_CHKSIZE_32 (0x4u << 4) /**< \brief (HSMCI_DMA) 32 data available */
#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */
/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
#define HSMCI_WPMR_WP_KEY_Pos 8
#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
#define HSMCI_WPSR_WP_VS_Pos 0
#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
#define HSMCI_WPSR_WP_VSRC_Pos 8
#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
#define HSMCI_FIFO_DATA_Pos 0
#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Image Sensor Interface */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_ISI Image Sensor Interface */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Isi hardware registers */
typedef struct {
  RwReg ISI_CFG1;       /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */
  RwReg ISI_CFG2;       /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */
  RwReg ISI_PSIZE;      /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */
  RwReg ISI_PDECF;      /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */
  RwReg ISI_Y2R_SET0;   /**< \brief (Isi Offset: 0x10) ISI CSC YCrCb To RGB Set 0 Register */
  RwReg ISI_Y2R_SET1;   /**< \brief (Isi Offset: 0x14) ISI CSC YCrCb To RGB Set 1 Register */
  RwReg ISI_R2Y_SET0;   /**< \brief (Isi Offset: 0x18) ISI CSC RGB To YCrCb Set 0 Register */
  RwReg ISI_R2Y_SET1;   /**< \brief (Isi Offset: 0x1C) ISI CSC RGB To YCrCb Set 1 Register */
  RwReg ISI_R2Y_SET2;   /**< \brief (Isi Offset: 0x20) ISI CSC RGB To YCrCb Set 2 Register */
  WoReg ISI_CR;         /**< \brief (Isi Offset: 0x24) ISI Control Register */
  RoReg ISI_SR;         /**< \brief (Isi Offset: 0x28) ISI Status Register */
  WoReg ISI_IER;        /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */
  WoReg ISI_IDR;        /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */
  RoReg ISI_IMR;        /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */
  WoReg ISI_DMA_CHER;   /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */
  WoReg ISI_DMA_CHDR;   /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */
  RoReg ISI_DMA_CHSR;   /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */
  RwReg ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */
  RwReg ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */
  RwReg ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */
  RwReg ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */
  RwReg ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */
  RwReg ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */
  RoReg Reserved1[34];
  RwReg ISI_WPCR;       /**< \brief (Isi Offset: 0xE4) Write Protection Control Register */
  RoReg ISI_WPSR;       /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */
} Isi;
#endif /* __ASSEMBLY__ */
/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */
#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */
#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */
#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */
#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */
#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */
#define ISI_CFG1_FRATE_Pos 8
#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */
#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos)))
#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */
#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */
#define ISI_CFG1_THMASK_Pos 13
#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */
#define   ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */
#define   ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */
#define   ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */
#define ISI_CFG1_SLD_Pos 16
#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */
#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos)))
#define ISI_CFG1_SFD_Pos 24
#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */
#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos)))
/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */
#define ISI_CFG2_IM_VSIZE_Pos 0
#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047]: */
#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos)))
#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2)  */
#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode: */
#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2)  */
#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2)  */
#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */
#define ISI_CFG2_IM_HSIZE_Pos 16
#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */
#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos)))
#define ISI_CFG2_YCC_SWAP_Pos 28
#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) Defines the YCC Image Data */
#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos)))
#define ISI_CFG2_RGB_CFG_Pos 30
#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) Defines RGB Pattern when RGB_MODE is set to 1 */
#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos)))
/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */
#define ISI_PSIZE_PREV_VSIZE_Pos 0
#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */
#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos)))
#define ISI_PSIZE_PREV_HSIZE_Pos 16
#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */
#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos)))
/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */
#define ISI_PDECF_DEC_FACTOR_Pos 0
#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */
#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos)))
/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI CSC YCrCb To RGB Set 0 Register -------- */
#define ISI_Y2R_SET0_C0_Pos 0
#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */
#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos)))
#define ISI_Y2R_SET0_C1_Pos 8
#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */
#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos)))
#define ISI_Y2R_SET0_C2_Pos 16
#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */
#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos)))
#define ISI_Y2R_SET0_C3_Pos 24
#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */
#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos)))
/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI CSC YCrCb To RGB Set 1 Register -------- */
#define ISI_Y2R_SET1_C4_Pos 0
#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */
#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos)))
#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */
#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */
#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */
/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI CSC RGB To YCrCb Set 0 Register -------- */
#define ISI_R2Y_SET0_C0_Pos 0
#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */
#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos)))
#define ISI_R2Y_SET0_C1_Pos 8
#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */
#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos)))
#define ISI_R2Y_SET0_C2_Pos 16
#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */
#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos)))
#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */
/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI CSC RGB To YCrCb Set 1 Register -------- */
#define ISI_R2Y_SET1_C3_Pos 0
#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */
#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos)))
#define ISI_R2Y_SET1_C4_Pos 8
#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */
#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos)))
#define ISI_R2Y_SET1_C5_Pos 16
#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */
#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos)))
#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */
/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI CSC RGB To YCrCb Set 2 Register -------- */
#define ISI_R2Y_SET2_C6_Pos 0
#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */
#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos)))
#define ISI_R2Y_SET2_C7_Pos 8
#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */
#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos)))
#define ISI_R2Y_SET2_C8_Pos 16
#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */
#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos)))
#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */
/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */
#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */
#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */
#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */
#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */
/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */
#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR)  */
#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated */
#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated */
#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request (this bit is a status bit) */
#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization */
#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated. */
#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated. */
#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress (this is a status bit) */
#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow */
#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow */
#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error */
#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun */
/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */
#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */
#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */
#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */
#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */
#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */
#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */
#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */
#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */
#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */
/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */
#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */
#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */
#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */
#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */
#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */
#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */
#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */
#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */
#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */
/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */
#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */
#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */
#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */
#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Interrupt */
#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Interrupt */
#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) FIFO Preview Overflow */
#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) FIFO Codec Overflow */
#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */
#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */
/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */
#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */
#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */
/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */
#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR)  */
#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR)  */
/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */
#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR)  */
#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR)  */
/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */
#define ISI_DMA_P_ADDR_P_ADDR_Pos 2
#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address. (This address is word aligned.) */
#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos)))
/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */
#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Field */
#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Field */
#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */
#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) (This field is only updated in the memory.) */
/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */
#define ISI_DMA_P_DSCR_P_DSCR_Pos 2
#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address (This address is word aligned.) */
#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos)))
/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */
#define ISI_DMA_C_ADDR_C_ADDR_Pos 2
#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address (This address is word aligned.) */
#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos)))
/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */
#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Field */
#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Field */
#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done flag control */
#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) (This field is only updated in the memory.) */
/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */
#define ISI_DMA_C_DSCR_C_DSCR_Pos 2
#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address (This address is word aligned.) */
#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos)))
/* -------- ISI_WPCR : (ISI Offset: 0xE4) Write Protection Control Register -------- */
#define ISI_WPCR_WP_EN (0x1u << 0) /**< \brief (ISI_WPCR) Write Protection Enable */
#define ISI_WPCR_WP_KEY_Pos 8
#define ISI_WPCR_WP_KEY_Msk (0xffffffu << ISI_WPCR_WP_KEY_Pos) /**< \brief (ISI_WPCR) Write Protection KEY Password */
#define ISI_WPCR_WP_KEY(value) ((ISI_WPCR_WP_KEY_Msk & ((value) << ISI_WPCR_WP_KEY_Pos)))
/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */
#define ISI_WPSR_WP_VS_Pos 0
#define ISI_WPSR_WP_VS_Msk (0xfu << ISI_WPSR_WP_VS_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Status */
#define ISI_WPSR_WP_VSRC_Pos 8
#define ISI_WPSR_WP_VSRC_Msk (0xffffu << ISI_WPSR_WP_VSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR LCD Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_LCDC LCD Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Lcdc hardware registers */
typedef struct {
  RwReg LCDC_LCDCFG0;       /**< \brief (Lcdc Offset: 0x00000000) LCD Controller Configuration Register 0 */
  RwReg LCDC_LCDCFG1;       /**< \brief (Lcdc Offset: 0x00000004) LCD Controller Configuration Register 1 */
  RwReg LCDC_LCDCFG2;       /**< \brief (Lcdc Offset: 0x00000008) LCD Controller Configuration Register 2 */
  RwReg LCDC_LCDCFG3;       /**< \brief (Lcdc Offset: 0x0000000C) LCD Controller Configuration Register 3 */
  RwReg LCDC_LCDCFG4;       /**< \brief (Lcdc Offset: 0x00000010) LCD Controller Configuration Register 4 */
  RwReg LCDC_LCDCFG5;       /**< \brief (Lcdc Offset: 0x00000014) LCD Controller Configuration Register 5 */
  RwReg LCDC_LCDCFG6;       /**< \brief (Lcdc Offset: 0x00000018) LCD Controller Configuration Register 6 */
  RoReg Reserved1[1];
  WoReg LCDC_LCDEN;         /**< \brief (Lcdc Offset: 0x00000020) LCD Controller Enable Register */
  WoReg LCDC_LCDDIS;        /**< \brief (Lcdc Offset: 0x00000024) LCD Controller Disable Register */
  RoReg LCDC_LCDSR;         /**< \brief (Lcdc Offset: 0x00000028) LCD Controller Status Register */
  WoReg LCDC_LCDIER;        /**< \brief (Lcdc Offset: 0x0000002C) LCD Controller Interrupt Enable Register */
  WoReg LCDC_LCDIDR;        /**< \brief (Lcdc Offset: 0x00000030) LCD Controller Interrupt Disable Register */
  RoReg LCDC_LCDIMR;        /**< \brief (Lcdc Offset: 0x00000034) LCD Controller Interrupt Mask Register */
  RoReg LCDC_LCDISR;        /**< \brief (Lcdc Offset: 0x00000038) LCD Controller Interrupt Status Register */
  RoReg Reserved2[1];
  WoReg LCDC_BASECHER;      /**< \brief (Lcdc Offset: 0x00000040) Base Layer Channel Enable Register */
  WoReg LCDC_BASECHDR;      /**< \brief (Lcdc Offset: 0x00000044) Base Layer Channel Disable Register */
  RoReg LCDC_BASECHSR;      /**< \brief (Lcdc Offset: 0x00000048) Base Layer Channel Status Register */
  WoReg LCDC_BASEIER;       /**< \brief (Lcdc Offset: 0x0000004C) Base Layer Interrupt Enable Register */
  WoReg LCDC_BASEIDR;       /**< \brief (Lcdc Offset: 0x00000050) Base Layer Interrupt Disabled Register */
  RoReg LCDC_BASEIMR;       /**< \brief (Lcdc Offset: 0x00000054) Base Layer Interrupt Mask Register */
  RoReg LCDC_BASEISR;       /**< \brief (Lcdc Offset: 0x00000058) Base Layer Interrupt status Register */
  RwReg LCDC_BASEHEAD;      /**< \brief (Lcdc Offset: 0x0000005C) Base DMA Head Register */
  RwReg LCDC_BASEADDR;      /**< \brief (Lcdc Offset: 0x00000060) Base DMA Address Register */
  RwReg LCDC_BASECTRL;      /**< \brief (Lcdc Offset: 0x00000064) Base DMA Control Register */
  RwReg LCDC_BASENEXT;      /**< \brief (Lcdc Offset: 0x00000068) Base DMA Next Register */
  RwReg LCDC_BASECFG0;      /**< \brief (Lcdc Offset: 0x0000006C) Base Configuration register 0 */
  RwReg LCDC_BASECFG1;      /**< \brief (Lcdc Offset: 0x00000070) Base Configuration register 1 */
  RwReg LCDC_BASECFG2;      /**< \brief (Lcdc Offset: 0x00000074) Base Configuration register 2 */
  RwReg LCDC_BASECFG3;      /**< \brief (Lcdc Offset: 0x00000078) Base Configuration register 3 */
  RwReg LCDC_BASECFG4;      /**< \brief (Lcdc Offset: 0x0000007C) Base Configuration register 4 */
  RwReg LCDC_BASECFG5;      /**< \brief (Lcdc Offset: 0x00000080) Base Configuration register 5 */
  RwReg LCDC_BASECFG6;      /**< \brief (Lcdc Offset: 0x00000084) Base Configuration register 6 */
  RoReg Reserved3[46];
  WoReg LCDC_OVR1CHER;      /**< \brief (Lcdc Offset: 0x00000140) Overlay 1 Channel Enable Register */
  WoReg LCDC_OVR1CHDR;      /**< \brief (Lcdc Offset: 0x00000144) Overlay 1 Channel Disable Register */
  RoReg LCDC_OVR1CHSR;      /**< \brief (Lcdc Offset: 0x00000148) Overlay 1 Channel Status Register */
  WoReg LCDC_OVR1IER;       /**< \brief (Lcdc Offset: 0x0000014C) Overlay 1 Interrupt Enable Register */
  WoReg LCDC_OVR1IDR;       /**< \brief (Lcdc Offset: 0x00000150) Overlay 1 Interrupt Disable Register */
  RoReg LCDC_OVR1IMR;       /**< \brief (Lcdc Offset: 0x00000154) Overlay 1 Interrupt Mask Register */
  RoReg LCDC_OVR1ISR;       /**< \brief (Lcdc Offset: 0x00000158) Overlay 1 Interrupt Status Register */
  RwReg LCDC_OVR1HEAD;      /**< \brief (Lcdc Offset: 0x0000015C) Overlay 1 DMA Head Register */
  RwReg LCDC_OVR1ADDR;      /**< \brief (Lcdc Offset: 0x00000160) Overlay 1 DMA Address Register */
  RwReg LCDC_OVR1CTRL;      /**< \brief (Lcdc Offset: 0x00000164) Overlay1 DMA Control Register */
  RwReg LCDC_OVR1NEXT;      /**< \brief (Lcdc Offset: 0x00000168) Overlay1 DMA Next Register */
  RwReg LCDC_OVR1CFG0;      /**< \brief (Lcdc Offset: 0x0000016C) Overlay 1 Configuration 0 Register */
  RwReg LCDC_OVR1CFG1;      /**< \brief (Lcdc Offset: 0x00000170) Overlay 1 Configuration 1 Register */
  RwReg LCDC_OVR1CFG2;      /**< \brief (Lcdc Offset: 0x00000174) Overlay 1 Configuration 2 Register */
  RwReg LCDC_OVR1CFG3;      /**< \brief (Lcdc Offset: 0x00000178) Overlay 1 Configuration 3 Register */
  RwReg LCDC_OVR1CFG4;      /**< \brief (Lcdc Offset: 0x0000017C) Overlay 1 Configuration 4 Register */
  RwReg LCDC_OVR1CFG5;      /**< \brief (Lcdc Offset: 0x00000180) Overlay 1 Configuration 5 Register */
  RwReg LCDC_OVR1CFG6;      /**< \brief (Lcdc Offset: 0x00000184) Overlay 1 Configuration 6 Register */
  RwReg LCDC_OVR1CFG7;      /**< \brief (Lcdc Offset: 0x00000188) Overlay 1 Configuration 7 Register */
  RwReg LCDC_OVR1CFG8;      /**< \brief (Lcdc Offset: 0x0000018C) Overlay 1 Configuration 8Register */
  RwReg LCDC_OVR1CFG9;      /**< \brief (Lcdc Offset: 0x00000190) Overlay 1 Configuration 9 Register */
  RoReg Reserved4[43];
  WoReg LCDC_OVR2CHER;      /**< \brief (Lcdc Offset: 0x00000240) Overlay 2 Channel Enable Register */
  WoReg LCDC_OVR2CHDR;      /**< \brief (Lcdc Offset: 0x00000244) Overlay 2 Channel Disable Register */
  RoReg LCDC_OVR2CHSR;      /**< \brief (Lcdc Offset: 0x00000248) Overlay 2 Channel Status Register */
  WoReg LCDC_OVR2IER;       /**< \brief (Lcdc Offset: 0x0000024C) Overlay 2 Interrupt Enable Register */
  WoReg LCDC_OVR2IDR;       /**< \brief (Lcdc Offset: 0x00000250) Overlay 2 Interrupt Disable Register */
  RoReg LCDC_OVR2IMR;       /**< \brief (Lcdc Offset: 0x00000254) Overlay 2 Interrupt Mask Register */
  RoReg LCDC_OVR2ISR;       /**< \brief (Lcdc Offset: 0x00000258) Overlay 2 Interrupt status Register */
  RwReg LCDC_OVR2HEAD;      /**< \brief (Lcdc Offset: 0x0000025C) Overlay 2 DMA Head Register */
  RwReg LCDC_OVR2ADDR;      /**< \brief (Lcdc Offset: 0x00000260) Overlay 2 DMA Address Register */
  RwReg LCDC_OVR2CTRL;      /**< \brief (Lcdc Offset: 0x00000264) Overlay 2 DMA Control Register */
  RwReg LCDC_OVR2NEXT;      /**< \brief (Lcdc Offset: 0x00000268) Overlay 2 DMA Next Register */
  RwReg LCDC_OVR2CFG0;      /**< \brief (Lcdc Offset: 0x0000026C) Overlay 2 Configuration 0 Register */
  RwReg LCDC_OVR2CFG1;      /**< \brief (Lcdc Offset: 0x00000270) Overlay 2 Configuration 1 Register */
  RwReg LCDC_OVR2CFG2;      /**< \brief (Lcdc Offset: 0x00000274) Overlay 2 Configuration 2 Register */
  RwReg LCDC_OVR2CFG3;      /**< \brief (Lcdc Offset: 0x00000278) Overlay 2 Configuration 3 Register */
  RwReg LCDC_OVR2CFG4;      /**< \brief (Lcdc Offset: 0x0000027C) Overlay 2 Configuration 4 Register */
  RwReg LCDC_OVR2CFG5;      /**< \brief (Lcdc Offset: 0x00000280) Overlay 2 Configuration 5 Register */
  RwReg LCDC_OVR2CFG6;      /**< \brief (Lcdc Offset: 0x00000284) Overlay 2 Configuration 6 Register */
  RwReg LCDC_OVR2CFG7;      /**< \brief (Lcdc Offset: 0x00000288) Overlay 2 Configuration 7 Register */
  RwReg LCDC_OVR2CFG8;      /**< \brief (Lcdc Offset: 0x0000028C) Overlay 2 Configuration 8 Register */
  RwReg LCDC_OVR2CFG9;      /**< \brief (Lcdc Offset: 0x00000290) Overlay 2 Configuration 9 Register */
  RoReg Reserved5[43];
  WoReg LCDC_HEOCHER;       /**< \brief (Lcdc Offset: 0x00000340) High-End Overlay Channel Enable Register */
  WoReg LCDC_HEOCHDR;       /**< \brief (Lcdc Offset: 0x00000344) High-End Overlay Channel Disable Register */
  RoReg LCDC_HEOCHSR;       /**< \brief (Lcdc Offset: 0x00000348) High-End Overlay Channel Status Register */
  WoReg LCDC_HEOIER;        /**< \brief (Lcdc Offset: 0x0000034C) High-End Overlay Interrupt Enable Register */
  WoReg LCDC_HEOIDR;        /**< \brief (Lcdc Offset: 0x00000350) High-End Overlay Interrupt Disable Register */
  RoReg LCDC_HEOIMR;        /**< \brief (Lcdc Offset: 0x00000354) High-End Overlay Interrupt Mask Register */
  RoReg LCDC_HEOISR;        /**< \brief (Lcdc Offset: 0x00000358) High-End Overlay Interrupt Status Register */
  RwReg LCDC_HEOHEAD;       /**< \brief (Lcdc Offset: 0x0000035C) High-End Overlay DMA Head Register */
  RwReg LCDC_HEOADDR;       /**< \brief (Lcdc Offset: 0x00000360) High-End Overlay DMA Address Register */
  RwReg LCDC_HEOCTRL;       /**< \brief (Lcdc Offset: 0x00000364) High-End Overlay DMA Control Register */
  RwReg LCDC_HEONEXT;       /**< \brief (Lcdc Offset: 0x00000368) High-End Overlay DMA Next Register */
  RwReg LCDC_HEOUHEAD;      /**< \brief (Lcdc Offset: 0x0000036C) High-End Overlay U DMA Head Register */
  RwReg LCDC_HEOUADDR;      /**< \brief (Lcdc Offset: 0x00000370) High-End Overlay U DMA Address Register */
  RwReg LCDC_HEOUCTRL;      /**< \brief (Lcdc Offset: 0x00000374) High-End Overlay U DMA control Register */
  RwReg LCDC_HEOUNEXT;      /**< \brief (Lcdc Offset: 0x00000378) High-End Overlay U DMA Next Register */
  RwReg LCDC_HEOVHEAD;      /**< \brief (Lcdc Offset: 0x0000037C) High-End Overlay V DMA Head Register */
  RwReg LCDC_HEOVADDR;      /**< \brief (Lcdc Offset: 0x00000380) High-End Overlay V DMA Address Register */
  RwReg LCDC_HEOVCTRL;      /**< \brief (Lcdc Offset: 0x00000384) High-End Overlay V DMA control Register */
  RwReg LCDC_HEOVNEXT;      /**< \brief (Lcdc Offset: 0x00000388) High-End Overlay VDMA Next Register */
  RwReg LCDC_HEOCFG0;       /**< \brief (Lcdc Offset: 0x0000038C) High-End Overlay Configuration Register 0 */
  RwReg LCDC_HEOCFG1;       /**< \brief (Lcdc Offset: 0x00000390) High-End Overlay Configuration Register 1 */
  RwReg LCDC_HEOCFG2;       /**< \brief (Lcdc Offset: 0x00000394) High-End Overlay Configuration Register 2 */
  RwReg LCDC_HEOCFG3;       /**< \brief (Lcdc Offset: 0x00000398) High-End Overlay Configuration Register 3 */
  RwReg LCDC_HEOCFG4;       /**< \brief (Lcdc Offset: 0x0000039C) High-End Overlay Configuration Register 4 */
  RwReg LCDC_HEOCFG5;       /**< \brief (Lcdc Offset: 0x000003A0) High-End Overlay Configuration Register 5 */
  RwReg LCDC_HEOCFG6;       /**< \brief (Lcdc Offset: 0x000003A4) High-End Overlay Configuration Register 6 */
  RwReg LCDC_HEOCFG7;       /**< \brief (Lcdc Offset: 0x000003A8) High-End Overlay Configuration Register 7 */
  RwReg LCDC_HEOCFG8;       /**< \brief (Lcdc Offset: 0x000003AC) High-End Overlay Configuration Register 8 */
  RwReg LCDC_HEOCFG9;       /**< \brief (Lcdc Offset: 0x000003B0) High-End Overlay Configuration Register 9 */
  RwReg LCDC_HEOCFG10;      /**< \brief (Lcdc Offset: 0x000003B4) High-End Overlay Configuration Register 10 */
  RwReg LCDC_HEOCFG11;      /**< \brief (Lcdc Offset: 0x000003B8) High-End Overlay Configuration Register 11 */
  RwReg LCDC_HEOCFG12;      /**< \brief (Lcdc Offset: 0x000003BC) High-End Overlay Configuration Register 12 */
  RwReg LCDC_HEOCFG13;      /**< \brief (Lcdc Offset: 0x000003C0) High-End Overlay Configuration Register 13 */
  RwReg LCDC_HEOCFG14;      /**< \brief (Lcdc Offset: 0x000003C4) High-End Overlay Configuration Register 14 */
  RwReg LCDC_HEOCFG15;      /**< \brief (Lcdc Offset: 0x000003C8) High-End Overlay Configuration Register 15 */
  RwReg LCDC_HEOCFG16;      /**< \brief (Lcdc Offset: 0x000003CC) High-End Overlay Configuration Register 16 */
  RwReg LCDC_HEOCFG17;      /**< \brief (Lcdc Offset: 0x000003D0) High-End Overlay Configuration Register 17 */
  RwReg LCDC_HEOCFG18;      /**< \brief (Lcdc Offset: 0x000003D4) High-End Overlay Configuration Register 18 */
  RwReg LCDC_HEOCFG19;      /**< \brief (Lcdc Offset: 0x000003D8) High-End Overlay Configuration Register 19 */
  RwReg LCDC_HEOCFG20;      /**< \brief (Lcdc Offset: 0x000003DC) High-End Overlay Configuration Register 20 */
  RwReg LCDC_HEOCFG21;      /**< \brief (Lcdc Offset: 0x000003E0) High-End Overlay Configuration Register 21 */
  RwReg LCDC_HEOCFG22;      /**< \brief (Lcdc Offset: 0x000003E4) High-End Overlay Configuration Register 22 */
  RwReg LCDC_HEOCFG23;      /**< \brief (Lcdc Offset: 0x000003E8) High-End Overlay Configuration Register 23 */
  RwReg LCDC_HEOCFG24;      /**< \brief (Lcdc Offset: 0x000003EC) High-End Overlay Configuration Register 24 */
  RwReg LCDC_HEOCFG25;      /**< \brief (Lcdc Offset: 0x000003F0) High-End Overlay Configuration Register 25 */
  RwReg LCDC_HEOCFG26;      /**< \brief (Lcdc Offset: 0x000003F4) High-End Overlay Configuration Register 26 */
  RwReg LCDC_HEOCFG27;      /**< \brief (Lcdc Offset: 0x000003F8) High-End Overlay Configuration Register 27 */
  RwReg LCDC_HEOCFG28;      /**< \brief (Lcdc Offset: 0x000003FC) High-End Overlay Configuration Register 28 */
  RwReg LCDC_HEOCFG29;      /**< \brief (Lcdc Offset: 0x00000400) High-End Overlay Configuration Register 29 */
  RwReg LCDC_HEOCFG30;      /**< \brief (Lcdc Offset: 0x00000404) High-End Overlay Configuration Register 30 */
  RwReg LCDC_HEOCFG31;      /**< \brief (Lcdc Offset: 0x00000408) High-End Overlay Configuration Register 31 */
  RwReg LCDC_HEOCFG32;      /**< \brief (Lcdc Offset: 0x0000040C) High-End Overlay Configuration Register 32 */
  RwReg LCDC_HEOCFG33;      /**< \brief (Lcdc Offset: 0x00000410) High-End Overlay Configuration Register 33 */
  RwReg LCDC_HEOCFG34;      /**< \brief (Lcdc Offset: 0x00000414) High-End Overlay Configuration Register 34 */
  RwReg LCDC_HEOCFG35;      /**< \brief (Lcdc Offset: 0x00000418) High-End Overlay Configuration Register 35 */
  RwReg LCDC_HEOCFG36;      /**< \brief (Lcdc Offset: 0x0000041C) High-End Overlay Configuration Register 36 */
  RwReg LCDC_HEOCFG37;      /**< \brief (Lcdc Offset: 0x00000420) High-End Overlay Configuration Register 37 */
  RwReg LCDC_HEOCFG38;      /**< \brief (Lcdc Offset: 0x00000424) High-End Overlay Configuration Register 38 */
  RwReg LCDC_HEOCFG39;      /**< \brief (Lcdc Offset: 0x00000428) High-End Overlay Configuration Register 39 */
  RwReg LCDC_HEOCFG40;      /**< \brief (Lcdc Offset: 0x0000042C) High-End Overlay Configuration Register 40 */
  RwReg LCDC_HEOCFG41;      /**< \brief (Lcdc Offset: 0x00000430) High-End Overlay Configuration Register 41 */
  RoReg Reserved6[3];
  WoReg LCDC_HCRCHER;       /**< \brief (Lcdc Offset: 0x00000440) Hardware Cursor Channel Enable Register */
  WoReg LCDC_HCRCHDR;       /**< \brief (Lcdc Offset: 0x00000444) Hardware Cursor Channel disable Register */
  RoReg LCDC_HCRCHSR;       /**< \brief (Lcdc Offset: 0x00000448) Hardware Cursor Channel Status Register */
  WoReg LCDC_HCRIER;        /**< \brief (Lcdc Offset: 0x0000044C) Hardware Cursor Interrupt Enable Register */
  WoReg LCDC_HCRIDR;        /**< \brief (Lcdc Offset: 0x00000450) Hardware Cursor Interrupt Disable Register */
  RoReg LCDC_HCRIMR;        /**< \brief (Lcdc Offset: 0x00000454) Hardware Cursor Interrupt Mask Register */
  RoReg LCDC_HCRISR;        /**< \brief (Lcdc Offset: 0x00000458) Hardware Cursor Interrupt Status Register */
  RwReg LCDC_HCRHEAD;       /**< \brief (Lcdc Offset: 0x0000045C) Hardware Cursor DMA Head Register */
  RwReg LCDC_HCRADDR;       /**< \brief (Lcdc Offset: 0x00000460) Hardware cursor DMA Address Register */
  RwReg LCDC_HCRCTRL;       /**< \brief (Lcdc Offset: 0x00000464) Hardware Cursor DMA Control Register */
  RwReg LCDC_HCRNEXT;       /**< \brief (Lcdc Offset: 0x00000468) Hardware Cursor DMA NExt Register */
  RwReg LCDC_HCRCFG0;       /**< \brief (Lcdc Offset: 0x0000046C) Hardware Cursor Configuration 0 Register */
  RwReg LCDC_HCRCFG1;       /**< \brief (Lcdc Offset: 0x00000470) Hardware Cursor Configuration 1 Register */
  RwReg LCDC_HCRCFG2;       /**< \brief (Lcdc Offset: 0x00000474) Hardware Cursor Configuration 2 Register */
  RwReg LCDC_HCRCFG3;       /**< \brief (Lcdc Offset: 0x00000478) Hardware Cursor Configuration 3 Register */
  RwReg LCDC_HCRCFG4;       /**< \brief (Lcdc Offset: 0x0000047C) Hardware Cursor Configuration 4 Register */
  RoReg Reserved7[1];
  RwReg LCDC_HCRCFG6;       /**< \brief (Lcdc Offset: 0x00000484) Hardware Cursor Configuration 6 Register */
  RwReg LCDC_HCRCFG7;       /**< \brief (Lcdc Offset: 0x00000488) Hardware Cursor Configuration 7 Register */
  RwReg LCDC_HCRCFG8;       /**< \brief (Lcdc Offset: 0x0000048C) Hardware Cursor Configuration 8 Register */
  RwReg LCDC_HCRCFG9;       /**< \brief (Lcdc Offset: 0x00000490) Hardware Cursor Configuration 9 Register */
  RoReg Reserved8[43];
  WoReg LCDC_PPCHER;        /**< \brief (Lcdc Offset: 0x00000540) Post Processing Channel Enable Register */
  WoReg LCDC_PPCHDR;        /**< \brief (Lcdc Offset: 0x00000544) Post Processing Channel Disable Register */
  RoReg LCDC_PPCHSR;        /**< \brief (Lcdc Offset: 0x00000548) Post Processing Channel Status Register */
  WoReg LCDC_PPIER;         /**< \brief (Lcdc Offset: 0x0000054C) Post Processing Interrupt Enable Register */
  WoReg LCDC_PPIDR;         /**< \brief (Lcdc Offset: 0x00000550) Post Processing Interrupt Disable Register */
  RoReg LCDC_PPIMR;         /**< \brief (Lcdc Offset: 0x00000554) Post Processing Interrupt Mask Register */
  RoReg LCDC_PPISR;         /**< \brief (Lcdc Offset: 0x00000558) Post Processing Interrupt Status Register */
  RwReg LCDC_PPHEAD;        /**< \brief (Lcdc Offset: 0x0000055C) Post Processing Head Register */
  RwReg LCDC_PPADDR;        /**< \brief (Lcdc Offset: 0x00000560) Post Processing Address Register */
  RwReg LCDC_PPCTRL;        /**< \brief (Lcdc Offset: 0x00000564) Post Processing Control Register */
  RwReg LCDC_PPNEXT;        /**< \brief (Lcdc Offset: 0x00000568) Post Processing Next Register */
  RwReg LCDC_PPCFG0;        /**< \brief (Lcdc Offset: 0x0000056C) Post Processing Configuration Register 0 */
  RwReg LCDC_PPCFG1;        /**< \brief (Lcdc Offset: 0x00000570) Post Processing Configuration Register 1 */
  RwReg LCDC_PPCFG2;        /**< \brief (Lcdc Offset: 0x00000574) Post Processing Configuration Register 2 */
  RwReg LCDC_PPCFG3;        /**< \brief (Lcdc Offset: 0x00000578) Post Processing Configuration Register 3 */
  RwReg LCDC_PPCFG4;        /**< \brief (Lcdc Offset: 0x0000057C) Post Processing Configuration Register 4 */
  RwReg LCDC_PPCFG5;        /**< \brief (Lcdc Offset: 0x00000580) Post Processing Configuration Register 5 */
  RoReg Reserved9[31];
  RwReg LCDC_BASECLUT[256]; /**< \brief (Lcdc Offset: 0x600) Base CLUT Register */
  RwReg LCDC_OVR1CLUT[256]; /**< \brief (Lcdc Offset: 0xA00) Overlay 1 CLUT Register */
  RwReg LCDC_OVR2CLUT[256]; /**< \brief (Lcdc Offset: 0xE00) Overlay 2 CLUT Register */
  RwReg LCDC_HEOCLUT[256];  /**< \brief (Lcdc Offset: 0x1200) High End Overlay CLUT Register */
  RwReg LCDC_HCRCLUT[256];  /**< \brief (Lcdc Offset: 0x1600) Hardware Cursor CLUT Register */
} Lcdc;
#endif /* __ASSEMBLY__ */
/* -------- LCDC_LCDCFG0 : (LCDC Offset: 0x00000000) LCD Controller Configuration Register 0 -------- */
#define LCDC_LCDCFG0_CLKPOL (0x1u << 0) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Polarity */
#define LCDC_LCDCFG0_CLKSEL (0x1u << 2) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Source Selection */
#define LCDC_LCDCFG0_CLKPWMSEL (0x1u << 3) /**< \brief (LCDC_LCDCFG0) LCD Controller PWM Clock Source Selection */
#define LCDC_LCDCFG0_CGDISBASE (0x1u << 8) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Base Layer */
#define LCDC_LCDCFG0_CGDISOVR1 (0x1u << 9) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Overlay 1 Layer */
#define LCDC_LCDCFG0_CGDISOVR2 (0x1u << 10) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Overlay 2 Layer */
#define LCDC_LCDCFG0_CGDISHEO (0x1u << 11) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the High End Overlay */
#define LCDC_LCDCFG0_CGDISHCR (0x1u << 12) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Hardware Cursor Layer */
#define LCDC_LCDCFG0_CGDISPP (0x1u << 13) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Post Processing Layer */
#define LCDC_LCDCFG0_CLKDIV_Pos 16
#define LCDC_LCDCFG0_CLKDIV_Msk (0xffu << LCDC_LCDCFG0_CLKDIV_Pos) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Divider */
#define LCDC_LCDCFG0_CLKDIV(value) ((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
/* -------- LCDC_LCDCFG1 : (LCDC Offset: 0x00000004) LCD Controller Configuration Register 1 -------- */
#define LCDC_LCDCFG1_HSPW_Pos 0
#define LCDC_LCDCFG1_HSPW_Msk (0x3fu << LCDC_LCDCFG1_HSPW_Pos) /**< \brief (LCDC_LCDCFG1) Horizontal Synchronization Pulse Width */
#define LCDC_LCDCFG1_HSPW(value) ((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
#define LCDC_LCDCFG1_VSPW_Pos 16
#define LCDC_LCDCFG1_VSPW_Msk (0x3fu << LCDC_LCDCFG1_VSPW_Pos) /**< \brief (LCDC_LCDCFG1) Vertical Synchronization Pulse Width */
#define LCDC_LCDCFG1_VSPW(value) ((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
/* -------- LCDC_LCDCFG2 : (LCDC Offset: 0x00000008) LCD Controller Configuration Register 2 -------- */
#define LCDC_LCDCFG2_VFPW_Pos 0
#define LCDC_LCDCFG2_VFPW_Msk (0x3fu << LCDC_LCDCFG2_VFPW_Pos) /**< \brief (LCDC_LCDCFG2) Vertical Front Porch Width */
#define LCDC_LCDCFG2_VFPW(value) ((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
#define LCDC_LCDCFG2_VBPW_Pos 16
#define LCDC_LCDCFG2_VBPW_Msk (0x3fu << LCDC_LCDCFG2_VBPW_Pos) /**< \brief (LCDC_LCDCFG2) Vertical Back Porch Width */
#define LCDC_LCDCFG2_VBPW(value) ((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
/* -------- LCDC_LCDCFG3 : (LCDC Offset: 0x0000000C) LCD Controller Configuration Register 3 -------- */
#define LCDC_LCDCFG3_HFPW_Pos 0
#define LCDC_LCDCFG3_HFPW_Msk (0x1ffu << LCDC_LCDCFG3_HFPW_Pos) /**< \brief (LCDC_LCDCFG3) Horizontal Front Porch Width */
#define LCDC_LCDCFG3_HFPW(value) ((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
#define LCDC_LCDCFG3_HBPW_Pos 16
#define LCDC_LCDCFG3_HBPW_Msk (0x1ffu << LCDC_LCDCFG3_HBPW_Pos) /**< \brief (LCDC_LCDCFG3) Horizontal Back Porch Width */
#define LCDC_LCDCFG3_HBPW(value) ((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
/* -------- LCDC_LCDCFG4 : (LCDC Offset: 0x00000010) LCD Controller Configuration Register 4 -------- */
#define LCDC_LCDCFG4_PPL_Pos 0
#define LCDC_LCDCFG4_PPL_Msk (0x7ffu << LCDC_LCDCFG4_PPL_Pos) /**< \brief (LCDC_LCDCFG4) Number of Pixels Per Line */
#define LCDC_LCDCFG4_PPL(value) ((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
#define LCDC_LCDCFG4_RPF_Pos 16
#define LCDC_LCDCFG4_RPF_Msk (0x7ffu << LCDC_LCDCFG4_RPF_Pos) /**< \brief (LCDC_LCDCFG4) Number of Active Row Per Frame */
#define LCDC_LCDCFG4_RPF(value) ((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
/* -------- LCDC_LCDCFG5 : (LCDC Offset: 0x00000014) LCD Controller Configuration Register 5 -------- */
#define LCDC_LCDCFG5_HSPOL (0x1u << 0) /**< \brief (LCDC_LCDCFG5) Horizontal Synchronization Pulse Polarity */
#define LCDC_LCDCFG5_VSPOL (0x1u << 1) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse Polarity */
#define LCDC_LCDCFG5_VSPDLYS (0x1u << 2) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse Start */
#define LCDC_LCDCFG5_VSPDLYE (0x1u << 3) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse End */
#define LCDC_LCDCFG5_DISPPOL (0x1u << 4) /**< \brief (LCDC_LCDCFG5) Display Signal Polarity */
#define LCDC_LCDCFG5_DITHER (0x1u << 6) /**< \brief (LCDC_LCDCFG5) LCD Controller Dithering */
#define LCDC_LCDCFG5_DISPDLY (0x1u << 7) /**< \brief (LCDC_LCDCFG5) LCD Controller Display Power Signal Synchronization */
#define LCDC_LCDCFG5_MODE_Pos 8
#define LCDC_LCDCFG5_MODE_Msk (0x3u << LCDC_LCDCFG5_MODE_Pos) /**< \brief (LCDC_LCDCFG5) LCD Controller Output Mode */
#define   LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0u << 8) /**< \brief (LCDC_LCDCFG5) LCD output mode is set to 12 bits per pixel */
#define   LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1u << 8) /**< \brief (LCDC_LCDCFG5) LCD output mode is set to 16 bits per pixel */
#define   LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2u << 8) /**< \brief (LCDC_LCDCFG5) LCD output mode is set to 18 bits per pixel */
#define   LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3u << 8) /**< \brief (LCDC_LCDCFG5) LCD output mode is set to 24 bits per pixel */
#define LCDC_LCDCFG5_PP (0x1u << 10) /**< \brief (LCDC_LCDCFG5) Post Processing Enable */
#define LCDC_LCDCFG5_VSPSU (0x1u << 12) /**< \brief (LCDC_LCDCFG5) LCD Controller Vertical synchronization Pulse Setup Configuration */
#define LCDC_LCDCFG5_VSPHO (0x1u << 13) /**< \brief (LCDC_LCDCFG5) LCD Controller Vertical synchronization Pulse Hold Configuration */
#define LCDC_LCDCFG5_GUARDTIME_Pos 16
#define LCDC_LCDCFG5_GUARDTIME_Msk (0x1fu << LCDC_LCDCFG5_GUARDTIME_Pos) /**< \brief (LCDC_LCDCFG5) LCD DISPLAY Guard Time */
#define LCDC_LCDCFG5_GUARDTIME(value) ((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
/* -------- LCDC_LCDCFG6 : (LCDC Offset: 0x00000018) LCD Controller Configuration Register 6 -------- */
#define LCDC_LCDCFG6_PWMPS_Pos 0
#define LCDC_LCDCFG6_PWMPS_Msk (0x7u << LCDC_LCDCFG6_PWMPS_Pos) /**< \brief (LCDC_LCDCFG6) PWM Clock Prescaler */
#define LCDC_LCDCFG6_PWMPS(value) ((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
#define LCDC_LCDCFG6_PWMPOL (0x1u << 4) /**< \brief (LCDC_LCDCFG6) LCD Controller PWM Signal Polarity */
#define LCDC_LCDCFG6_PWMCVAL_Pos 8
#define LCDC_LCDCFG6_PWMCVAL_Msk (0xffu << LCDC_LCDCFG6_PWMCVAL_Pos) /**< \brief (LCDC_LCDCFG6) LCD Controller PWM Compare Value */
#define LCDC_LCDCFG6_PWMCVAL(value) ((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
/* -------- LCDC_LCDEN : (LCDC Offset: 0x00000020) LCD Controller Enable Register -------- */
#define LCDC_LCDEN_CLKEN (0x1u << 0) /**< \brief (LCDC_LCDEN) LCD Controller Pixel Clock Enable */
#define LCDC_LCDEN_SYNCEN (0x1u << 1) /**< \brief (LCDC_LCDEN) LCD Controller Horizontal and Vertical Synchronization Enable */
#define LCDC_LCDEN_DISPEN (0x1u << 2) /**< \brief (LCDC_LCDEN) LCD Controller DISP Signal Enable */
#define LCDC_LCDEN_PWMEN (0x1u << 3) /**< \brief (LCDC_LCDEN) LCD Controller Pulse Width Modulation Enable */
/* -------- LCDC_LCDDIS : (LCDC Offset: 0x00000024) LCD Controller Disable Register -------- */
#define LCDC_LCDDIS_CLKDIS (0x1u << 0) /**< \brief (LCDC_LCDDIS) LCD Controller Pixel Clock Disable */
#define LCDC_LCDDIS_SYNCDIS (0x1u << 1) /**< \brief (LCDC_LCDDIS) LCD Controller Horizontal and Vertical Synchronization Disable */
#define LCDC_LCDDIS_DISPDIS (0x1u << 2) /**< \brief (LCDC_LCDDIS) LCD Controller DISP Signal Disable */
#define LCDC_LCDDIS_PWMDIS (0x1u << 3) /**< \brief (LCDC_LCDDIS) LCD Controller Pulse Width Modulation Disable */
#define LCDC_LCDDIS_CLKRST (0x1u << 8) /**< \brief (LCDC_LCDDIS) LCD Controller Clock Reset */
#define LCDC_LCDDIS_SYNCRST (0x1u << 9) /**< \brief (LCDC_LCDDIS) LCD Controller Horizontal and Vertical Synchronization Reset */
#define LCDC_LCDDIS_DISPRST (0x1u << 10) /**< \brief (LCDC_LCDDIS) LCD Controller DISP Signal Reset */
#define LCDC_LCDDIS_PWMRST (0x1u << 11) /**< \brief (LCDC_LCDDIS) LCD Controller PWM Reset */
/* -------- LCDC_LCDSR : (LCDC Offset: 0x00000028) LCD Controller Status Register -------- */
#define LCDC_LCDSR_CLKSTS (0x1u << 0) /**< \brief (LCDC_LCDSR) Clock Status */
#define LCDC_LCDSR_LCDSTS (0x1u << 1) /**< \brief (LCDC_LCDSR) LCD Controller Synchronization status */
#define LCDC_LCDSR_DISPSTS (0x1u << 2) /**< \brief (LCDC_LCDSR) LCD Controller DISP Signal Status */
#define LCDC_LCDSR_PWMSTS (0x1u << 3) /**< \brief (LCDC_LCDSR) LCD Controller PWM Signal Status */
#define LCDC_LCDSR_SIPSTS (0x1u << 4) /**< \brief (LCDC_LCDSR) Synchronization In Progress */
/* -------- LCDC_LCDIER : (LCDC Offset: 0x0000002C) LCD Controller Interrupt Enable Register -------- */
#define LCDC_LCDIER_SOFIE (0x1u << 0) /**< \brief (LCDC_LCDIER) Start of Frame Interrupt Enable Register */
#define LCDC_LCDIER_DISIE (0x1u << 1) /**< \brief (LCDC_LCDIER) LCD Disable Interrupt Enable Register */
#define LCDC_LCDIER_DISPIE (0x1u << 2) /**< \brief (LCDC_LCDIER) Power UP/Down Sequence Terminated Interrupt Enable Register */
#define LCDC_LCDIER_FIFOERRIE (0x1u << 4) /**< \brief (LCDC_LCDIER) Output FIFO Error Interrupt Enable Register */
#define LCDC_LCDIER_BASEIE (0x1u << 8) /**< \brief (LCDC_LCDIER) Base Layer Interrupt Enable Register */
#define LCDC_LCDIER_OVR1IE (0x1u << 9) /**< \brief (LCDC_LCDIER) Overlay 1 Interrupt Enable Register */
#define LCDC_LCDIER_OVR2IE (0x1u << 10) /**< \brief (LCDC_LCDIER) Overlay 2 Interrupt Enable Register */
#define LCDC_LCDIER_HEOIE (0x1u << 11) /**< \brief (LCDC_LCDIER) High End Overlay Interrupt Enable Register */
#define LCDC_LCDIER_HCRIE (0x1u << 12) /**< \brief (LCDC_LCDIER) Hardware Cursor Interrupt Enable Register */
#define LCDC_LCDIER_PPIE (0x1u << 13) /**< \brief (LCDC_LCDIER) Post Processing Interrupt Enable Register */
/* -------- LCDC_LCDIDR : (LCDC Offset: 0x00000030) LCD Controller Interrupt Disable Register -------- */
#define LCDC_LCDIDR_SOFID (0x1u << 0) /**< \brief (LCDC_LCDIDR) Start of Frame Interrupt Disable Register */
#define LCDC_LCDIDR_DISID (0x1u << 1) /**< \brief (LCDC_LCDIDR) LCD Disable Interrupt Disable Register */
#define LCDC_LCDIDR_DISPID (0x1u << 2) /**< \brief (LCDC_LCDIDR) Power UP/Down Sequence Terminated Interrupt Disable Register */
#define LCDC_LCDIDR_FIFOERRID (0x1u << 4) /**< \brief (LCDC_LCDIDR) Output FIFO Error Interrupt Disable Register */
#define LCDC_LCDIDR_BASEID (0x1u << 8) /**< \brief (LCDC_LCDIDR) Base Layer Interrupt Disable Register */
#define LCDC_LCDIDR_OVR1ID (0x1u << 9) /**< \brief (LCDC_LCDIDR) Overlay 1 Interrupt Disable Register */
#define LCDC_LCDIDR_OVR2ID (0x1u << 10) /**< \brief (LCDC_LCDIDR) Overlay 2 Interrupt Disable Register */
#define LCDC_LCDIDR_HEOID (0x1u << 11) /**< \brief (LCDC_LCDIDR) High End Overlay Interrupt Disable Register */
#define LCDC_LCDIDR_HCRID (0x1u << 12) /**< \brief (LCDC_LCDIDR) Hardware Cursor Interrupt Disable Register */
#define LCDC_LCDIDR_PPID (0x1u << 13) /**< \brief (LCDC_LCDIDR) Post Processing Interrupt Disable Register */
/* -------- LCDC_LCDIMR : (LCDC Offset: 0x00000034) LCD Controller Interrupt Mask Register -------- */
#define LCDC_LCDIMR_SOFIM (0x1u << 0) /**< \brief (LCDC_LCDIMR) Start of Frame Interrupt Mask Register */
#define LCDC_LCDIMR_DISIM (0x1u << 1) /**< \brief (LCDC_LCDIMR) LCD Disable Interrupt Mask Register */
#define LCDC_LCDIMR_DISPIM (0x1u << 2) /**< \brief (LCDC_LCDIMR) Power UP/Down Sequence Terminated Interrupt Mask Register */
#define LCDC_LCDIMR_FIFOERRIM (0x1u << 4) /**< \brief (LCDC_LCDIMR) Output FIFO Error Interrupt Mask Register */
#define LCDC_LCDIMR_BASEIM (0x1u << 8) /**< \brief (LCDC_LCDIMR) Base Layer Interrupt Mask Register */
#define LCDC_LCDIMR_OVR1IM (0x1u << 9) /**< \brief (LCDC_LCDIMR) Overlay 1 Interrupt Mask Register */
#define LCDC_LCDIMR_OVR2IM (0x1u << 10) /**< \brief (LCDC_LCDIMR) Overlay 2 Interrupt Mask Register */
#define LCDC_LCDIMR_HEOIM (0x1u << 11) /**< \brief (LCDC_LCDIMR) High End Overlay Interrupt Mask Register */
#define LCDC_LCDIMR_HCRIM (0x1u << 12) /**< \brief (LCDC_LCDIMR) Hardware Cursor Interrupt Mask Register */
#define LCDC_LCDIMR_PPIM (0x1u << 13) /**< \brief (LCDC_LCDIMR) Post Processing Interrupt Mask Register */
/* -------- LCDC_LCDISR : (LCDC Offset: 0x00000038) LCD Controller Interrupt Status Register -------- */
#define LCDC_LCDISR_SOF (0x1u << 0) /**< \brief (LCDC_LCDISR) Start of Frame Interrupt Status Register */
#define LCDC_LCDISR_DIS (0x1u << 1) /**< \brief (LCDC_LCDISR) LCD Disable Interrupt Status Register */
#define LCDC_LCDISR_DISP (0x1u << 2) /**< \brief (LCDC_LCDISR) Power-up/Power-down Sequence Terminated Interrupt Status Register */
#define LCDC_LCDISR_FIFOERR (0x1u << 4) /**< \brief (LCDC_LCDISR) Output FIFO Error */
#define LCDC_LCDISR_BASE (0x1u << 8) /**< \brief (LCDC_LCDISR) Base Layer Raw Interrupt Status Register */
#define LCDC_LCDISR_OVR1 (0x1u << 9) /**< \brief (LCDC_LCDISR) Overlay 1 Raw Interrupt Status Register */
#define LCDC_LCDISR_OVR2 (0x1u << 10) /**< \brief (LCDC_LCDISR) Overlay 2 Raw Interrupt Status Register */
#define LCDC_LCDISR_HEO (0x1u << 11) /**< \brief (LCDC_LCDISR) High End Overlay Raw Interrupt Status Register */
#define LCDC_LCDISR_HCR (0x1u << 12) /**< \brief (LCDC_LCDISR) Hardware Cursor Raw Interrupt Status Register */
#define LCDC_LCDISR_PP (0x1u << 13) /**< \brief (LCDC_LCDISR) Post Processing Raw Interrupt Status Register */
/* -------- LCDC_BASECHER : (LCDC Offset: 0x00000040) Base Layer Channel Enable Register -------- */
#define LCDC_BASECHER_CHEN (0x1u << 0) /**< \brief (LCDC_BASECHER) Channel Enable Register */
#define LCDC_BASECHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_BASECHER) Update Overlay Attributes Enable Register */
#define LCDC_BASECHER_A2QEN (0x1u << 2) /**< \brief (LCDC_BASECHER) Add Head Pointer Enable Register */
/* -------- LCDC_BASECHDR : (LCDC Offset: 0x00000044) Base Layer Channel Disable Register -------- */
#define LCDC_BASECHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_BASECHDR) Channel Disable Register */
#define LCDC_BASECHDR_CHRST (0x1u << 8) /**< \brief (LCDC_BASECHDR) Channel Reset Register */
/* -------- LCDC_BASECHSR : (LCDC Offset: 0x00000048) Base Layer Channel Status Register -------- */
#define LCDC_BASECHSR_CHSR (0x1u << 0) /**< \brief (LCDC_BASECHSR) Channel Status Register */
#define LCDC_BASECHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_BASECHSR) Update Overlay Attributes In Progress */
#define LCDC_BASECHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_BASECHSR) Add To Queue Pending Register */
/* -------- LCDC_BASEIER : (LCDC Offset: 0x0000004C) Base Layer Interrupt Enable Register -------- */
#define LCDC_BASEIER_DMA (0x1u << 2) /**< \brief (LCDC_BASEIER) End of DMA Transfer Interrupt Enable Register */
#define LCDC_BASEIER_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIER) Descriptor Loaded Interrupt Enable Register */
#define LCDC_BASEIER_ADD (0x1u << 4) /**< \brief (LCDC_BASEIER) Head Descriptor Loaded Interrupt Enable Register */
#define LCDC_BASEIER_DONE (0x1u << 5) /**< \brief (LCDC_BASEIER) End of List Interrupt Enable Register */
#define LCDC_BASEIER_OVR (0x1u << 6) /**< \brief (LCDC_BASEIER) Overflow Interrupt Enable Register */
/* -------- LCDC_BASEIDR : (LCDC Offset: 0x00000050) Base Layer Interrupt Disabled Register -------- */
#define LCDC_BASEIDR_DMA (0x1u << 2) /**< \brief (LCDC_BASEIDR) End of DMA Transfer Interrupt Disable Register */
#define LCDC_BASEIDR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIDR) Descriptor Loaded Interrupt Disable Register */
#define LCDC_BASEIDR_ADD (0x1u << 4) /**< \brief (LCDC_BASEIDR) Head Descriptor Loaded Interrupt Disable Register */
#define LCDC_BASEIDR_DONE (0x1u << 5) /**< \brief (LCDC_BASEIDR) End of List Interrupt Disable Register */
#define LCDC_BASEIDR_OVR (0x1u << 6) /**< \brief (LCDC_BASEIDR) Overflow Interrupt Disable Register */
/* -------- LCDC_BASEIMR : (LCDC Offset: 0x00000054) Base Layer Interrupt Mask Register -------- */
#define LCDC_BASEIMR_DMA (0x1u << 2) /**< \brief (LCDC_BASEIMR) End of DMA Transfer Interrupt Mask Register */
#define LCDC_BASEIMR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIMR) Descriptor Loaded Interrupt Mask Register */
#define LCDC_BASEIMR_ADD (0x1u << 4) /**< \brief (LCDC_BASEIMR) Head Descriptor Loaded Interrupt Mask Register */
#define LCDC_BASEIMR_DONE (0x1u << 5) /**< \brief (LCDC_BASEIMR) End of List Interrupt Mask Register */
#define LCDC_BASEIMR_OVR (0x1u << 6) /**< \brief (LCDC_BASEIMR) Overflow Interrupt Mask Register */
/* -------- LCDC_BASEISR : (LCDC Offset: 0x00000058) Base Layer Interrupt status Register -------- */
#define LCDC_BASEISR_DMA (0x1u << 2) /**< \brief (LCDC_BASEISR) End of DMA Transfer */
#define LCDC_BASEISR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEISR) DMA Descriptor Loaded */
#define LCDC_BASEISR_ADD (0x1u << 4) /**< \brief (LCDC_BASEISR) Head Descriptor Loaded */
#define LCDC_BASEISR_DONE (0x1u << 5) /**< \brief (LCDC_BASEISR) End of List Detected */
#define LCDC_BASEISR_OVR (0x1u << 6) /**< \brief (LCDC_BASEISR) Overflow Detected */
/* -------- LCDC_BASEHEAD : (LCDC Offset: 0x0000005C) Base DMA Head Register -------- */
#define LCDC_BASEHEAD_HEAD_Pos 2
#define LCDC_BASEHEAD_HEAD_Msk (0x3fffffffu << LCDC_BASEHEAD_HEAD_Pos) /**< \brief (LCDC_BASEHEAD) DMA Head Pointer */
#define LCDC_BASEHEAD_HEAD(value) ((LCDC_BASEHEAD_HEAD_Msk & ((value) << LCDC_BASEHEAD_HEAD_Pos)))
/* -------- LCDC_BASEADDR : (LCDC Offset: 0x00000060) Base DMA Address Register -------- */
#define LCDC_BASEADDR_ADDR_Pos 0
#define LCDC_BASEADDR_ADDR_Msk (0xffffffffu << LCDC_BASEADDR_ADDR_Pos) /**< \brief (LCDC_BASEADDR) DMA Transfer Start Address */
#define LCDC_BASEADDR_ADDR(value) ((LCDC_BASEADDR_ADDR_Msk & ((value) << LCDC_BASEADDR_ADDR_Pos)))
/* -------- LCDC_BASECTRL : (LCDC Offset: 0x00000064) Base DMA Control Register -------- */
#define LCDC_BASECTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_BASECTRL) Transfer Descriptor Fetch Enable */
#define LCDC_BASECTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_BASECTRL) Lookup Table Fetch Enable */
#define LCDC_BASECTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_BASECTRL) End of DMA Transfer Interrupt Enable */
#define LCDC_BASECTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_BASECTRL) Descriptor Loaded Interrupt Enable */
#define LCDC_BASECTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_BASECTRL) Add Head Descriptor to Queue Interrupt Enable */
#define LCDC_BASECTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_BASECTRL) End of List Interrupt Enable */
/* -------- LCDC_BASENEXT : (LCDC Offset: 0x00000068) Base DMA Next Register -------- */
#define LCDC_BASENEXT_NEXT_Pos 0
#define LCDC_BASENEXT_NEXT_Msk (0xffffffffu << LCDC_BASENEXT_NEXT_Pos) /**< \brief (LCDC_BASENEXT) DMA Descriptor Next Address */
#define LCDC_BASENEXT_NEXT(value) ((LCDC_BASENEXT_NEXT_Msk & ((value) << LCDC_BASENEXT_NEXT_Pos)))
/* -------- LCDC_BASECFG0 : (LCDC Offset: 0x0000006C) Base Configuration register 0 -------- */
#define LCDC_BASECFG0_SIF (0x1u << 0) /**< \brief (LCDC_BASECFG0) Source Interface */
#define LCDC_BASECFG0_BLEN_Pos 4
#define LCDC_BASECFG0_BLEN_Msk (0x3u << LCDC_BASECFG0_BLEN_Pos) /**< \brief (LCDC_BASECFG0) AHB Burst Length */
#define   LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define LCDC_BASECFG0_DLBO (0x1u << 8) /**< \brief (LCDC_BASECFG0) Defined Length Burst Only For Channel Bus Transaction. */
/* -------- LCDC_BASECFG1 : (LCDC Offset: 0x00000070) Base Configuration register 1 -------- */
#define LCDC_BASECFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_BASECFG1) Color Lookup Table Enable */
#define LCDC_BASECFG1_RGBMODE_Pos 4
#define LCDC_BASECFG1_RGBMODE_Msk (0xfu << LCDC_BASECFG1_RGBMODE_Pos) /**< \brief (LCDC_BASECFG1) RGB Input Mode Selection */
#define   LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_BASECFG1) 12 bpp RGB 444 */
#define   LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp ARGB 4444 */
#define   LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp RGBA 4444 */
#define   LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp RGB 565 */
#define   LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp TRGB 1555 */
#define   LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_BASECFG1) 18 bpp RGB 666 */
#define   LCDC_BASECFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_BASECFG1) 18 bpp RGB 666 PACKED */
#define   LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_BASECFG1) 19 bpp TRGB 1666 */
#define   LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_BASECFG1) 19 bpp TRGB 1666 PACKED */
#define   LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_BASECFG1) 24 bpp RGB 888 */
#define   LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_BASECFG1) 24 bpp RGB 888 PACKED */
#define   LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_BASECFG1) 25 bpp TRGB 1888 */
#define   LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_BASECFG1) 32 bpp ARGB 8888 */
#define   LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_BASECFG1) 32 bpp RGBA 8888 */
#define LCDC_BASECFG1_CLUTMODE_Pos 8
#define LCDC_BASECFG1_CLUTMODE_Msk (0x3u << LCDC_BASECFG1_CLUTMODE_Pos) /**< \brief (LCDC_BASECFG1) Color Lookup Table Input Mode Selection */
#define   LCDC_BASECFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_BASECFG1) color lookup table mode set to 1 bit per pixel */
#define   LCDC_BASECFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_BASECFG1) color lookup table mode set to 2 bits per pixel */
#define   LCDC_BASECFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_BASECFG1) color lookup table mode set to 4 bits per pixel */
#define   LCDC_BASECFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_BASECFG1) color lookup table mode set to 8 bits per pixel */
/* -------- LCDC_BASECFG2 : (LCDC Offset: 0x00000074) Base Configuration register 2 -------- */
#define LCDC_BASECFG2_XSTRIDE_Pos 0
#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffffu << LCDC_BASECFG2_XSTRIDE_Pos) /**< \brief (LCDC_BASECFG2) Horizontal Stride */
#define LCDC_BASECFG2_XSTRIDE(value) ((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
/* -------- LCDC_BASECFG3 : (LCDC Offset: 0x00000078) Base Configuration register 3 -------- */
#define LCDC_BASECFG3_BDEF_Pos 0
#define LCDC_BASECFG3_BDEF_Msk (0xffu << LCDC_BASECFG3_BDEF_Pos) /**< \brief (LCDC_BASECFG3) Blue Default */
#define LCDC_BASECFG3_BDEF(value) ((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
#define LCDC_BASECFG3_GDEF_Pos 8
#define LCDC_BASECFG3_GDEF_Msk (0xffu << LCDC_BASECFG3_GDEF_Pos) /**< \brief (LCDC_BASECFG3) Green Default */
#define LCDC_BASECFG3_GDEF(value) ((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
#define LCDC_BASECFG3_RDEF_Pos 16
#define LCDC_BASECFG3_RDEF_Msk (0xffu << LCDC_BASECFG3_RDEF_Pos) /**< \brief (LCDC_BASECFG3) Red Default */
#define LCDC_BASECFG3_RDEF(value) ((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
/* -------- LCDC_BASECFG4 : (LCDC Offset: 0x0000007C) Base Configuration register 4 -------- */
#define LCDC_BASECFG4_DMA (0x1u << 8) /**< \brief (LCDC_BASECFG4) Use DMA Data Path */
#define LCDC_BASECFG4_REP (0x1u << 9) /**< \brief (LCDC_BASECFG4) Use Replication logic to expand RGB color to 24 bits */
#define LCDC_BASECFG4_DISCEN (0x1u << 11) /**< \brief (LCDC_BASECFG4) Discard Area Enable */
/* -------- LCDC_BASECFG5 : (LCDC Offset: 0x00000080) Base Configuration register 5 -------- */
#define LCDC_BASECFG5_DISCXPOS_Pos 0
#define LCDC_BASECFG5_DISCXPOS_Msk (0x7ffu << LCDC_BASECFG5_DISCXPOS_Pos) /**< \brief (LCDC_BASECFG5) Discard Area horizontal coordinate */
#define LCDC_BASECFG5_DISCXPOS(value) ((LCDC_BASECFG5_DISCXPOS_Msk & ((value) << LCDC_BASECFG5_DISCXPOS_Pos)))
#define LCDC_BASECFG5_DISCYPOS_Pos 16
#define LCDC_BASECFG5_DISCYPOS_Msk (0x7ffu << LCDC_BASECFG5_DISCYPOS_Pos) /**< \brief (LCDC_BASECFG5) Discard Area Vertical coordinate */
#define LCDC_BASECFG5_DISCYPOS(value) ((LCDC_BASECFG5_DISCYPOS_Msk & ((value) << LCDC_BASECFG5_DISCYPOS_Pos)))
/* -------- LCDC_BASECFG6 : (LCDC Offset: 0x00000084) Base Configuration register 6 -------- */
#define LCDC_BASECFG6_DISCXSIZE_Pos 0
#define LCDC_BASECFG6_DISCXSIZE_Msk (0x7ffu << LCDC_BASECFG6_DISCXSIZE_Pos) /**< \brief (LCDC_BASECFG6) Discard Area Horizontal Size */
#define LCDC_BASECFG6_DISCXSIZE(value) ((LCDC_BASECFG6_DISCXSIZE_Msk & ((value) << LCDC_BASECFG6_DISCXSIZE_Pos)))
#define LCDC_BASECFG6_DISCYSIZE_Pos 16
#define LCDC_BASECFG6_DISCYSIZE_Msk (0x7ffu << LCDC_BASECFG6_DISCYSIZE_Pos) /**< \brief (LCDC_BASECFG6) Discard Area Vertical Size */
#define LCDC_BASECFG6_DISCYSIZE(value) ((LCDC_BASECFG6_DISCYSIZE_Msk & ((value) << LCDC_BASECFG6_DISCYSIZE_Pos)))
/* -------- LCDC_OVR1CHER : (LCDC Offset: 0x00000140) Overlay 1 Channel Enable Register -------- */
#define LCDC_OVR1CHER_CHEN (0x1u << 0) /**< \brief (LCDC_OVR1CHER) Channel Enable Register */
#define LCDC_OVR1CHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_OVR1CHER) Update Overlay Attributes Enable Register */
#define LCDC_OVR1CHER_A2QEN (0x1u << 2) /**< \brief (LCDC_OVR1CHER) Add Head Pointer Enable Register */
/* -------- LCDC_OVR1CHDR : (LCDC Offset: 0x00000144) Overlay 1 Channel Disable Register -------- */
#define LCDC_OVR1CHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_OVR1CHDR) Channel Disable Register */
#define LCDC_OVR1CHDR_CHRST (0x1u << 8) /**< \brief (LCDC_OVR1CHDR) Channel Reset Register */
/* -------- LCDC_OVR1CHSR : (LCDC Offset: 0x00000148) Overlay 1 Channel Status Register -------- */
#define LCDC_OVR1CHSR_CHSR (0x1u << 0) /**< \brief (LCDC_OVR1CHSR) Channel Status Register */
#define LCDC_OVR1CHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_OVR1CHSR) Update Overlay Attributes In Progress */
#define LCDC_OVR1CHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_OVR1CHSR) Add to Queue Pending Register */
/* -------- LCDC_OVR1IER : (LCDC Offset: 0x0000014C) Overlay 1 Interrupt Enable Register -------- */
#define LCDC_OVR1IER_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IER) End of DMA Transfer Interrupt Enable Register */
#define LCDC_OVR1IER_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IER) Descriptor Loaded Interrupt Enable Register */
#define LCDC_OVR1IER_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IER) Head Descriptor Loaded Interrupt Enable Register */
#define LCDC_OVR1IER_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IER) End of List Interrupt Enable Register */
#define LCDC_OVR1IER_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IER) Overflow Interrupt Enable Register */
/* -------- LCDC_OVR1IDR : (LCDC Offset: 0x00000150) Overlay 1 Interrupt Disable Register -------- */
#define LCDC_OVR1IDR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IDR) End of DMA Transfer Interrupt Disable Register */
#define LCDC_OVR1IDR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IDR) Descriptor Loaded Interrupt Disable Register */
#define LCDC_OVR1IDR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IDR) Head Descriptor Loaded Interrupt Disable Register */
#define LCDC_OVR1IDR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IDR) End of List Interrupt Disable Register */
#define LCDC_OVR1IDR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IDR) Overflow Interrupt Disable Register */
/* -------- LCDC_OVR1IMR : (LCDC Offset: 0x00000154) Overlay 1 Interrupt Mask Register -------- */
#define LCDC_OVR1IMR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IMR) End of DMA Transfer Interrupt Mask Register */
#define LCDC_OVR1IMR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IMR) Descriptor Loaded Interrupt Mask Register */
#define LCDC_OVR1IMR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IMR) Head Descriptor Loaded Interrupt Mask Register */
#define LCDC_OVR1IMR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IMR) End of List Interrupt Mask Register */
#define LCDC_OVR1IMR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IMR) Overflow Interrupt Mask Register */
/* -------- LCDC_OVR1ISR : (LCDC Offset: 0x00000158) Overlay 1 Interrupt Status Register -------- */
#define LCDC_OVR1ISR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1ISR) End of DMA Transfer */
#define LCDC_OVR1ISR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1ISR) DMA Descriptor Loaded */
#define LCDC_OVR1ISR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1ISR) Head Descriptor Loaded */
#define LCDC_OVR1ISR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1ISR) End of List Detected Register */
#define LCDC_OVR1ISR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1ISR) Overflow Detected */
/* -------- LCDC_OVR1HEAD : (LCDC Offset: 0x0000015C) Overlay 1 DMA Head Register -------- */
#define LCDC_OVR1HEAD_HEAD_Pos 2
#define LCDC_OVR1HEAD_HEAD_Msk (0x3fffffffu << LCDC_OVR1HEAD_HEAD_Pos) /**< \brief (LCDC_OVR1HEAD) DMA Head Pointer */
#define LCDC_OVR1HEAD_HEAD(value) ((LCDC_OVR1HEAD_HEAD_Msk & ((value) << LCDC_OVR1HEAD_HEAD_Pos)))
/* -------- LCDC_OVR1ADDR : (LCDC Offset: 0x00000160) Overlay 1 DMA Address Register -------- */
#define LCDC_OVR1ADDR_ADDR_Pos 0
#define LCDC_OVR1ADDR_ADDR_Msk (0xffffffffu << LCDC_OVR1ADDR_ADDR_Pos) /**< \brief (LCDC_OVR1ADDR) DMA Transfer Overlay 1 Address */
#define LCDC_OVR1ADDR_ADDR(value) ((LCDC_OVR1ADDR_ADDR_Msk & ((value) << LCDC_OVR1ADDR_ADDR_Pos)))
/* -------- LCDC_OVR1CTRL : (LCDC Offset: 0x00000164) Overlay1 DMA Control Register -------- */
#define LCDC_OVR1CTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_OVR1CTRL) Transfer Descriptor Fetch Enable */
#define LCDC_OVR1CTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_OVR1CTRL) Lookup Table Fetch Enable */
#define LCDC_OVR1CTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_OVR1CTRL) End of DMA Transfer Interrupt Enable */
#define LCDC_OVR1CTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_OVR1CTRL) Descriptor Loaded Interrupt Enable */
#define LCDC_OVR1CTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_OVR1CTRL) Add Head Descriptor to Queue Interrupt Enable */
#define LCDC_OVR1CTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_OVR1CTRL) End of List Interrupt Enable */
/* -------- LCDC_OVR1NEXT : (LCDC Offset: 0x00000168) Overlay1 DMA Next Register -------- */
#define LCDC_OVR1NEXT_NEXT_Pos 0
#define LCDC_OVR1NEXT_NEXT_Msk (0xffffffffu << LCDC_OVR1NEXT_NEXT_Pos) /**< \brief (LCDC_OVR1NEXT) DMA Descriptor Next Address */
#define LCDC_OVR1NEXT_NEXT(value) ((LCDC_OVR1NEXT_NEXT_Msk & ((value) << LCDC_OVR1NEXT_NEXT_Pos)))
/* -------- LCDC_OVR1CFG0 : (LCDC Offset: 0x0000016C) Overlay 1 Configuration 0 Register -------- */
#define LCDC_OVR1CFG0_SIF (0x1u << 0) /**< \brief (LCDC_OVR1CFG0) Source Interface */
#define LCDC_OVR1CFG0_BLEN_Pos 4
#define LCDC_OVR1CFG0_BLEN_Msk (0x3u << LCDC_OVR1CFG0_BLEN_Pos) /**< \brief (LCDC_OVR1CFG0) AHB Burst Length */
#define   LCDC_OVR1CFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define LCDC_OVR1CFG0_DLBO (0x1u << 8) /**< \brief (LCDC_OVR1CFG0) Defined Length Burst Only for Channel Bus Transaction. */
#define LCDC_OVR1CFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_OVR1CFG0) Hardware Rotation Optimization Disable */
#define LCDC_OVR1CFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_OVR1CFG0) Hardware Rotation Lock Disable */
/* -------- LCDC_OVR1CFG1 : (LCDC Offset: 0x00000170) Overlay 1 Configuration 1 Register -------- */
#define LCDC_OVR1CFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table Enable */
#define LCDC_OVR1CFG1_RGBMODE_Pos 4
#define LCDC_OVR1CFG1_RGBMODE_Msk (0xfu << LCDC_OVR1CFG1_RGBMODE_Pos) /**< \brief (LCDC_OVR1CFG1) RGB Input Mode Selection */
#define   LCDC_OVR1CFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_OVR1CFG1) 12 bpp RGB 444 */
#define   LCDC_OVR1CFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp ARGB 4444 */
#define   LCDC_OVR1CFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp RGBA 4444 */
#define   LCDC_OVR1CFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp RGB 565 */
#define   LCDC_OVR1CFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp TRGB 1555 */
#define   LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_OVR1CFG1) 18 bpp RGB 666 */
#define   LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_OVR1CFG1) 18 bpp RGB 666 PACKED */
#define   LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_OVR1CFG1) 19 bpp TRGB 1666 */
#define   LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_OVR1CFG1) 19 bpp TRGB 1666 PACKED */
#define   LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_OVR1CFG1) 24 bpp RGB 888 */
#define   LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_OVR1CFG1) 24 bpp RGB 888 PACKED */
#define   LCDC_OVR1CFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_OVR1CFG1) 25 bpp TRGB 1888 */
#define   LCDC_OVR1CFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_OVR1CFG1) 32 bpp ARGB 8888 */
#define   LCDC_OVR1CFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_OVR1CFG1) 32 bpp RGBA 8888 */
#define LCDC_OVR1CFG1_CLUTMODE_Pos 8
#define LCDC_OVR1CFG1_CLUTMODE_Msk (0x3u << LCDC_OVR1CFG1_CLUTMODE_Pos) /**< \brief (LCDC_OVR1CFG1) Color Lookup table input mode selection */
#define   LCDC_OVR1CFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_OVR1CFG1) color lookup table mode set to 1 bit per pixel */
#define   LCDC_OVR1CFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_OVR1CFG1) color lookup table mode set to 2 bits per pixel */
#define   LCDC_OVR1CFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_OVR1CFG1) color lookup table mode set to 4 bits per pixel */
#define   LCDC_OVR1CFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_OVR1CFG1) color lookup table mode set to 8 bits per pixel */
/* -------- LCDC_OVR1CFG2 : (LCDC Offset: 0x00000174) Overlay 1 Configuration 2 Register -------- */
#define LCDC_OVR1CFG2_XPOS_Pos 0
#define LCDC_OVR1CFG2_XPOS_Msk (0x7ffu << LCDC_OVR1CFG2_XPOS_Pos) /**< \brief (LCDC_OVR1CFG2) Horizontal Window Position */
#define LCDC_OVR1CFG2_XPOS(value) ((LCDC_OVR1CFG2_XPOS_Msk & ((value) << LCDC_OVR1CFG2_XPOS_Pos)))
#define LCDC_OVR1CFG2_YPOS_Pos 16
#define LCDC_OVR1CFG2_YPOS_Msk (0x7ffu << LCDC_OVR1CFG2_YPOS_Pos) /**< \brief (LCDC_OVR1CFG2) Vertical Window Position */
#define LCDC_OVR1CFG2_YPOS(value) ((LCDC_OVR1CFG2_YPOS_Msk & ((value) << LCDC_OVR1CFG2_YPOS_Pos)))
/* -------- LCDC_OVR1CFG3 : (LCDC Offset: 0x00000178) Overlay 1 Configuration 3 Register -------- */
#define LCDC_OVR1CFG3_XSIZE_Pos 0
#define LCDC_OVR1CFG3_XSIZE_Msk (0x7ffu << LCDC_OVR1CFG3_XSIZE_Pos) /**< \brief (LCDC_OVR1CFG3) Horizontal Window Size */
#define LCDC_OVR1CFG3_XSIZE(value) ((LCDC_OVR1CFG3_XSIZE_Msk & ((value) << LCDC_OVR1CFG3_XSIZE_Pos)))
#define LCDC_OVR1CFG3_YSIZE_Pos 16
#define LCDC_OVR1CFG3_YSIZE_Msk (0x7ffu << LCDC_OVR1CFG3_YSIZE_Pos) /**< \brief (LCDC_OVR1CFG3) Vertical Window Size */
#define LCDC_OVR1CFG3_YSIZE(value) ((LCDC_OVR1CFG3_YSIZE_Msk & ((value) << LCDC_OVR1CFG3_YSIZE_Pos)))
/* -------- LCDC_OVR1CFG4 : (LCDC Offset: 0x0000017C) Overlay 1 Configuration 4 Register -------- */
#define LCDC_OVR1CFG4_XSTRIDE_Pos 0
#define LCDC_OVR1CFG4_XSTRIDE_Msk (0xffffffffu << LCDC_OVR1CFG4_XSTRIDE_Pos) /**< \brief (LCDC_OVR1CFG4) Horizontal Stride */
#define LCDC_OVR1CFG4_XSTRIDE(value) ((LCDC_OVR1CFG4_XSTRIDE_Msk & ((value) << LCDC_OVR1CFG4_XSTRIDE_Pos)))
/* -------- LCDC_OVR1CFG5 : (LCDC Offset: 0x00000180) Overlay 1 Configuration 5 Register -------- */
#define LCDC_OVR1CFG5_PSTRIDE_Pos 0
#define LCDC_OVR1CFG5_PSTRIDE_Msk (0xffffffffu << LCDC_OVR1CFG5_PSTRIDE_Pos) /**< \brief (LCDC_OVR1CFG5) Pixel Stride */
#define LCDC_OVR1CFG5_PSTRIDE(value) ((LCDC_OVR1CFG5_PSTRIDE_Msk & ((value) << LCDC_OVR1CFG5_PSTRIDE_Pos)))
/* -------- LCDC_OVR1CFG6 : (LCDC Offset: 0x00000184) Overlay 1 Configuration 6 Register -------- */
#define LCDC_OVR1CFG6_BDEF_Pos 0
#define LCDC_OVR1CFG6_BDEF_Msk (0xffu << LCDC_OVR1CFG6_BDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Blue Default */
#define LCDC_OVR1CFG6_BDEF(value) ((LCDC_OVR1CFG6_BDEF_Msk & ((value) << LCDC_OVR1CFG6_BDEF_Pos)))
#define LCDC_OVR1CFG6_GDEF_Pos 8
#define LCDC_OVR1CFG6_GDEF_Msk (0xffu << LCDC_OVR1CFG6_GDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Green Default */
#define LCDC_OVR1CFG6_GDEF(value) ((LCDC_OVR1CFG6_GDEF_Msk & ((value) << LCDC_OVR1CFG6_GDEF_Pos)))
#define LCDC_OVR1CFG6_RDEF_Pos 16
#define LCDC_OVR1CFG6_RDEF_Msk (0xffu << LCDC_OVR1CFG6_RDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Red Default */
#define LCDC_OVR1CFG6_RDEF(value) ((LCDC_OVR1CFG6_RDEF_Msk & ((value) << LCDC_OVR1CFG6_RDEF_Pos)))
/* -------- LCDC_OVR1CFG7 : (LCDC Offset: 0x00000188) Overlay 1 Configuration 7 Register -------- */
#define LCDC_OVR1CFG7_BKEY_Pos 0
#define LCDC_OVR1CFG7_BKEY_Msk (0xffu << LCDC_OVR1CFG7_BKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Blue Color Component Chroma Key */
#define LCDC_OVR1CFG7_BKEY(value) ((LCDC_OVR1CFG7_BKEY_Msk & ((value) << LCDC_OVR1CFG7_BKEY_Pos)))
#define LCDC_OVR1CFG7_GKEY_Pos 8
#define LCDC_OVR1CFG7_GKEY_Msk (0xffu << LCDC_OVR1CFG7_GKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Green Color Component Chroma Key */
#define LCDC_OVR1CFG7_GKEY(value) ((LCDC_OVR1CFG7_GKEY_Msk & ((value) << LCDC_OVR1CFG7_GKEY_Pos)))
#define LCDC_OVR1CFG7_RKEY_Pos 16
#define LCDC_OVR1CFG7_RKEY_Msk (0xffu << LCDC_OVR1CFG7_RKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Red Color Component Chroma Key */
#define LCDC_OVR1CFG7_RKEY(value) ((LCDC_OVR1CFG7_RKEY_Msk & ((value) << LCDC_OVR1CFG7_RKEY_Pos)))
/* -------- LCDC_OVR1CFG8 : (LCDC Offset: 0x0000018C) Overlay 1 Configuration 8Register -------- */
#define LCDC_OVR1CFG8_BMASK_Pos 0
#define LCDC_OVR1CFG8_BMASK_Msk (0xffu << LCDC_OVR1CFG8_BMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Blue Color Component Chroma Key Mask */
#define LCDC_OVR1CFG8_BMASK(value) ((LCDC_OVR1CFG8_BMASK_Msk & ((value) << LCDC_OVR1CFG8_BMASK_Pos)))
#define LCDC_OVR1CFG8_GMASK_Pos 8
#define LCDC_OVR1CFG8_GMASK_Msk (0xffu << LCDC_OVR1CFG8_GMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Green Color Component Chroma Key Mask */
#define LCDC_OVR1CFG8_GMASK(value) ((LCDC_OVR1CFG8_GMASK_Msk & ((value) << LCDC_OVR1CFG8_GMASK_Pos)))
#define LCDC_OVR1CFG8_RMASK_Pos 16
#define LCDC_OVR1CFG8_RMASK_Msk (0xffu << LCDC_OVR1CFG8_RMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Red Color Component Chroma Key Mask */
#define LCDC_OVR1CFG8_RMASK(value) ((LCDC_OVR1CFG8_RMASK_Msk & ((value) << LCDC_OVR1CFG8_RMASK_Pos)))
/* -------- LCDC_OVR1CFG9 : (LCDC Offset: 0x00000190) Overlay 1 Configuration 9 Register -------- */
#define LCDC_OVR1CFG9_CRKEY (0x1u << 0) /**< \brief (LCDC_OVR1CFG9) Blender Chroma Key Enable */
#define LCDC_OVR1CFG9_INV (0x1u << 1) /**< \brief (LCDC_OVR1CFG9) Blender Inverted Blender Output Enable */
#define LCDC_OVR1CFG9_ITER2BL (0x1u << 2) /**< \brief (LCDC_OVR1CFG9) Blender Iterated Color Enable */
#define LCDC_OVR1CFG9_ITER (0x1u << 3) /**< \brief (LCDC_OVR1CFG9) Blender Use Iterated Color */
#define LCDC_OVR1CFG9_REVALPHA (0x1u << 4) /**< \brief (LCDC_OVR1CFG9) Blender Reverse Alpha */
#define LCDC_OVR1CFG9_GAEN (0x1u << 5) /**< \brief (LCDC_OVR1CFG9) Blender Global Alpha Enable */
#define LCDC_OVR1CFG9_LAEN (0x1u << 6) /**< \brief (LCDC_OVR1CFG9) Blender Local Alpha Enable */
#define LCDC_OVR1CFG9_OVR (0x1u << 7) /**< \brief (LCDC_OVR1CFG9) Blender Overlay Layer Enable */
#define LCDC_OVR1CFG9_DMA (0x1u << 8) /**< \brief (LCDC_OVR1CFG9) Blender DMA Layer Enable */
#define LCDC_OVR1CFG9_REP (0x1u << 9) /**< \brief (LCDC_OVR1CFG9) Use Replication logic to expand RGB color to 24 bits */
#define LCDC_OVR1CFG9_DSTKEY (0x1u << 10) /**< \brief (LCDC_OVR1CFG9) Destination Chroma Keying */
#define LCDC_OVR1CFG9_GA_Pos 16
#define LCDC_OVR1CFG9_GA_Msk (0xffu << LCDC_OVR1CFG9_GA_Pos) /**< \brief (LCDC_OVR1CFG9) Blender Global Alpha */
#define LCDC_OVR1CFG9_GA(value) ((LCDC_OVR1CFG9_GA_Msk & ((value) << LCDC_OVR1CFG9_GA_Pos)))
/* -------- LCDC_OVR2CHER : (LCDC Offset: 0x00000240) Overlay 2 Channel Enable Register -------- */
#define LCDC_OVR2CHER_CHEN (0x1u << 0) /**< \brief (LCDC_OVR2CHER) Channel Enable Register */
#define LCDC_OVR2CHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_OVR2CHER) Update Overlay Attributes Enable Register */
#define LCDC_OVR2CHER_A2QEN (0x1u << 2) /**< \brief (LCDC_OVR2CHER) Add Head Pointer Enable Register */
/* -------- LCDC_OVR2CHDR : (LCDC Offset: 0x00000244) Overlay 2 Channel Disable Register -------- */
#define LCDC_OVR2CHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_OVR2CHDR) Channel Disable Register */
#define LCDC_OVR2CHDR_CHRST (0x1u << 8) /**< \brief (LCDC_OVR2CHDR) Channel Reset Register */
/* -------- LCDC_OVR2CHSR : (LCDC Offset: 0x00000248) Overlay 2 Channel Status Register -------- */
#define LCDC_OVR2CHSR_CHSR (0x1u << 0) /**< \brief (LCDC_OVR2CHSR) Channel Status Register */
#define LCDC_OVR2CHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_OVR2CHSR) Update Overlay Attributes In Progress */
#define LCDC_OVR2CHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_OVR2CHSR) Add To Queue Pending Register */
/* -------- LCDC_OVR2IER : (LCDC Offset: 0x0000024C) Overlay 2 Interrupt Enable Register -------- */
#define LCDC_OVR2IER_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IER) End of DMA Transfer Interrupt Enable Register */
#define LCDC_OVR2IER_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IER) Descriptor Loaded Interrupt Enable Register */
#define LCDC_OVR2IER_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IER) Head Descriptor Loaded Interrupt Enable Register */
#define LCDC_OVR2IER_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IER) End of List Interrupt Enable Register */
#define LCDC_OVR2IER_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IER) Overflow Interrupt Enable Register */
/* -------- LCDC_OVR2IDR : (LCDC Offset: 0x00000250) Overlay 2 Interrupt Disable Register -------- */
#define LCDC_OVR2IDR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IDR) End of DMA Transfer Interrupt Disable Register */
#define LCDC_OVR2IDR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IDR) Descriptor Loaded Interrupt Disable Register */
#define LCDC_OVR2IDR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IDR) Head Descriptor Loaded Interrupt Disable Register */
#define LCDC_OVR2IDR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IDR) End of List Interrupt Disable Register */
#define LCDC_OVR2IDR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IDR) Overflow Interrupt Disable Register */
/* -------- LCDC_OVR2IMR : (LCDC Offset: 0x00000254) Overlay 2 Interrupt Mask Register -------- */
#define LCDC_OVR2IMR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IMR) End of DMA Transfer Interrupt Mask Register */
#define LCDC_OVR2IMR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IMR) Descriptor Loaded Interrupt Mask Register */
#define LCDC_OVR2IMR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IMR) Head Descriptor Loaded Interrupt Mask Register */
#define LCDC_OVR2IMR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IMR) End of List Interrupt Mask Register */
#define LCDC_OVR2IMR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IMR) Overflow Interrupt Mask Register */
/* -------- LCDC_OVR2ISR : (LCDC Offset: 0x00000258) Overlay 2 Interrupt status Register -------- */
#define LCDC_OVR2ISR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2ISR) End of DMA Transfer */
#define LCDC_OVR2ISR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2ISR) DMA Descriptor Loaded */
#define LCDC_OVR2ISR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2ISR) Head Descriptor Loaded Interrupt Disable Register */
#define LCDC_OVR2ISR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2ISR) End Of List Interrupt Disable Register */
#define LCDC_OVR2ISR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2ISR) Overflow Detected */
/* -------- LCDC_OVR2HEAD : (LCDC Offset: 0x0000025C) Overlay 2 DMA Head Register -------- */
#define LCDC_OVR2HEAD_HEAD_Pos 2
#define LCDC_OVR2HEAD_HEAD_Msk (0x3fffffffu << LCDC_OVR2HEAD_HEAD_Pos) /**< \brief (LCDC_OVR2HEAD) DMA Head Pointer */
#define LCDC_OVR2HEAD_HEAD(value) ((LCDC_OVR2HEAD_HEAD_Msk & ((value) << LCDC_OVR2HEAD_HEAD_Pos)))
/* -------- LCDC_OVR2ADDR : (LCDC Offset: 0x00000260) Overlay 2 DMA Address Register -------- */
#define LCDC_OVR2ADDR_ADDR_Pos 0
#define LCDC_OVR2ADDR_ADDR_Msk (0xffffffffu << LCDC_OVR2ADDR_ADDR_Pos) /**< \brief (LCDC_OVR2ADDR) DMA Transfer Overlay 2 Address */
#define LCDC_OVR2ADDR_ADDR(value) ((LCDC_OVR2ADDR_ADDR_Msk & ((value) << LCDC_OVR2ADDR_ADDR_Pos)))
/* -------- LCDC_OVR2CTRL : (LCDC Offset: 0x00000264) Overlay 2 DMA Control Register -------- */
#define LCDC_OVR2CTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_OVR2CTRL) Transfer Descriptor Fetch Enable */
#define LCDC_OVR2CTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_OVR2CTRL) Lookup Table Fetch Enable */
#define LCDC_OVR2CTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_OVR2CTRL) End of DMA Transfer Interrupt Enable */
#define LCDC_OVR2CTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_OVR2CTRL) Descriptor Loaded Interrupt Enable */
#define LCDC_OVR2CTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_OVR2CTRL) Add Head Descriptor to Queue Interrupt Enable */
#define LCDC_OVR2CTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_OVR2CTRL) End of List Interrupt Enable */
/* -------- LCDC_OVR2NEXT : (LCDC Offset: 0x00000268) Overlay 2 DMA Next Register -------- */
#define LCDC_OVR2NEXT_NEXT_Pos 0
#define LCDC_OVR2NEXT_NEXT_Msk (0xffffffffu << LCDC_OVR2NEXT_NEXT_Pos) /**< \brief (LCDC_OVR2NEXT) DMA Descriptor Next Address */
#define LCDC_OVR2NEXT_NEXT(value) ((LCDC_OVR2NEXT_NEXT_Msk & ((value) << LCDC_OVR2NEXT_NEXT_Pos)))
/* -------- LCDC_OVR2CFG0 : (LCDC Offset: 0x0000026C) Overlay 2 Configuration 0 Register -------- */
#define LCDC_OVR2CFG0_BLEN_Pos 4
#define LCDC_OVR2CFG0_BLEN_Msk (0x3u << LCDC_OVR2CFG0_BLEN_Pos) /**< \brief (LCDC_OVR2CFG0) AHB Burst Length */
#define   LCDC_OVR2CFG0_BLEN_AHB_SINGLE (0x0u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_OVR2CFG0_BLEN_AHB_INCR4 (0x1u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_OVR2CFG0_BLEN_AHB_INCR8 (0x2u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_OVR2CFG0_BLEN_AHB_INCR16 (0x3u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define LCDC_OVR2CFG0_DLBO (0x1u << 8) /**< \brief (LCDC_OVR2CFG0) Defined Length Burst Only For Channel Bus Transaction. */
#define LCDC_OVR2CFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_OVR2CFG0) Hardware Rotation Optimization Disable */
#define LCDC_OVR2CFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_OVR2CFG0) Hardware Rotation Lock Disable */
/* -------- LCDC_OVR2CFG1 : (LCDC Offset: 0x00000270) Overlay 2 Configuration 1 Register -------- */
#define LCDC_OVR2CFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table Enable */
#define LCDC_OVR2CFG1_RGBMODE_Pos 4
#define LCDC_OVR2CFG1_RGBMODE_Msk (0xfu << LCDC_OVR2CFG1_RGBMODE_Pos) /**< \brief (LCDC_OVR2CFG1) RGB Input Mode Selection */
#define   LCDC_OVR2CFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_OVR2CFG1) 12 bpp RGB 444 */
#define   LCDC_OVR2CFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp ARGB 4444 */
#define   LCDC_OVR2CFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp RGBA 4444 */
#define   LCDC_OVR2CFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp RGB 565 */
#define   LCDC_OVR2CFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp TRGB 1555 */
#define   LCDC_OVR2CFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_OVR2CFG1) 18 bpp RGB 666 */
#define   LCDC_OVR2CFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_OVR2CFG1) 18 bpp RGB 666 PACKED */
#define   LCDC_OVR2CFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_OVR2CFG1) 19 bpp TRGB 1666 */
#define   LCDC_OVR2CFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_OVR2CFG1) 19 bpp TRGB 1666 PACKED */
#define   LCDC_OVR2CFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_OVR2CFG1) 24 bpp RGB 888 */
#define   LCDC_OVR2CFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_OVR2CFG1) 24 bpp RGB 888 PACKED */
#define   LCDC_OVR2CFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_OVR2CFG1) 25 bpp TRGB 1888 */
#define   LCDC_OVR2CFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_OVR2CFG1) 32 bpp ARGB 8888 */
#define   LCDC_OVR2CFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_OVR2CFG1) 32 bpp RGBA 8888 */
#define LCDC_OVR2CFG1_CLUTMODE_Pos 8
#define LCDC_OVR2CFG1_CLUTMODE_Msk (0x3u << LCDC_OVR2CFG1_CLUTMODE_Pos) /**< \brief (LCDC_OVR2CFG1) Color Lookup table input mode selection */
#define   LCDC_OVR2CFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_OVR2CFG1) color lookup table mode set to 1 bit per pixel */
#define   LCDC_OVR2CFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_OVR2CFG1) color lookup table mode set to 2 bits per pixel */
#define   LCDC_OVR2CFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_OVR2CFG1) color lookup table mode set to 4 bits per pixel */
#define   LCDC_OVR2CFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_OVR2CFG1) color lookup table mode set to 8 bits per pixel */
/* -------- LCDC_OVR2CFG2 : (LCDC Offset: 0x00000274) Overlay 2 Configuration 2 Register -------- */
#define LCDC_OVR2CFG2_XPOS_Pos 0
#define LCDC_OVR2CFG2_XPOS_Msk (0x7ffu << LCDC_OVR2CFG2_XPOS_Pos) /**< \brief (LCDC_OVR2CFG2) Horizontal Window Position */
#define LCDC_OVR2CFG2_XPOS(value) ((LCDC_OVR2CFG2_XPOS_Msk & ((value) << LCDC_OVR2CFG2_XPOS_Pos)))
#define LCDC_OVR2CFG2_YPOS_Pos 16
#define LCDC_OVR2CFG2_YPOS_Msk (0x7ffu << LCDC_OVR2CFG2_YPOS_Pos) /**< \brief (LCDC_OVR2CFG2) Vertical Window Position */
#define LCDC_OVR2CFG2_YPOS(value) ((LCDC_OVR2CFG2_YPOS_Msk & ((value) << LCDC_OVR2CFG2_YPOS_Pos)))
/* -------- LCDC_OVR2CFG3 : (LCDC Offset: 0x00000278) Overlay 2 Configuration 3 Register -------- */
#define LCDC_OVR2CFG3_XSIZE_Pos 0
#define LCDC_OVR2CFG3_XSIZE_Msk (0x7ffu << LCDC_OVR2CFG3_XSIZE_Pos) /**< \brief (LCDC_OVR2CFG3) Horizontal Window Size */
#define LCDC_OVR2CFG3_XSIZE(value) ((LCDC_OVR2CFG3_XSIZE_Msk & ((value) << LCDC_OVR2CFG3_XSIZE_Pos)))
#define LCDC_OVR2CFG3_YSIZE_Pos 16
#define LCDC_OVR2CFG3_YSIZE_Msk (0x7ffu << LCDC_OVR2CFG3_YSIZE_Pos) /**< \brief (LCDC_OVR2CFG3) Vertical Window Size */
#define LCDC_OVR2CFG3_YSIZE(value) ((LCDC_OVR2CFG3_YSIZE_Msk & ((value) << LCDC_OVR2CFG3_YSIZE_Pos)))
/* -------- LCDC_OVR2CFG4 : (LCDC Offset: 0x0000027C) Overlay 2 Configuration 4 Register -------- */
#define LCDC_OVR2CFG4_XSTRIDE_Pos 0
#define LCDC_OVR2CFG4_XSTRIDE_Msk (0xffffffffu << LCDC_OVR2CFG4_XSTRIDE_Pos) /**< \brief (LCDC_OVR2CFG4) Horizontal Stride */
#define LCDC_OVR2CFG4_XSTRIDE(value) ((LCDC_OVR2CFG4_XSTRIDE_Msk & ((value) << LCDC_OVR2CFG4_XSTRIDE_Pos)))
/* -------- LCDC_OVR2CFG5 : (LCDC Offset: 0x00000280) Overlay 2 Configuration 5 Register -------- */
#define LCDC_OVR2CFG5_PSTRIDE_Pos 0
#define LCDC_OVR2CFG5_PSTRIDE_Msk (0xffffffffu << LCDC_OVR2CFG5_PSTRIDE_Pos) /**< \brief (LCDC_OVR2CFG5) Pixel Stride */
#define LCDC_OVR2CFG5_PSTRIDE(value) ((LCDC_OVR2CFG5_PSTRIDE_Msk & ((value) << LCDC_OVR2CFG5_PSTRIDE_Pos)))
/* -------- LCDC_OVR2CFG6 : (LCDC Offset: 0x00000284) Overlay 2 Configuration 6 Register -------- */
#define LCDC_OVR2CFG6_BDEF_Pos 0
#define LCDC_OVR2CFG6_BDEF_Msk (0xffu << LCDC_OVR2CFG6_BDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Blue Default */
#define LCDC_OVR2CFG6_BDEF(value) ((LCDC_OVR2CFG6_BDEF_Msk & ((value) << LCDC_OVR2CFG6_BDEF_Pos)))
#define LCDC_OVR2CFG6_GDEF_Pos 8
#define LCDC_OVR2CFG6_GDEF_Msk (0xffu << LCDC_OVR2CFG6_GDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Green Default */
#define LCDC_OVR2CFG6_GDEF(value) ((LCDC_OVR2CFG6_GDEF_Msk & ((value) << LCDC_OVR2CFG6_GDEF_Pos)))
#define LCDC_OVR2CFG6_RDEF_Pos 16
#define LCDC_OVR2CFG6_RDEF_Msk (0xffu << LCDC_OVR2CFG6_RDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Red Default */
#define LCDC_OVR2CFG6_RDEF(value) ((LCDC_OVR2CFG6_RDEF_Msk & ((value) << LCDC_OVR2CFG6_RDEF_Pos)))
/* -------- LCDC_OVR2CFG7 : (LCDC Offset: 0x00000288) Overlay 2 Configuration 7 Register -------- */
#define LCDC_OVR2CFG7_BKEY_Pos 0
#define LCDC_OVR2CFG7_BKEY_Msk (0xffu << LCDC_OVR2CFG7_BKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Blue Color Component Chroma Key */
#define LCDC_OVR2CFG7_BKEY(value) ((LCDC_OVR2CFG7_BKEY_Msk & ((value) << LCDC_OVR2CFG7_BKEY_Pos)))
#define LCDC_OVR2CFG7_GKEY_Pos 8
#define LCDC_OVR2CFG7_GKEY_Msk (0xffu << LCDC_OVR2CFG7_GKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Green Color Component Chroma Key */
#define LCDC_OVR2CFG7_GKEY(value) ((LCDC_OVR2CFG7_GKEY_Msk & ((value) << LCDC_OVR2CFG7_GKEY_Pos)))
#define LCDC_OVR2CFG7_RKEY_Pos 16
#define LCDC_OVR2CFG7_RKEY_Msk (0xffu << LCDC_OVR2CFG7_RKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Red Color Component Chroma Key */
#define LCDC_OVR2CFG7_RKEY(value) ((LCDC_OVR2CFG7_RKEY_Msk & ((value) << LCDC_OVR2CFG7_RKEY_Pos)))
/* -------- LCDC_OVR2CFG8 : (LCDC Offset: 0x0000028C) Overlay 2 Configuration 8 Register -------- */
#define LCDC_OVR2CFG8_BMASK_Pos 0
#define LCDC_OVR2CFG8_BMASK_Msk (0xffu << LCDC_OVR2CFG8_BMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Blue Color Component Chroma Key Mask */
#define LCDC_OVR2CFG8_BMASK(value) ((LCDC_OVR2CFG8_BMASK_Msk & ((value) << LCDC_OVR2CFG8_BMASK_Pos)))
#define LCDC_OVR2CFG8_GMASK_Pos 8
#define LCDC_OVR2CFG8_GMASK_Msk (0xffu << LCDC_OVR2CFG8_GMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Green Color Component Chroma Key Mask */
#define LCDC_OVR2CFG8_GMASK(value) ((LCDC_OVR2CFG8_GMASK_Msk & ((value) << LCDC_OVR2CFG8_GMASK_Pos)))
#define LCDC_OVR2CFG8_RMASK_Pos 16
#define LCDC_OVR2CFG8_RMASK_Msk (0xffu << LCDC_OVR2CFG8_RMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Red Color Component Chroma Key Mask */
#define LCDC_OVR2CFG8_RMASK(value) ((LCDC_OVR2CFG8_RMASK_Msk & ((value) << LCDC_OVR2CFG8_RMASK_Pos)))
/* -------- LCDC_OVR2CFG9 : (LCDC Offset: 0x00000290) Overlay 2 Configuration 9 Register -------- */
#define LCDC_OVR2CFG9_CRKEY (0x1u << 0) /**< \brief (LCDC_OVR2CFG9) Blender Chroma Key Enable */
#define LCDC_OVR2CFG9_INV (0x1u << 1) /**< \brief (LCDC_OVR2CFG9) Blender Inverted Blender Output Enable */
#define LCDC_OVR2CFG9_ITER2BL (0x1u << 2) /**< \brief (LCDC_OVR2CFG9) Blender Iterated Color Enable */
#define LCDC_OVR2CFG9_ITER (0x1u << 3) /**< \brief (LCDC_OVR2CFG9) Blender Use Iterated Color */
#define LCDC_OVR2CFG9_REVALPHA (0x1u << 4) /**< \brief (LCDC_OVR2CFG9) Blender Reverse Alpha */
#define LCDC_OVR2CFG9_GAEN (0x1u << 5) /**< \brief (LCDC_OVR2CFG9) Blender Global Alpha Enable */
#define LCDC_OVR2CFG9_LAEN (0x1u << 6) /**< \brief (LCDC_OVR2CFG9) Blender Local Alpha Enable */
#define LCDC_OVR2CFG9_OVR (0x1u << 7) /**< \brief (LCDC_OVR2CFG9) Blender Overlay Layer Enable */
#define LCDC_OVR2CFG9_DMA (0x1u << 8) /**< \brief (LCDC_OVR2CFG9) Blender DMA Layer Enable */
#define LCDC_OVR2CFG9_REP (0x1u << 9) /**< \brief (LCDC_OVR2CFG9) Use Replication logic to expand RGB color to 24 bits */
#define LCDC_OVR2CFG9_DSTKEY (0x1u << 10) /**< \brief (LCDC_OVR2CFG9) Destination Chroma Keying */
#define LCDC_OVR2CFG9_GA_Pos 16
#define LCDC_OVR2CFG9_GA_Msk (0xffu << LCDC_OVR2CFG9_GA_Pos) /**< \brief (LCDC_OVR2CFG9) Blender Global Alpha */
#define LCDC_OVR2CFG9_GA(value) ((LCDC_OVR2CFG9_GA_Msk & ((value) << LCDC_OVR2CFG9_GA_Pos)))
/* -------- LCDC_HEOCHER : (LCDC Offset: 0x00000340) High-End Overlay Channel Enable Register -------- */
#define LCDC_HEOCHER_CHEN (0x1u << 0) /**< \brief (LCDC_HEOCHER) Channel Enable Register */
#define LCDC_HEOCHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_HEOCHER) Update Overlay Attributes Enable Register */
#define LCDC_HEOCHER_A2QEN (0x1u << 2) /**< \brief (LCDC_HEOCHER) Add Head Pointer Enable Register */
/* -------- LCDC_HEOCHDR : (LCDC Offset: 0x00000344) High-End Overlay Channel Disable Register -------- */
#define LCDC_HEOCHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_HEOCHDR) Channel Disable Register */
#define LCDC_HEOCHDR_CHRST (0x1u << 8) /**< \brief (LCDC_HEOCHDR) Channel Reset Register */
/* -------- LCDC_HEOCHSR : (LCDC Offset: 0x00000348) High-End Overlay Channel Status Register -------- */
#define LCDC_HEOCHSR_CHSR (0x1u << 0) /**< \brief (LCDC_HEOCHSR) Channel Status Register */
#define LCDC_HEOCHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_HEOCHSR) Update Overlay Attributes In Progress */
#define LCDC_HEOCHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_HEOCHSR) Add To Queue Pending Register */
/* -------- LCDC_HEOIER : (LCDC Offset: 0x0000034C) High-End Overlay Interrupt Enable Register -------- */
#define LCDC_HEOIER_DMA (0x1u << 2) /**< \brief (LCDC_HEOIER) End of DMA Transfer Interrupt Enable Register */
#define LCDC_HEOIER_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIER) Descriptor Loaded Interrupt Enable Register */
#define LCDC_HEOIER_ADD (0x1u << 4) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded Interrupt Enable Register */
#define LCDC_HEOIER_DONE (0x1u << 5) /**< \brief (LCDC_HEOIER) End of List Interrupt Enable Register */
#define LCDC_HEOIER_OVR (0x1u << 6) /**< \brief (LCDC_HEOIER) Overflow Interrupt Enable Register */
#define LCDC_HEOIER_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIER) End of DMA Transfer for U or UV Chrominance Interrupt Enable Register */
#define LCDC_HEOIER_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIER) Descriptor Loaded for U or UV Chrominance Interrupt Enable Register */
#define LCDC_HEOIER_UADD (0x1u << 12) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded for U or UV Chrominance Interrupt Enable Register */
#define LCDC_HEOIER_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIER) End of List for U or UV Chrominance Interrupt Enable Register */
#define LCDC_HEOIER_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIER) Overflow for U or UV Chrominance Interrupt Enable Register */
#define LCDC_HEOIER_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIER) End of DMA for V Chrominance Transfer Interrupt Enable Register */
#define LCDC_HEOIER_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIER) Descriptor Loaded for V Chrominance Interrupt Enable Register */
#define LCDC_HEOIER_VADD (0x1u << 20) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded for V Chrominance Interrupt Enable Register */
#define LCDC_HEOIER_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIER) End of List for V Chrominance Interrupt Enable Register */
#define LCDC_HEOIER_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIER) Overflow for V Chrominance Interrupt Enable Register */
/* -------- LCDC_HEOIDR : (LCDC Offset: 0x00000350) High-End Overlay Interrupt Disable Register -------- */
#define LCDC_HEOIDR_DMA (0x1u << 2) /**< \brief (LCDC_HEOIDR) End of DMA Transfer Interrupt Disable Register */
#define LCDC_HEOIDR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIDR) Descriptor Loaded Interrupt Disable Register */
#define LCDC_HEOIDR_ADD (0x1u << 4) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded Interrupt Disable Register */
#define LCDC_HEOIDR_DONE (0x1u << 5) /**< \brief (LCDC_HEOIDR) End of List Interrupt Disable Register */
#define LCDC_HEOIDR_OVR (0x1u << 6) /**< \brief (LCDC_HEOIDR) Overflow Interrupt Disable Register */
#define LCDC_HEOIDR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIDR) End of DMA Transfer for U or UV Chrominance Component Interrupt Disable Register */
#define LCDC_HEOIDR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIDR) Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register */
#define LCDC_HEOIDR_UADD (0x1u << 12) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register */
#define LCDC_HEOIDR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIDR) End of List Interrupt for U or UV Chrominance Component Disable Register */
#define LCDC_HEOIDR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIDR) Overflow Interrupt for U or UV Chrominance Component Disable Register */
#define LCDC_HEOIDR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIDR) End of DMA Transfer for V Chrominance Component Interrupt Disable Register */
#define LCDC_HEOIDR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIDR) Descriptor Loaded for V Chrominance Component Interrupt Disable Register */
#define LCDC_HEOIDR_VADD (0x1u << 20) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded for V Chrominance Component Interrupt Disable Register */
#define LCDC_HEOIDR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIDR) End of List for V Chrominance Component Interrupt Disable Register */
#define LCDC_HEOIDR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIDR) Overflow for V Chrominance Component Interrupt Disable Register */
/* -------- LCDC_HEOIMR : (LCDC Offset: 0x00000354) High-End Overlay Interrupt Mask Register -------- */
#define LCDC_HEOIMR_DMA (0x1u << 2) /**< \brief (LCDC_HEOIMR) End of DMA Transfer Interrupt Mask Register */
#define LCDC_HEOIMR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIMR) Descriptor Loaded Interrupt Mask Register */
#define LCDC_HEOIMR_ADD (0x1u << 4) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded Interrupt Mask Register */
#define LCDC_HEOIMR_DONE (0x1u << 5) /**< \brief (LCDC_HEOIMR) End of List Interrupt Mask Register */
#define LCDC_HEOIMR_OVR (0x1u << 6) /**< \brief (LCDC_HEOIMR) Overflow Interrupt Mask Register */
#define LCDC_HEOIMR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIMR) End of DMA Transfer for U or UV Chrominance Component Interrupt Mask Register */
#define LCDC_HEOIMR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIMR) Descriptor Loaded for U or UV Chrominance Component Interrupt Mask Register */
#define LCDC_HEOIMR_UADD (0x1u << 12) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded for U or UV Chrominance Component Mask Register */
#define LCDC_HEOIMR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIMR) End of List for U or UV Chrominance Component Mask Register */
#define LCDC_HEOIMR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIMR) Overflow for U Chrominance Interrupt Mask Register */
#define LCDC_HEOIMR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIMR) End of DMA Transfer for V Chrominance Component Interrupt Mask Register */
#define LCDC_HEOIMR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIMR) Descriptor Loaded for V Chrominance Component Interrupt Mask Register */
#define LCDC_HEOIMR_VADD (0x1u << 20) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded for V Chrominance Component Mask Register */
#define LCDC_HEOIMR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIMR) End of List for V Chrominance Component Mask Register */
#define LCDC_HEOIMR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIMR) Overflow for V Chrominance Interrupt Mask Register */
/* -------- LCDC_HEOISR : (LCDC Offset: 0x00000358) High-End Overlay Interrupt Status Register -------- */
#define LCDC_HEOISR_DMA (0x1u << 2) /**< \brief (LCDC_HEOISR) End of DMA Transfer */
#define LCDC_HEOISR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded */
#define LCDC_HEOISR_ADD (0x1u << 4) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded */
#define LCDC_HEOISR_DONE (0x1u << 5) /**< \brief (LCDC_HEOISR) End of List Detected */
#define LCDC_HEOISR_OVR (0x1u << 6) /**< \brief (LCDC_HEOISR) Overflow Detected */
#define LCDC_HEOISR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOISR) End of DMA Transfer for U component */
#define LCDC_HEOISR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded for U component */
#define LCDC_HEOISR_UADD (0x1u << 12) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded for U component */
#define LCDC_HEOISR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOISR) End of List Detected for U component */
#define LCDC_HEOISR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOISR) Overflow Detected for U component */
#define LCDC_HEOISR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOISR) End of DMA Transfer for V component */
#define LCDC_HEOISR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded for V component */
#define LCDC_HEOISR_VADD (0x1u << 20) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded for V component */
#define LCDC_HEOISR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOISR) End of List Detected for V component */
#define LCDC_HEOISR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOISR) Overflow Detected for V component */
/* -------- LCDC_HEOHEAD : (LCDC Offset: 0x0000035C) High-End Overlay DMA Head Register -------- */
#define LCDC_HEOHEAD_HEAD_Pos 2
#define LCDC_HEOHEAD_HEAD_Msk (0x3fffffffu << LCDC_HEOHEAD_HEAD_Pos) /**< \brief (LCDC_HEOHEAD) DMA Head Pointer */
#define LCDC_HEOHEAD_HEAD(value) ((LCDC_HEOHEAD_HEAD_Msk & ((value) << LCDC_HEOHEAD_HEAD_Pos)))
/* -------- LCDC_HEOADDR : (LCDC Offset: 0x00000360) High-End Overlay DMA Address Register -------- */
#define LCDC_HEOADDR_ADDR_Pos 0
#define LCDC_HEOADDR_ADDR_Msk (0xffffffffu << LCDC_HEOADDR_ADDR_Pos) /**< \brief (LCDC_HEOADDR) DMA Transfer start Address */
#define LCDC_HEOADDR_ADDR(value) ((LCDC_HEOADDR_ADDR_Msk & ((value) << LCDC_HEOADDR_ADDR_Pos)))
/* -------- LCDC_HEOCTRL : (LCDC Offset: 0x00000364) High-End Overlay DMA Control Register -------- */
#define LCDC_HEOCTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_HEOCTRL) Transfer Descriptor Fetch Enable */
#define LCDC_HEOCTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_HEOCTRL) Lookup Table Fetch Enable */
#define LCDC_HEOCTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_HEOCTRL) End of DMA Transfer Interrupt Enable */
#define LCDC_HEOCTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOCTRL) Descriptor Loaded Interrupt Enable */
#define LCDC_HEOCTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_HEOCTRL) Add Head Descriptor to Queue Interrupt Enable */
#define LCDC_HEOCTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_HEOCTRL) End of List Interrupt Enable */
/* -------- LCDC_HEONEXT : (LCDC Offset: 0x00000368) High-End Overlay DMA Next Register -------- */
#define LCDC_HEONEXT_NEXT_Pos 0
#define LCDC_HEONEXT_NEXT_Msk (0xffffffffu << LCDC_HEONEXT_NEXT_Pos) /**< \brief (LCDC_HEONEXT) DMA Descriptor Next Address */
#define LCDC_HEONEXT_NEXT(value) ((LCDC_HEONEXT_NEXT_Msk & ((value) << LCDC_HEONEXT_NEXT_Pos)))
/* -------- LCDC_HEOUHEAD : (LCDC Offset: 0x0000036C) High-End Overlay U DMA Head Register -------- */
#define LCDC_HEOUHEAD_UHEAD_Pos 0
#define LCDC_HEOUHEAD_UHEAD_Msk (0xffffffffu << LCDC_HEOUHEAD_UHEAD_Pos) /**< \brief (LCDC_HEOUHEAD) DMA Head Pointer */
#define LCDC_HEOUHEAD_UHEAD(value) ((LCDC_HEOUHEAD_UHEAD_Msk & ((value) << LCDC_HEOUHEAD_UHEAD_Pos)))
/* -------- LCDC_HEOUADDR : (LCDC Offset: 0x00000370) High-End Overlay U DMA Address Register -------- */
#define LCDC_HEOUADDR_UADDR_Pos 0
#define LCDC_HEOUADDR_UADDR_Msk (0xffffffffu << LCDC_HEOUADDR_UADDR_Pos) /**< \brief (LCDC_HEOUADDR) DMA Transfer Start Address for U or UV Chrominance */
#define LCDC_HEOUADDR_UADDR(value) ((LCDC_HEOUADDR_UADDR_Msk & ((value) << LCDC_HEOUADDR_UADDR_Pos)))
/* -------- LCDC_HEOUCTRL : (LCDC Offset: 0x00000374) High-End Overlay U DMA control Register -------- */
#define LCDC_HEOUCTRL_UDFETCH (0x1u << 0) /**< \brief (LCDC_HEOUCTRL) Transfer Descriptor Fetch Enable */
#define LCDC_HEOUCTRL_UDMAIEN (0x1u << 2) /**< \brief (LCDC_HEOUCTRL) End of DMA Transfer Interrupt Enable */
#define LCDC_HEOUCTRL_UDSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOUCTRL) Descriptor Loaded Interrupt Enable */
#define LCDC_HEOUCTRL_UADDIEN (0x1u << 4) /**< \brief (LCDC_HEOUCTRL) Add Head Descriptor to Queue Interrupt Enable */
#define LCDC_HEOUCTRL_UDONEIEN (0x1u << 5) /**< \brief (LCDC_HEOUCTRL) End of List Interrupt Enable */
/* -------- LCDC_HEOUNEXT : (LCDC Offset: 0x00000378) High-End Overlay U DMA Next Register -------- */
#define LCDC_HEOUNEXT_UNEXT_Pos 0
#define LCDC_HEOUNEXT_UNEXT_Msk (0xffffffffu << LCDC_HEOUNEXT_UNEXT_Pos) /**< \brief (LCDC_HEOUNEXT) DMA Descriptor Next Address */
#define LCDC_HEOUNEXT_UNEXT(value) ((LCDC_HEOUNEXT_UNEXT_Msk & ((value) << LCDC_HEOUNEXT_UNEXT_Pos)))
/* -------- LCDC_HEOVHEAD : (LCDC Offset: 0x0000037C) High-End Overlay V DMA Head Register -------- */
#define LCDC_HEOVHEAD_VHEAD_Pos 0
#define LCDC_HEOVHEAD_VHEAD_Msk (0xffffffffu << LCDC_HEOVHEAD_VHEAD_Pos) /**< \brief (LCDC_HEOVHEAD) DMA Head Pointer */
#define LCDC_HEOVHEAD_VHEAD(value) ((LCDC_HEOVHEAD_VHEAD_Msk & ((value) << LCDC_HEOVHEAD_VHEAD_Pos)))
/* -------- LCDC_HEOVADDR : (LCDC Offset: 0x00000380) High-End Overlay V DMA Address Register -------- */
#define LCDC_HEOVADDR_VADDR_Pos 0
#define LCDC_HEOVADDR_VADDR_Msk (0xffffffffu << LCDC_HEOVADDR_VADDR_Pos) /**< \brief (LCDC_HEOVADDR) DMA Transfer Start Address for V Chrominance */
#define LCDC_HEOVADDR_VADDR(value) ((LCDC_HEOVADDR_VADDR_Msk & ((value) << LCDC_HEOVADDR_VADDR_Pos)))
/* -------- LCDC_HEOVCTRL : (LCDC Offset: 0x00000384) High-End Overlay V DMA control Register -------- */
#define LCDC_HEOVCTRL_VDFETCH (0x1u << 0) /**< \brief (LCDC_HEOVCTRL) Transfer Descriptor Fetch Enable */
#define LCDC_HEOVCTRL_VDMAIEN (0x1u << 2) /**< \brief (LCDC_HEOVCTRL) End of DMA Transfer Interrupt Enable */
#define LCDC_HEOVCTRL_VDSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOVCTRL) Descriptor Loaded Interrupt Enable */
#define LCDC_HEOVCTRL_VADDIEN (0x1u << 4) /**< \brief (LCDC_HEOVCTRL) Add Head Descriptor to Queue Interrupt Enable */
#define LCDC_HEOVCTRL_VDONEIEN (0x1u << 5) /**< \brief (LCDC_HEOVCTRL) End of List Interrupt Enable */
/* -------- LCDC_HEOVNEXT : (LCDC Offset: 0x00000388) High-End Overlay VDMA Next Register -------- */
#define LCDC_HEOVNEXT_VNEXT_Pos 0
#define LCDC_HEOVNEXT_VNEXT_Msk (0xffffffffu << LCDC_HEOVNEXT_VNEXT_Pos) /**< \brief (LCDC_HEOVNEXT) DMA Descriptor Next Address */
#define LCDC_HEOVNEXT_VNEXT(value) ((LCDC_HEOVNEXT_VNEXT_Msk & ((value) << LCDC_HEOVNEXT_VNEXT_Pos)))
/* -------- LCDC_HEOCFG0 : (LCDC Offset: 0x0000038C) High-End Overlay Configuration Register 0 -------- */
#define LCDC_HEOCFG0_SIF (0x1u << 0) /**< \brief (LCDC_HEOCFG0) Source Interface */
#define LCDC_HEOCFG0_BLEN_Pos 4
#define LCDC_HEOCFG0_BLEN_Msk (0x3u << LCDC_HEOCFG0_BLEN_Pos) /**< \brief (LCDC_HEOCFG0) AHB Burst Length */
#define   LCDC_HEOCFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define LCDC_HEOCFG0_BLENUV_Pos 6
#define LCDC_HEOCFG0_BLENUV_Msk (0x3u << LCDC_HEOCFG0_BLENUV_Pos) /**< \brief (LCDC_HEOCFG0) AHB Burst Length for U-V channel */
#define   LCDC_HEOCFG0_BLENUV_AHB_SINGLE (0x0u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_HEOCFG0_BLENUV_AHB_INCR4 (0x1u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_HEOCFG0_BLENUV_AHB_INCR8 (0x2u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_HEOCFG0_BLENUV_AHB_INCR16 (0x3u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define LCDC_HEOCFG0_DLBO (0x1u << 8) /**< \brief (LCDC_HEOCFG0) Defined Length Burst Only For Channel Bus Transaction. */
#define LCDC_HEOCFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_HEOCFG0) Hardware Rotation Optimization Disable */
#define LCDC_HEOCFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_HEOCFG0) Hardware Rotation Lock Disable */
/* -------- LCDC_HEOCFG1 : (LCDC Offset: 0x00000390) High-End Overlay Configuration Register 1 -------- */
#define LCDC_HEOCFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_HEOCFG1) Color Lookup Table Enable */
#define LCDC_HEOCFG1_YUVEN (0x1u << 1) /**< \brief (LCDC_HEOCFG1) YUV Color Space Enable */
#define LCDC_HEOCFG1_RGBMODE_Pos 4
#define LCDC_HEOCFG1_RGBMODE_Msk (0xfu << LCDC_HEOCFG1_RGBMODE_Pos) /**< \brief (LCDC_HEOCFG1) RGB input mode selection */
#define   LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_HEOCFG1) 12 bpp RGB 444 */
#define   LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp ARGB 4444 */
#define   LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp RGBA 4444 */
#define   LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp RGB 565 */
#define   LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp TRGB 1555 */
#define   LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_HEOCFG1) 18 bpp RGB 666 */
#define   LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_HEOCFG1) 18 bpp RGB 666 PACKED */
#define   LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_HEOCFG1) 19 bpp TRGB 1666 */
#define   LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_HEOCFG1) 19 bpp TRGB 1666 PACKED */
#define   LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_HEOCFG1) 24 bpp RGB 888 */
#define   LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_HEOCFG1) 24 bpp RGB 888 PACKED */
#define   LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_HEOCFG1) 25 bpp TRGB 1888 */
#define   LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_HEOCFG1) 32 bpp ARGB 8888 */
#define   LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_HEOCFG1) 32 bpp RGBA 8888 */
#define LCDC_HEOCFG1_CLUTMODE_Pos 8
#define LCDC_HEOCFG1_CLUTMODE_Msk (0x3u << LCDC_HEOCFG1_CLUTMODE_Pos) /**< \brief (LCDC_HEOCFG1) Color Lookup table input mode selection */
#define   LCDC_HEOCFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_HEOCFG1) color lookup table mode set to 1 bit per pixel */
#define   LCDC_HEOCFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_HEOCFG1) color lookup table mode set to 2 bits per pixel */
#define   LCDC_HEOCFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_HEOCFG1) color lookup table mode set to 4 bits per pixel */
#define   LCDC_HEOCFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_HEOCFG1) color lookup table mode set to 8 bits per pixel */
#define LCDC_HEOCFG1_YUVMODE_Pos 12
#define LCDC_HEOCFG1_YUVMODE_Msk (0xfu << LCDC_HEOCFG1_YUVMODE_Pos) /**< \brief (LCDC_HEOCFG1) YUV input mode selection */
#define   LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR (0x0u << 12) /**< \brief (LCDC_HEOCFG1) 32 bpp AYCbCr 444 */
#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0 (0x1u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Cr(n)Y(n+1)Cb(n)Y(n) 422 */
#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1 (0x2u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Y(n+1)Cr(n)Y(n)Cb(n) 422 */
#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2 (0x3u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Cb(n)Y(+1)Cr(n)Y(n) 422 */
#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3 (0x4u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Y(n+1)Cb(n)Y(n)Cr(n) 422 */
#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR (0x5u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Semiplanar 422 YCbCr */
#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR (0x6u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Planar 422 YCbCr */
#define   LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR (0x7u << 12) /**< \brief (LCDC_HEOCFG1) 12 bpp Semiplanar 420 YCbCr */
#define   LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR (0x8u << 12) /**< \brief (LCDC_HEOCFG1) 12 bpp Planar 420 YCbCr */
#define LCDC_HEOCFG1_YUV422ROT (0x1u << 16) /**< \brief (LCDC_HEOCFG1) YUV 4:2:2 Rotation */
#define LCDC_HEOCFG1_YUV422SWP (0x1u << 17) /**< \brief (LCDC_HEOCFG1) YUV 4:2:2 SWAP */
#define LCDC_HEOCFG1_DSCALEOPT (0x1u << 20) /**< \brief (LCDC_HEOCFG1) Down Scaling Bandwidth Optimization */
/* -------- LCDC_HEOCFG2 : (LCDC Offset: 0x00000394) High-End Overlay Configuration Register 2 -------- */
#define LCDC_HEOCFG2_XPOS_Pos 0
#define LCDC_HEOCFG2_XPOS_Msk (0x7ffu << LCDC_HEOCFG2_XPOS_Pos) /**< \brief (LCDC_HEOCFG2) Horizontal Window Position */
#define LCDC_HEOCFG2_XPOS(value) ((LCDC_HEOCFG2_XPOS_Msk & ((value) << LCDC_HEOCFG2_XPOS_Pos)))
#define LCDC_HEOCFG2_YPOS_Pos 16
#define LCDC_HEOCFG2_YPOS_Msk (0x7ffu << LCDC_HEOCFG2_YPOS_Pos) /**< \brief (LCDC_HEOCFG2) Vertical Window Position */
#define LCDC_HEOCFG2_YPOS(value) ((LCDC_HEOCFG2_YPOS_Msk & ((value) << LCDC_HEOCFG2_YPOS_Pos)))
/* -------- LCDC_HEOCFG3 : (LCDC Offset: 0x00000398) High-End Overlay Configuration Register 3 -------- */
#define LCDC_HEOCFG3_XSIZE_Pos 0
#define LCDC_HEOCFG3_XSIZE_Msk (0x7ffu << LCDC_HEOCFG3_XSIZE_Pos) /**< \brief (LCDC_HEOCFG3) Horizontal Window Size */
#define LCDC_HEOCFG3_XSIZE(value) ((LCDC_HEOCFG3_XSIZE_Msk & ((value) << LCDC_HEOCFG3_XSIZE_Pos)))
#define LCDC_HEOCFG3_YSIZE_Pos 16
#define LCDC_HEOCFG3_YSIZE_Msk (0x7ffu << LCDC_HEOCFG3_YSIZE_Pos) /**< \brief (LCDC_HEOCFG3) Vertical Window Size */
#define LCDC_HEOCFG3_YSIZE(value) ((LCDC_HEOCFG3_YSIZE_Msk & ((value) << LCDC_HEOCFG3_YSIZE_Pos)))
/* -------- LCDC_HEOCFG4 : (LCDC Offset: 0x0000039C) High-End Overlay Configuration Register 4 -------- */
#define LCDC_HEOCFG4_XMEM_SIZE_Pos 0
#define LCDC_HEOCFG4_XMEM_SIZE_Msk (0x7ffu << LCDC_HEOCFG4_XMEM_SIZE_Pos) /**< \brief (LCDC_HEOCFG4) Horizontal image Size in Memory */
#define LCDC_HEOCFG4_XMEM_SIZE(value) ((LCDC_HEOCFG4_XMEM_SIZE_Msk & ((value) << LCDC_HEOCFG4_XMEM_SIZE_Pos)))
#define LCDC_HEOCFG4_YMEM_SIZE_Pos 16
#define LCDC_HEOCFG4_YMEM_SIZE_Msk (0x7ffu << LCDC_HEOCFG4_YMEM_SIZE_Pos) /**< \brief (LCDC_HEOCFG4) Vertical image Size in Memory */
#define LCDC_HEOCFG4_YMEM_SIZE(value) ((LCDC_HEOCFG4_YMEM_SIZE_Msk & ((value) << LCDC_HEOCFG4_YMEM_SIZE_Pos)))
/* -------- LCDC_HEOCFG5 : (LCDC Offset: 0x000003A0) High-End Overlay Configuration Register 5 -------- */
#define LCDC_HEOCFG5_XSTRIDE_Pos 0
#define LCDC_HEOCFG5_XSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG5_XSTRIDE_Pos) /**< \brief (LCDC_HEOCFG5) Horizontal Stride */
#define LCDC_HEOCFG5_XSTRIDE(value) ((LCDC_HEOCFG5_XSTRIDE_Msk & ((value) << LCDC_HEOCFG5_XSTRIDE_Pos)))
/* -------- LCDC_HEOCFG6 : (LCDC Offset: 0x000003A4) High-End Overlay Configuration Register 6 -------- */
#define LCDC_HEOCFG6_PSTRIDE_Pos 0
#define LCDC_HEOCFG6_PSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG6_PSTRIDE_Pos) /**< \brief (LCDC_HEOCFG6) Pixel Stride */
#define LCDC_HEOCFG6_PSTRIDE(value) ((LCDC_HEOCFG6_PSTRIDE_Msk & ((value) << LCDC_HEOCFG6_PSTRIDE_Pos)))
/* -------- LCDC_HEOCFG7 : (LCDC Offset: 0x000003A8) High-End Overlay Configuration Register 7 -------- */
#define LCDC_HEOCFG7_UVXSTRIDE_Pos 0
#define LCDC_HEOCFG7_UVXSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG7_UVXSTRIDE_Pos) /**< \brief (LCDC_HEOCFG7) UV Horizontal Stride */
#define LCDC_HEOCFG7_UVXSTRIDE(value) ((LCDC_HEOCFG7_UVXSTRIDE_Msk & ((value) << LCDC_HEOCFG7_UVXSTRIDE_Pos)))
/* -------- LCDC_HEOCFG8 : (LCDC Offset: 0x000003AC) High-End Overlay Configuration Register 8 -------- */
#define LCDC_HEOCFG8_UVPSTRIDE_Pos 0
#define LCDC_HEOCFG8_UVPSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG8_UVPSTRIDE_Pos) /**< \brief (LCDC_HEOCFG8) UV Pixel Stride */
#define LCDC_HEOCFG8_UVPSTRIDE(value) ((LCDC_HEOCFG8_UVPSTRIDE_Msk & ((value) << LCDC_HEOCFG8_UVPSTRIDE_Pos)))
/* -------- LCDC_HEOCFG9 : (LCDC Offset: 0x000003B0) High-End Overlay Configuration Register 9 -------- */
#define LCDC_HEOCFG9_BDEF_Pos 0
#define LCDC_HEOCFG9_BDEF_Msk (0xffu << LCDC_HEOCFG9_BDEF_Pos) /**< \brief (LCDC_HEOCFG9) Blue Default */
#define LCDC_HEOCFG9_BDEF(value) ((LCDC_HEOCFG9_BDEF_Msk & ((value) << LCDC_HEOCFG9_BDEF_Pos)))
#define LCDC_HEOCFG9_GDEF_Pos 8
#define LCDC_HEOCFG9_GDEF_Msk (0xffu << LCDC_HEOCFG9_GDEF_Pos) /**< \brief (LCDC_HEOCFG9) Green Default */
#define LCDC_HEOCFG9_GDEF(value) ((LCDC_HEOCFG9_GDEF_Msk & ((value) << LCDC_HEOCFG9_GDEF_Pos)))
#define LCDC_HEOCFG9_RDEF_Pos 16
#define LCDC_HEOCFG9_RDEF_Msk (0xffu << LCDC_HEOCFG9_RDEF_Pos) /**< \brief (LCDC_HEOCFG9) Red Default */
#define LCDC_HEOCFG9_RDEF(value) ((LCDC_HEOCFG9_RDEF_Msk & ((value) << LCDC_HEOCFG9_RDEF_Pos)))
/* -------- LCDC_HEOCFG10 : (LCDC Offset: 0x000003B4) High-End Overlay Configuration Register 10 -------- */
#define LCDC_HEOCFG10_BKEY_Pos 0
#define LCDC_HEOCFG10_BKEY_Msk (0xffu << LCDC_HEOCFG10_BKEY_Pos) /**< \brief (LCDC_HEOCFG10) Blue Color Component Chroma Key */
#define LCDC_HEOCFG10_BKEY(value) ((LCDC_HEOCFG10_BKEY_Msk & ((value) << LCDC_HEOCFG10_BKEY_Pos)))
#define LCDC_HEOCFG10_GKEY_Pos 8
#define LCDC_HEOCFG10_GKEY_Msk (0xffu << LCDC_HEOCFG10_GKEY_Pos) /**< \brief (LCDC_HEOCFG10) Green Color Component Chroma Key */
#define LCDC_HEOCFG10_GKEY(value) ((LCDC_HEOCFG10_GKEY_Msk & ((value) << LCDC_HEOCFG10_GKEY_Pos)))
#define LCDC_HEOCFG10_RKEY_Pos 16
#define LCDC_HEOCFG10_RKEY_Msk (0xffu << LCDC_HEOCFG10_RKEY_Pos) /**< \brief (LCDC_HEOCFG10) Red Color Component Chroma Key */
#define LCDC_HEOCFG10_RKEY(value) ((LCDC_HEOCFG10_RKEY_Msk & ((value) << LCDC_HEOCFG10_RKEY_Pos)))
/* -------- LCDC_HEOCFG11 : (LCDC Offset: 0x000003B8) High-End Overlay Configuration Register 11 -------- */
#define LCDC_HEOCFG11_BMASK_Pos 0
#define LCDC_HEOCFG11_BMASK_Msk (0xffu << LCDC_HEOCFG11_BMASK_Pos) /**< \brief (LCDC_HEOCFG11) Blue Color Component Chroma Key Mask */
#define LCDC_HEOCFG11_BMASK(value) ((LCDC_HEOCFG11_BMASK_Msk & ((value) << LCDC_HEOCFG11_BMASK_Pos)))
#define LCDC_HEOCFG11_GMASK_Pos 8
#define LCDC_HEOCFG11_GMASK_Msk (0xffu << LCDC_HEOCFG11_GMASK_Pos) /**< \brief (LCDC_HEOCFG11) Green Color Component Chroma Key Mask */
#define LCDC_HEOCFG11_GMASK(value) ((LCDC_HEOCFG11_GMASK_Msk & ((value) << LCDC_HEOCFG11_GMASK_Pos)))
#define LCDC_HEOCFG11_RMASK_Pos 16
#define LCDC_HEOCFG11_RMASK_Msk (0xffu << LCDC_HEOCFG11_RMASK_Pos) /**< \brief (LCDC_HEOCFG11) Red Color Component Chroma Key Mask */
#define LCDC_HEOCFG11_RMASK(value) ((LCDC_HEOCFG11_RMASK_Msk & ((value) << LCDC_HEOCFG11_RMASK_Pos)))
/* -------- LCDC_HEOCFG12 : (LCDC Offset: 0x000003BC) High-End Overlay Configuration Register 12 -------- */
#define LCDC_HEOCFG12_CRKEY (0x1u << 0) /**< \brief (LCDC_HEOCFG12) Blender Chroma Key Enable */
#define LCDC_HEOCFG12_INV (0x1u << 1) /**< \brief (LCDC_HEOCFG12) Blender Inverted Blender Output Enable */
#define LCDC_HEOCFG12_ITER2BL (0x1u << 2) /**< \brief (LCDC_HEOCFG12) Blender Iterated Color Enable */
#define LCDC_HEOCFG12_ITER (0x1u << 3) /**< \brief (LCDC_HEOCFG12) Blender Use Iterated Color */
#define LCDC_HEOCFG12_REVALPHA (0x1u << 4) /**< \brief (LCDC_HEOCFG12) Blender Reverse Alpha */
#define LCDC_HEOCFG12_GAEN (0x1u << 5) /**< \brief (LCDC_HEOCFG12) Blender Global Alpha Enable */
#define LCDC_HEOCFG12_LAEN (0x1u << 6) /**< \brief (LCDC_HEOCFG12) Blender Local Alpha Enable */
#define LCDC_HEOCFG12_OVR (0x1u << 7) /**< \brief (LCDC_HEOCFG12) Blender Overlay Layer Enable */
#define LCDC_HEOCFG12_DMA (0x1u << 8) /**< \brief (LCDC_HEOCFG12) Blender DMA Layer Enable */
#define LCDC_HEOCFG12_REP (0x1u << 9) /**< \brief (LCDC_HEOCFG12) Use Replication logic to expand RGB color to 24 bits */
#define LCDC_HEOCFG12_DSTKEY (0x1u << 10) /**< \brief (LCDC_HEOCFG12) Destination Chroma Keying */
#define LCDC_HEOCFG12_VIDPRI (0x1u << 12) /**< \brief (LCDC_HEOCFG12) Video Priority */
#define LCDC_HEOCFG12_GA_Pos 16
#define LCDC_HEOCFG12_GA_Msk (0xffu << LCDC_HEOCFG12_GA_Pos) /**< \brief (LCDC_HEOCFG12) Blender Global Alpha */
#define LCDC_HEOCFG12_GA(value) ((LCDC_HEOCFG12_GA_Msk & ((value) << LCDC_HEOCFG12_GA_Pos)))
/* -------- LCDC_HEOCFG13 : (LCDC Offset: 0x000003C0) High-End Overlay Configuration Register 13 -------- */
#define LCDC_HEOCFG13_XFACTOR_Pos 0
#define LCDC_HEOCFG13_XFACTOR_Msk (0x3fffu << LCDC_HEOCFG13_XFACTOR_Pos) /**< \brief (LCDC_HEOCFG13) Horizontal Scaling Factor */
#define LCDC_HEOCFG13_XFACTOR(value) ((LCDC_HEOCFG13_XFACTOR_Msk & ((value) << LCDC_HEOCFG13_XFACTOR_Pos)))
#define LCDC_HEOCFG13_YFACTOR_Pos 16
#define LCDC_HEOCFG13_YFACTOR_Msk (0x3fffu << LCDC_HEOCFG13_YFACTOR_Pos) /**< \brief (LCDC_HEOCFG13) Vertical Scaling Factor */
#define LCDC_HEOCFG13_YFACTOR(value) ((LCDC_HEOCFG13_YFACTOR_Msk & ((value) << LCDC_HEOCFG13_YFACTOR_Pos)))
#define LCDC_HEOCFG13_SCALEN (0x1u << 31) /**< \brief (LCDC_HEOCFG13) Hardware Scaler Enable */
/* -------- LCDC_HEOCFG14 : (LCDC Offset: 0x000003C4) High-End Overlay Configuration Register 14 -------- */
#define LCDC_HEOCFG14_CSCRY_Pos 0
#define LCDC_HEOCFG14_CSCRY_Msk (0x3ffu << LCDC_HEOCFG14_CSCRY_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion Y coefficient for Red Component 1:2:7 format */
#define LCDC_HEOCFG14_CSCRY(value) ((LCDC_HEOCFG14_CSCRY_Msk & ((value) << LCDC_HEOCFG14_CSCRY_Pos)))
#define LCDC_HEOCFG14_CSCRU_Pos 10
#define LCDC_HEOCFG14_CSCRU_Msk (0x3ffu << LCDC_HEOCFG14_CSCRU_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion U coefficient for Red Component 1:2:7 format */
#define LCDC_HEOCFG14_CSCRU(value) ((LCDC_HEOCFG14_CSCRU_Msk & ((value) << LCDC_HEOCFG14_CSCRU_Pos)))
#define LCDC_HEOCFG14_CSCRV_Pos 20
#define LCDC_HEOCFG14_CSCRV_Msk (0x3ffu << LCDC_HEOCFG14_CSCRV_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion V coefficient for Red Component 1:2:7 format */
#define LCDC_HEOCFG14_CSCRV(value) ((LCDC_HEOCFG14_CSCRV_Msk & ((value) << LCDC_HEOCFG14_CSCRV_Pos)))
#define LCDC_HEOCFG14_CSCYOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG14) Color Space Conversion Offset */
/* -------- LCDC_HEOCFG15 : (LCDC Offset: 0x000003C8) High-End Overlay Configuration Register 15 -------- */
#define LCDC_HEOCFG15_CSCGY_Pos 0
#define LCDC_HEOCFG15_CSCGY_Msk (0x3ffu << LCDC_HEOCFG15_CSCGY_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion Y coefficient for Green Component 1:2:7 format */
#define LCDC_HEOCFG15_CSCGY(value) ((LCDC_HEOCFG15_CSCGY_Msk & ((value) << LCDC_HEOCFG15_CSCGY_Pos)))
#define LCDC_HEOCFG15_CSCGU_Pos 10
#define LCDC_HEOCFG15_CSCGU_Msk (0x3ffu << LCDC_HEOCFG15_CSCGU_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion U coefficient for Green Component 1:2:7 format */
#define LCDC_HEOCFG15_CSCGU(value) ((LCDC_HEOCFG15_CSCGU_Msk & ((value) << LCDC_HEOCFG15_CSCGU_Pos)))
#define LCDC_HEOCFG15_CSCGV_Pos 20
#define LCDC_HEOCFG15_CSCGV_Msk (0x3ffu << LCDC_HEOCFG15_CSCGV_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion V coefficient for Green Component 1:2:7 format */
#define LCDC_HEOCFG15_CSCGV(value) ((LCDC_HEOCFG15_CSCGV_Msk & ((value) << LCDC_HEOCFG15_CSCGV_Pos)))
#define LCDC_HEOCFG15_CSCUOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG15) Color Space Conversion Offset */
/* -------- LCDC_HEOCFG16 : (LCDC Offset: 0x000003CC) High-End Overlay Configuration Register 16 -------- */
#define LCDC_HEOCFG16_CSCBY_Pos 0
#define LCDC_HEOCFG16_CSCBY_Msk (0x3ffu << LCDC_HEOCFG16_CSCBY_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion Y coefficient for Blue Component 1:2:7 format */
#define LCDC_HEOCFG16_CSCBY(value) ((LCDC_HEOCFG16_CSCBY_Msk & ((value) << LCDC_HEOCFG16_CSCBY_Pos)))
#define LCDC_HEOCFG16_CSCBU_Pos 10
#define LCDC_HEOCFG16_CSCBU_Msk (0x3ffu << LCDC_HEOCFG16_CSCBU_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion U coefficient for Blue Component 1:2:7 format */
#define LCDC_HEOCFG16_CSCBU(value) ((LCDC_HEOCFG16_CSCBU_Msk & ((value) << LCDC_HEOCFG16_CSCBU_Pos)))
#define LCDC_HEOCFG16_CSCBV_Pos 20
#define LCDC_HEOCFG16_CSCBV_Msk (0x3ffu << LCDC_HEOCFG16_CSCBV_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion V coefficient for Blue Component 1:2:7 format */
#define LCDC_HEOCFG16_CSCBV(value) ((LCDC_HEOCFG16_CSCBV_Msk & ((value) << LCDC_HEOCFG16_CSCBV_Pos)))
#define LCDC_HEOCFG16_CSCVOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG16) Color Space Conversion Offset */
/* -------- LCDC_HEOCFG17 : (LCDC Offset: 0x000003D0) High-End Overlay Configuration Register 17 -------- */
#define LCDC_HEOCFG17_XPHI0COEFF0_Pos 0
#define LCDC_HEOCFG17_XPHI0COEFF0_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF0_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 0 */
#define LCDC_HEOCFG17_XPHI0COEFF0(value) ((LCDC_HEOCFG17_XPHI0COEFF0_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF0_Pos)))
#define LCDC_HEOCFG17_XPHI0COEFF1_Pos 8
#define LCDC_HEOCFG17_XPHI0COEFF1_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF1_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 1 */
#define LCDC_HEOCFG17_XPHI0COEFF1(value) ((LCDC_HEOCFG17_XPHI0COEFF1_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF1_Pos)))
#define LCDC_HEOCFG17_XPHI0COEFF2_Pos 16
#define LCDC_HEOCFG17_XPHI0COEFF2_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF2_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 2 */
#define LCDC_HEOCFG17_XPHI0COEFF2(value) ((LCDC_HEOCFG17_XPHI0COEFF2_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF2_Pos)))
#define LCDC_HEOCFG17_XPHI0COEFF3_Pos 24
#define LCDC_HEOCFG17_XPHI0COEFF3_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF3_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 3 */
#define LCDC_HEOCFG17_XPHI0COEFF3(value) ((LCDC_HEOCFG17_XPHI0COEFF3_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF3_Pos)))
/* -------- LCDC_HEOCFG18 : (LCDC Offset: 0x000003D4) High-End Overlay Configuration Register 18 -------- */
#define LCDC_HEOCFG18_XPHI0COEFF4_Pos 0
#define LCDC_HEOCFG18_XPHI0COEFF4_Msk (0xffu << LCDC_HEOCFG18_XPHI0COEFF4_Pos) /**< \brief (LCDC_HEOCFG18) Horizontal Coefficient for phase 0 tap 4 */
#define LCDC_HEOCFG18_XPHI0COEFF4(value) ((LCDC_HEOCFG18_XPHI0COEFF4_Msk & ((value) << LCDC_HEOCFG18_XPHI0COEFF4_Pos)))
/* -------- LCDC_HEOCFG19 : (LCDC Offset: 0x000003D8) High-End Overlay Configuration Register 19 -------- */
#define LCDC_HEOCFG19_XPHI1COEFF0_Pos 0
#define LCDC_HEOCFG19_XPHI1COEFF0_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF0_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 0 */
#define LCDC_HEOCFG19_XPHI1COEFF0(value) ((LCDC_HEOCFG19_XPHI1COEFF0_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF0_Pos)))
#define LCDC_HEOCFG19_XPHI1COEFF1_Pos 8
#define LCDC_HEOCFG19_XPHI1COEFF1_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF1_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 1 */
#define LCDC_HEOCFG19_XPHI1COEFF1(value) ((LCDC_HEOCFG19_XPHI1COEFF1_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF1_Pos)))
#define LCDC_HEOCFG19_XPHI1COEFF2_Pos 16
#define LCDC_HEOCFG19_XPHI1COEFF2_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF2_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 2 */
#define LCDC_HEOCFG19_XPHI1COEFF2(value) ((LCDC_HEOCFG19_XPHI1COEFF2_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF2_Pos)))
#define LCDC_HEOCFG19_XPHI1COEFF3_Pos 24
#define LCDC_HEOCFG19_XPHI1COEFF3_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF3_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 3 */
#define LCDC_HEOCFG19_XPHI1COEFF3(value) ((LCDC_HEOCFG19_XPHI1COEFF3_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF3_Pos)))
/* -------- LCDC_HEOCFG20 : (LCDC Offset: 0x000003DC) High-End Overlay Configuration Register 20 -------- */
#define LCDC_HEOCFG20_XPHI1COEFF4_Pos 0
#define LCDC_HEOCFG20_XPHI1COEFF4_Msk (0xffu << LCDC_HEOCFG20_XPHI1COEFF4_Pos) /**< \brief (LCDC_HEOCFG20) Horizontal Coefficient for phase 1 tap 4 */
#define LCDC_HEOCFG20_XPHI1COEFF4(value) ((LCDC_HEOCFG20_XPHI1COEFF4_Msk & ((value) << LCDC_HEOCFG20_XPHI1COEFF4_Pos)))
/* -------- LCDC_HEOCFG21 : (LCDC Offset: 0x000003E0) High-End Overlay Configuration Register 21 -------- */
#define LCDC_HEOCFG21_XPHI2COEFF0_Pos 0
#define LCDC_HEOCFG21_XPHI2COEFF0_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF0_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 0 */
#define LCDC_HEOCFG21_XPHI2COEFF0(value) ((LCDC_HEOCFG21_XPHI2COEFF0_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF0_Pos)))
#define LCDC_HEOCFG21_XPHI2COEFF1_Pos 8
#define LCDC_HEOCFG21_XPHI2COEFF1_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF1_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 1 */
#define LCDC_HEOCFG21_XPHI2COEFF1(value) ((LCDC_HEOCFG21_XPHI2COEFF1_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF1_Pos)))
#define LCDC_HEOCFG21_XPHI2COEFF2_Pos 16
#define LCDC_HEOCFG21_XPHI2COEFF2_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF2_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 2 */
#define LCDC_HEOCFG21_XPHI2COEFF2(value) ((LCDC_HEOCFG21_XPHI2COEFF2_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF2_Pos)))
#define LCDC_HEOCFG21_XPHI2COEFF3_Pos 24
#define LCDC_HEOCFG21_XPHI2COEFF3_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF3_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 3 */
#define LCDC_HEOCFG21_XPHI2COEFF3(value) ((LCDC_HEOCFG21_XPHI2COEFF3_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF3_Pos)))
/* -------- LCDC_HEOCFG22 : (LCDC Offset: 0x000003E4) High-End Overlay Configuration Register 22 -------- */
#define LCDC_HEOCFG22_XPHI2COEFF4_Pos 0
#define LCDC_HEOCFG22_XPHI2COEFF4_Msk (0xffu << LCDC_HEOCFG22_XPHI2COEFF4_Pos) /**< \brief (LCDC_HEOCFG22) Horizontal Coefficient for phase 2 tap 4 */
#define LCDC_HEOCFG22_XPHI2COEFF4(value) ((LCDC_HEOCFG22_XPHI2COEFF4_Msk & ((value) << LCDC_HEOCFG22_XPHI2COEFF4_Pos)))
/* -------- LCDC_HEOCFG23 : (LCDC Offset: 0x000003E8) High-End Overlay Configuration Register 23 -------- */
#define LCDC_HEOCFG23_XPHI3COEFF0_Pos 0
#define LCDC_HEOCFG23_XPHI3COEFF0_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF0_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 0 */
#define LCDC_HEOCFG23_XPHI3COEFF0(value) ((LCDC_HEOCFG23_XPHI3COEFF0_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF0_Pos)))
#define LCDC_HEOCFG23_XPHI3COEFF1_Pos 8
#define LCDC_HEOCFG23_XPHI3COEFF1_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF1_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 1 */
#define LCDC_HEOCFG23_XPHI3COEFF1(value) ((LCDC_HEOCFG23_XPHI3COEFF1_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF1_Pos)))
#define LCDC_HEOCFG23_XPHI3COEFF2_Pos 16
#define LCDC_HEOCFG23_XPHI3COEFF2_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF2_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 2 */
#define LCDC_HEOCFG23_XPHI3COEFF2(value) ((LCDC_HEOCFG23_XPHI3COEFF2_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF2_Pos)))
#define LCDC_HEOCFG23_XPHI3COEFF3_Pos 24
#define LCDC_HEOCFG23_XPHI3COEFF3_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF3_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 3 */
#define LCDC_HEOCFG23_XPHI3COEFF3(value) ((LCDC_HEOCFG23_XPHI3COEFF3_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF3_Pos)))
/* -------- LCDC_HEOCFG24 : (LCDC Offset: 0x000003EC) High-End Overlay Configuration Register 24 -------- */
#define LCDC_HEOCFG24_XPHI3COEFF4_Pos 0
#define LCDC_HEOCFG24_XPHI3COEFF4_Msk (0xffu << LCDC_HEOCFG24_XPHI3COEFF4_Pos) /**< \brief (LCDC_HEOCFG24) Horizontal Coefficient for phase 3 tap 4 */
#define LCDC_HEOCFG24_XPHI3COEFF4(value) ((LCDC_HEOCFG24_XPHI3COEFF4_Msk & ((value) << LCDC_HEOCFG24_XPHI3COEFF4_Pos)))
/* -------- LCDC_HEOCFG25 : (LCDC Offset: 0x000003F0) High-End Overlay Configuration Register 25 -------- */
#define LCDC_HEOCFG25_XPHI4COEFF0_Pos 0
#define LCDC_HEOCFG25_XPHI4COEFF0_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF0_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 0 */
#define LCDC_HEOCFG25_XPHI4COEFF0(value) ((LCDC_HEOCFG25_XPHI4COEFF0_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF0_Pos)))
#define LCDC_HEOCFG25_XPHI4COEFF1_Pos 8
#define LCDC_HEOCFG25_XPHI4COEFF1_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF1_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 1 */
#define LCDC_HEOCFG25_XPHI4COEFF1(value) ((LCDC_HEOCFG25_XPHI4COEFF1_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF1_Pos)))
#define LCDC_HEOCFG25_XPHI4COEFF2_Pos 16
#define LCDC_HEOCFG25_XPHI4COEFF2_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF2_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 2 */
#define LCDC_HEOCFG25_XPHI4COEFF2(value) ((LCDC_HEOCFG25_XPHI4COEFF2_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF2_Pos)))
#define LCDC_HEOCFG25_XPHI4COEFF3_Pos 24
#define LCDC_HEOCFG25_XPHI4COEFF3_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF3_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 3 */
#define LCDC_HEOCFG25_XPHI4COEFF3(value) ((LCDC_HEOCFG25_XPHI4COEFF3_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF3_Pos)))
/* -------- LCDC_HEOCFG26 : (LCDC Offset: 0x000003F4) High-End Overlay Configuration Register 26 -------- */
#define LCDC_HEOCFG26_XPHI4COEFF4_Pos 0
#define LCDC_HEOCFG26_XPHI4COEFF4_Msk (0xffu << LCDC_HEOCFG26_XPHI4COEFF4_Pos) /**< \brief (LCDC_HEOCFG26) Horizontal Coefficient for phase 4 tap 4 */
#define LCDC_HEOCFG26_XPHI4COEFF4(value) ((LCDC_HEOCFG26_XPHI4COEFF4_Msk & ((value) << LCDC_HEOCFG26_XPHI4COEFF4_Pos)))
/* -------- LCDC_HEOCFG27 : (LCDC Offset: 0x000003F8) High-End Overlay Configuration Register 27 -------- */
#define LCDC_HEOCFG27_XPHI5COEFF0_Pos 0
#define LCDC_HEOCFG27_XPHI5COEFF0_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF0_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 0 */
#define LCDC_HEOCFG27_XPHI5COEFF0(value) ((LCDC_HEOCFG27_XPHI5COEFF0_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF0_Pos)))
#define LCDC_HEOCFG27_XPHI5COEFF1_Pos 8
#define LCDC_HEOCFG27_XPHI5COEFF1_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF1_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 1 */
#define LCDC_HEOCFG27_XPHI5COEFF1(value) ((LCDC_HEOCFG27_XPHI5COEFF1_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF1_Pos)))
#define LCDC_HEOCFG27_XPHI5COEFF2_Pos 16
#define LCDC_HEOCFG27_XPHI5COEFF2_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF2_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 2 */
#define LCDC_HEOCFG27_XPHI5COEFF2(value) ((LCDC_HEOCFG27_XPHI5COEFF2_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF2_Pos)))
#define LCDC_HEOCFG27_XPHI5COEFF3_Pos 24
#define LCDC_HEOCFG27_XPHI5COEFF3_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF3_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 3 */
#define LCDC_HEOCFG27_XPHI5COEFF3(value) ((LCDC_HEOCFG27_XPHI5COEFF3_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF3_Pos)))
/* -------- LCDC_HEOCFG28 : (LCDC Offset: 0x000003FC) High-End Overlay Configuration Register 28 -------- */
#define LCDC_HEOCFG28_XPHI5COEFF4_Pos 0
#define LCDC_HEOCFG28_XPHI5COEFF4_Msk (0xffu << LCDC_HEOCFG28_XPHI5COEFF4_Pos) /**< \brief (LCDC_HEOCFG28) Horizontal Coefficient for phase 5 tap 4 */
#define LCDC_HEOCFG28_XPHI5COEFF4(value) ((LCDC_HEOCFG28_XPHI5COEFF4_Msk & ((value) << LCDC_HEOCFG28_XPHI5COEFF4_Pos)))
/* -------- LCDC_HEOCFG29 : (LCDC Offset: 0x00000400) High-End Overlay Configuration Register 29 -------- */
#define LCDC_HEOCFG29_XPHI6COEFF0_Pos 0
#define LCDC_HEOCFG29_XPHI6COEFF0_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF0_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 0 */
#define LCDC_HEOCFG29_XPHI6COEFF0(value) ((LCDC_HEOCFG29_XPHI6COEFF0_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF0_Pos)))
#define LCDC_HEOCFG29_XPHI6COEFF1_Pos 8
#define LCDC_HEOCFG29_XPHI6COEFF1_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF1_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 1 */
#define LCDC_HEOCFG29_XPHI6COEFF1(value) ((LCDC_HEOCFG29_XPHI6COEFF1_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF1_Pos)))
#define LCDC_HEOCFG29_XPHI6COEFF2_Pos 16
#define LCDC_HEOCFG29_XPHI6COEFF2_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF2_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 2 */
#define LCDC_HEOCFG29_XPHI6COEFF2(value) ((LCDC_HEOCFG29_XPHI6COEFF2_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF2_Pos)))
#define LCDC_HEOCFG29_XPHI6COEFF3_Pos 24
#define LCDC_HEOCFG29_XPHI6COEFF3_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF3_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 3 */
#define LCDC_HEOCFG29_XPHI6COEFF3(value) ((LCDC_HEOCFG29_XPHI6COEFF3_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF3_Pos)))
/* -------- LCDC_HEOCFG30 : (LCDC Offset: 0x00000404) High-End Overlay Configuration Register 30 -------- */
#define LCDC_HEOCFG30_XPHI6COEFF4_Pos 0
#define LCDC_HEOCFG30_XPHI6COEFF4_Msk (0xffu << LCDC_HEOCFG30_XPHI6COEFF4_Pos) /**< \brief (LCDC_HEOCFG30) Horizontal Coefficient for phase 6 tap 4 */
#define LCDC_HEOCFG30_XPHI6COEFF4(value) ((LCDC_HEOCFG30_XPHI6COEFF4_Msk & ((value) << LCDC_HEOCFG30_XPHI6COEFF4_Pos)))
/* -------- LCDC_HEOCFG31 : (LCDC Offset: 0x00000408) High-End Overlay Configuration Register 31 -------- */
#define LCDC_HEOCFG31_XPHI7COEFF0_Pos 0
#define LCDC_HEOCFG31_XPHI7COEFF0_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF0_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 0 */
#define LCDC_HEOCFG31_XPHI7COEFF0(value) ((LCDC_HEOCFG31_XPHI7COEFF0_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF0_Pos)))
#define LCDC_HEOCFG31_XPHI7COEFF1_Pos 8
#define LCDC_HEOCFG31_XPHI7COEFF1_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF1_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 1 */
#define LCDC_HEOCFG31_XPHI7COEFF1(value) ((LCDC_HEOCFG31_XPHI7COEFF1_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF1_Pos)))
#define LCDC_HEOCFG31_XPHI7COEFF2_Pos 16
#define LCDC_HEOCFG31_XPHI7COEFF2_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF2_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 2 */
#define LCDC_HEOCFG31_XPHI7COEFF2(value) ((LCDC_HEOCFG31_XPHI7COEFF2_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF2_Pos)))
#define LCDC_HEOCFG31_XPHI7COEFF3_Pos 24
#define LCDC_HEOCFG31_XPHI7COEFF3_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF3_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 3 */
#define LCDC_HEOCFG31_XPHI7COEFF3(value) ((LCDC_HEOCFG31_XPHI7COEFF3_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF3_Pos)))
/* -------- LCDC_HEOCFG32 : (LCDC Offset: 0x0000040C) High-End Overlay Configuration Register 32 -------- */
#define LCDC_HEOCFG32_XPHI7COEFF4_Pos 0
#define LCDC_HEOCFG32_XPHI7COEFF4_Msk (0xffu << LCDC_HEOCFG32_XPHI7COEFF4_Pos) /**< \brief (LCDC_HEOCFG32) Horizontal Coefficient for phase 7 tap 4 */
#define LCDC_HEOCFG32_XPHI7COEFF4(value) ((LCDC_HEOCFG32_XPHI7COEFF4_Msk & ((value) << LCDC_HEOCFG32_XPHI7COEFF4_Pos)))
/* -------- LCDC_HEOCFG33 : (LCDC Offset: 0x00000410) High-End Overlay Configuration Register 33 -------- */
#define LCDC_HEOCFG33_YPHI0COEFF0_Pos 0
#define LCDC_HEOCFG33_YPHI0COEFF0_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF0_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 0 */
#define LCDC_HEOCFG33_YPHI0COEFF0(value) ((LCDC_HEOCFG33_YPHI0COEFF0_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF0_Pos)))
#define LCDC_HEOCFG33_YPHI0COEFF1_Pos 8
#define LCDC_HEOCFG33_YPHI0COEFF1_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF1_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 1 */
#define LCDC_HEOCFG33_YPHI0COEFF1(value) ((LCDC_HEOCFG33_YPHI0COEFF1_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF1_Pos)))
#define LCDC_HEOCFG33_YPHI0COEFF2_Pos 16
#define LCDC_HEOCFG33_YPHI0COEFF2_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF2_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 2 */
#define LCDC_HEOCFG33_YPHI0COEFF2(value) ((LCDC_HEOCFG33_YPHI0COEFF2_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF2_Pos)))
/* -------- LCDC_HEOCFG34 : (LCDC Offset: 0x00000414) High-End Overlay Configuration Register 34 -------- */
#define LCDC_HEOCFG34_YPHI1COEFF0_Pos 0
#define LCDC_HEOCFG34_YPHI1COEFF0_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF0_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 0 */
#define LCDC_HEOCFG34_YPHI1COEFF0(value) ((LCDC_HEOCFG34_YPHI1COEFF0_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF0_Pos)))
#define LCDC_HEOCFG34_YPHI1COEFF1_Pos 8
#define LCDC_HEOCFG34_YPHI1COEFF1_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF1_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 1 */
#define LCDC_HEOCFG34_YPHI1COEFF1(value) ((LCDC_HEOCFG34_YPHI1COEFF1_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF1_Pos)))
#define LCDC_HEOCFG34_YPHI1COEFF2_Pos 16
#define LCDC_HEOCFG34_YPHI1COEFF2_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF2_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 2 */
#define LCDC_HEOCFG34_YPHI1COEFF2(value) ((LCDC_HEOCFG34_YPHI1COEFF2_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF2_Pos)))
/* -------- LCDC_HEOCFG35 : (LCDC Offset: 0x00000418) High-End Overlay Configuration Register 35 -------- */
#define LCDC_HEOCFG35_YPHI2COEFF0_Pos 0
#define LCDC_HEOCFG35_YPHI2COEFF0_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF0_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 0 */
#define LCDC_HEOCFG35_YPHI2COEFF0(value) ((LCDC_HEOCFG35_YPHI2COEFF0_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF0_Pos)))
#define LCDC_HEOCFG35_YPHI2COEFF1_Pos 8
#define LCDC_HEOCFG35_YPHI2COEFF1_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF1_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 1 */
#define LCDC_HEOCFG35_YPHI2COEFF1(value) ((LCDC_HEOCFG35_YPHI2COEFF1_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF1_Pos)))
#define LCDC_HEOCFG35_YPHI2COEFF2_Pos 16
#define LCDC_HEOCFG35_YPHI2COEFF2_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF2_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 2 */
#define LCDC_HEOCFG35_YPHI2COEFF2(value) ((LCDC_HEOCFG35_YPHI2COEFF2_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF2_Pos)))
/* -------- LCDC_HEOCFG36 : (LCDC Offset: 0x0000041C) High-End Overlay Configuration Register 36 -------- */
#define LCDC_HEOCFG36_YPHI3COEFF0_Pos 0
#define LCDC_HEOCFG36_YPHI3COEFF0_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF0_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 0 */
#define LCDC_HEOCFG36_YPHI3COEFF0(value) ((LCDC_HEOCFG36_YPHI3COEFF0_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF0_Pos)))
#define LCDC_HEOCFG36_YPHI3COEFF1_Pos 8
#define LCDC_HEOCFG36_YPHI3COEFF1_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF1_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 1 */
#define LCDC_HEOCFG36_YPHI3COEFF1(value) ((LCDC_HEOCFG36_YPHI3COEFF1_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF1_Pos)))
#define LCDC_HEOCFG36_YPHI3COEFF2_Pos 16
#define LCDC_HEOCFG36_YPHI3COEFF2_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF2_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 2 */
#define LCDC_HEOCFG36_YPHI3COEFF2(value) ((LCDC_HEOCFG36_YPHI3COEFF2_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF2_Pos)))
/* -------- LCDC_HEOCFG37 : (LCDC Offset: 0x00000420) High-End Overlay Configuration Register 37 -------- */
#define LCDC_HEOCFG37_YPHI4COEFF0_Pos 0
#define LCDC_HEOCFG37_YPHI4COEFF0_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF0_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 0 */
#define LCDC_HEOCFG37_YPHI4COEFF0(value) ((LCDC_HEOCFG37_YPHI4COEFF0_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF0_Pos)))
#define LCDC_HEOCFG37_YPHI4COEFF1_Pos 8
#define LCDC_HEOCFG37_YPHI4COEFF1_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF1_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 1 */
#define LCDC_HEOCFG37_YPHI4COEFF1(value) ((LCDC_HEOCFG37_YPHI4COEFF1_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF1_Pos)))
#define LCDC_HEOCFG37_YPHI4COEFF2_Pos 16
#define LCDC_HEOCFG37_YPHI4COEFF2_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF2_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 2 */
#define LCDC_HEOCFG37_YPHI4COEFF2(value) ((LCDC_HEOCFG37_YPHI4COEFF2_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF2_Pos)))
/* -------- LCDC_HEOCFG38 : (LCDC Offset: 0x00000424) High-End Overlay Configuration Register 38 -------- */
#define LCDC_HEOCFG38_YPHI5COEFF0_Pos 0
#define LCDC_HEOCFG38_YPHI5COEFF0_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF0_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 0 */
#define LCDC_HEOCFG38_YPHI5COEFF0(value) ((LCDC_HEOCFG38_YPHI5COEFF0_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF0_Pos)))
#define LCDC_HEOCFG38_YPHI5COEFF1_Pos 8
#define LCDC_HEOCFG38_YPHI5COEFF1_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF1_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 1 */
#define LCDC_HEOCFG38_YPHI5COEFF1(value) ((LCDC_HEOCFG38_YPHI5COEFF1_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF1_Pos)))
#define LCDC_HEOCFG38_YPHI5COEFF2_Pos 16
#define LCDC_HEOCFG38_YPHI5COEFF2_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF2_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 2 */
#define LCDC_HEOCFG38_YPHI5COEFF2(value) ((LCDC_HEOCFG38_YPHI5COEFF2_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF2_Pos)))
/* -------- LCDC_HEOCFG39 : (LCDC Offset: 0x00000428) High-End Overlay Configuration Register 39 -------- */
#define LCDC_HEOCFG39_YPHI6COEFF0_Pos 0
#define LCDC_HEOCFG39_YPHI6COEFF0_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF0_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 0 */
#define LCDC_HEOCFG39_YPHI6COEFF0(value) ((LCDC_HEOCFG39_YPHI6COEFF0_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF0_Pos)))
#define LCDC_HEOCFG39_YPHI6COEFF1_Pos 8
#define LCDC_HEOCFG39_YPHI6COEFF1_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF1_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 1 */
#define LCDC_HEOCFG39_YPHI6COEFF1(value) ((LCDC_HEOCFG39_YPHI6COEFF1_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF1_Pos)))
#define LCDC_HEOCFG39_YPHI6COEFF2_Pos 16
#define LCDC_HEOCFG39_YPHI6COEFF2_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF2_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 2 */
#define LCDC_HEOCFG39_YPHI6COEFF2(value) ((LCDC_HEOCFG39_YPHI6COEFF2_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF2_Pos)))
/* -------- LCDC_HEOCFG40 : (LCDC Offset: 0x0000042C) High-End Overlay Configuration Register 40 -------- */
#define LCDC_HEOCFG40_YPHI7COEFF0_Pos 0
#define LCDC_HEOCFG40_YPHI7COEFF0_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF0_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 0 */
#define LCDC_HEOCFG40_YPHI7COEFF0(value) ((LCDC_HEOCFG40_YPHI7COEFF0_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF0_Pos)))
#define LCDC_HEOCFG40_YPHI7COEFF1_Pos 8
#define LCDC_HEOCFG40_YPHI7COEFF1_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF1_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 1 */
#define LCDC_HEOCFG40_YPHI7COEFF1(value) ((LCDC_HEOCFG40_YPHI7COEFF1_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF1_Pos)))
#define LCDC_HEOCFG40_YPHI7COEFF2_Pos 16
#define LCDC_HEOCFG40_YPHI7COEFF2_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF2_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 2 */
#define LCDC_HEOCFG40_YPHI7COEFF2(value) ((LCDC_HEOCFG40_YPHI7COEFF2_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF2_Pos)))
/* -------- LCDC_HEOCFG41 : (LCDC Offset: 0x00000430) High-End Overlay Configuration Register 41 -------- */
#define LCDC_HEOCFG41_XPHIDEF_Pos 0
#define LCDC_HEOCFG41_XPHIDEF_Msk (0x7u << LCDC_HEOCFG41_XPHIDEF_Pos) /**< \brief (LCDC_HEOCFG41) Horizontal Filter Phase Offset */
#define LCDC_HEOCFG41_XPHIDEF(value) ((LCDC_HEOCFG41_XPHIDEF_Msk & ((value) << LCDC_HEOCFG41_XPHIDEF_Pos)))
#define LCDC_HEOCFG41_YPHIDEF_Pos 16
#define LCDC_HEOCFG41_YPHIDEF_Msk (0x7u << LCDC_HEOCFG41_YPHIDEF_Pos) /**< \brief (LCDC_HEOCFG41) Vertical Filter Phase Offset */
#define LCDC_HEOCFG41_YPHIDEF(value) ((LCDC_HEOCFG41_YPHIDEF_Msk & ((value) << LCDC_HEOCFG41_YPHIDEF_Pos)))
/* -------- LCDC_HCRCHER : (LCDC Offset: 0x00000440) Hardware Cursor Channel Enable Register -------- */
#define LCDC_HCRCHER_CHEN (0x1u << 0) /**< \brief (LCDC_HCRCHER) Channel Enable Register */
#define LCDC_HCRCHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_HCRCHER) Update Overlay Attributes Enable Register */
#define LCDC_HCRCHER_A2QEN (0x1u << 2) /**< \brief (LCDC_HCRCHER) Add Head Pointer Enable Register */
/* -------- LCDC_HCRCHDR : (LCDC Offset: 0x00000444) Hardware Cursor Channel disable Register -------- */
#define LCDC_HCRCHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_HCRCHDR) Channel Disable Register */
#define LCDC_HCRCHDR_CHRST (0x1u << 8) /**< \brief (LCDC_HCRCHDR) Channel Reset Register */
/* -------- LCDC_HCRCHSR : (LCDC Offset: 0x00000448) Hardware Cursor Channel Status Register -------- */
#define LCDC_HCRCHSR_CHSR (0x1u << 0) /**< \brief (LCDC_HCRCHSR) Channel Status Register */
#define LCDC_HCRCHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_HCRCHSR) Update Overlay Attributes In Progress */
#define LCDC_HCRCHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_HCRCHSR) Add To Queue Pending Register */
/* -------- LCDC_HCRIER : (LCDC Offset: 0x0000044C) Hardware Cursor Interrupt Enable Register -------- */
#define LCDC_HCRIER_DMA (0x1u << 2) /**< \brief (LCDC_HCRIER) End of DMA Transfer Interrupt Enable Register */
#define LCDC_HCRIER_DSCR (0x1u << 3) /**< \brief (LCDC_HCRIER) Descriptor Loaded Interrupt Enable Register */
#define LCDC_HCRIER_ADD (0x1u << 4) /**< \brief (LCDC_HCRIER) Head Descriptor Loaded Interrupt Enable Register */
#define LCDC_HCRIER_DONE (0x1u << 5) /**< \brief (LCDC_HCRIER) End of List Interrupt Enable Register */
#define LCDC_HCRIER_OVR (0x1u << 6) /**< \brief (LCDC_HCRIER) Overflow Interrupt Enable Register */
/* -------- LCDC_HCRIDR : (LCDC Offset: 0x00000450) Hardware Cursor Interrupt Disable Register -------- */
#define LCDC_HCRIDR_DMA (0x1u << 2) /**< \brief (LCDC_HCRIDR) End of DMA Transfer Interrupt Disable Register */
#define LCDC_HCRIDR_DSCR (0x1u << 3) /**< \brief (LCDC_HCRIDR) Descriptor Loaded Interrupt Disable Register */
#define LCDC_HCRIDR_ADD (0x1u << 4) /**< \brief (LCDC_HCRIDR) Head Descriptor Loaded Interrupt Disable Register */
#define LCDC_HCRIDR_DONE (0x1u << 5) /**< \brief (LCDC_HCRIDR) End of List Interrupt Disable Register */
#define LCDC_HCRIDR_OVR (0x1u << 6) /**< \brief (LCDC_HCRIDR) Overflow Interrupt Disable Register */
/* -------- LCDC_HCRIMR : (LCDC Offset: 0x00000454) Hardware Cursor Interrupt Mask Register -------- */
#define LCDC_HCRIMR_DMA (0x1u << 2) /**< \brief (LCDC_HCRIMR) End of DMA Transfer Interrupt Mask Register */
#define LCDC_HCRIMR_DSCR (0x1u << 3) /**< \brief (LCDC_HCRIMR) Descriptor Loaded Interrupt Mask Register */
#define LCDC_HCRIMR_ADD (0x1u << 4) /**< \brief (LCDC_HCRIMR) Head Descriptor Loaded Interrupt Mask Register */
#define LCDC_HCRIMR_DONE (0x1u << 5) /**< \brief (LCDC_HCRIMR) End of List Interrupt Mask Register */
#define LCDC_HCRIMR_OVR (0x1u << 6) /**< \brief (LCDC_HCRIMR) Overflow Interrupt Mask Register */
/* -------- LCDC_HCRISR : (LCDC Offset: 0x00000458) Hardware Cursor Interrupt Status Register -------- */
#define LCDC_HCRISR_DMA (0x1u << 2) /**< \brief (LCDC_HCRISR) End of DMA Transfer */
#define LCDC_HCRISR_DSCR (0x1u << 3) /**< \brief (LCDC_HCRISR) DMA Descriptor Loaded */
#define LCDC_HCRISR_ADD (0x1u << 4) /**< \brief (LCDC_HCRISR) Head Descriptor Loaded */
#define LCDC_HCRISR_DONE (0x1u << 5) /**< \brief (LCDC_HCRISR) End of List Detected */
#define LCDC_HCRISR_OVR (0x1u << 6) /**< \brief (LCDC_HCRISR) Overflow Detected */
/* -------- LCDC_HCRHEAD : (LCDC Offset: 0x0000045C) Hardware Cursor DMA Head Register -------- */
#define LCDC_HCRHEAD_HEAD_Pos 2
#define LCDC_HCRHEAD_HEAD_Msk (0x3fffffffu << LCDC_HCRHEAD_HEAD_Pos) /**< \brief (LCDC_HCRHEAD) DMA Head Pointer */
#define LCDC_HCRHEAD_HEAD(value) ((LCDC_HCRHEAD_HEAD_Msk & ((value) << LCDC_HCRHEAD_HEAD_Pos)))
/* -------- LCDC_HCRADDR : (LCDC Offset: 0x00000460) Hardware cursor DMA Address Register -------- */
#define LCDC_HCRADDR_ADDR_Pos 0
#define LCDC_HCRADDR_ADDR_Msk (0xffffffffu << LCDC_HCRADDR_ADDR_Pos) /**< \brief (LCDC_HCRADDR) DMA Transfer start address */
#define LCDC_HCRADDR_ADDR(value) ((LCDC_HCRADDR_ADDR_Msk & ((value) << LCDC_HCRADDR_ADDR_Pos)))
/* -------- LCDC_HCRCTRL : (LCDC Offset: 0x00000464) Hardware Cursor DMA Control Register -------- */
#define LCDC_HCRCTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_HCRCTRL) Transfer Descriptor Fetch Enable */
#define LCDC_HCRCTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_HCRCTRL) Lookup Table Fetch Enable */
#define LCDC_HCRCTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_HCRCTRL) End of DMA Transfer Interrupt Enable */
#define LCDC_HCRCTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_HCRCTRL) Descriptor Loaded Interrupt Enable */
#define LCDC_HCRCTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_HCRCTRL) Add Head Descriptor to Queue Interrupt Enable */
#define LCDC_HCRCTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_HCRCTRL) End of List Interrupt Enable */
/* -------- LCDC_HCRNEXT : (LCDC Offset: 0x00000468) Hardware Cursor DMA NExt Register -------- */
#define LCDC_HCRNEXT_NEXT_Pos 0
#define LCDC_HCRNEXT_NEXT_Msk (0xffffffffu << LCDC_HCRNEXT_NEXT_Pos) /**< \brief (LCDC_HCRNEXT) DMA Descriptor Next Address */
#define LCDC_HCRNEXT_NEXT(value) ((LCDC_HCRNEXT_NEXT_Msk & ((value) << LCDC_HCRNEXT_NEXT_Pos)))
/* -------- LCDC_HCRCFG0 : (LCDC Offset: 0x0000046C) Hardware Cursor Configuration 0 Register -------- */
#define LCDC_HCRCFG0_SIF (0x1u << 0) /**< \brief (LCDC_HCRCFG0) Source Interface */
#define LCDC_HCRCFG0_BLEN_Pos 4
#define LCDC_HCRCFG0_BLEN_Msk (0x3u << LCDC_HCRCFG0_BLEN_Pos) /**< \brief (LCDC_HCRCFG0) AHB Burst Length */
#define   LCDC_HCRCFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_HCRCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_HCRCFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_HCRCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_HCRCFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_HCRCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_HCRCFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_HCRCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define LCDC_HCRCFG0_DLBO (0x1u << 8) /**< \brief (LCDC_HCRCFG0) Defined Length Burst Only for Channel Bus Transaction. */
/* -------- LCDC_HCRCFG1 : (LCDC Offset: 0x00000470) Hardware Cursor Configuration 1 Register -------- */
#define LCDC_HCRCFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_HCRCFG1) Color Lookup Table Enable */
#define LCDC_HCRCFG1_RGBMODE_Pos 4
#define LCDC_HCRCFG1_RGBMODE_Msk (0xfu << LCDC_HCRCFG1_RGBMODE_Pos) /**< \brief (LCDC_HCRCFG1) RGB input mode selection */
#define   LCDC_HCRCFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_HCRCFG1) 12 bpp RGB 444 */
#define   LCDC_HCRCFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_HCRCFG1) 16 bpp ARGB 4444 */
#define   LCDC_HCRCFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_HCRCFG1) 16 bpp RGBA 4444 */
#define   LCDC_HCRCFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_HCRCFG1) 16 bpp RGB 565 */
#define   LCDC_HCRCFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_HCRCFG1) 16 bpp TRGB 1555 */
#define   LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_HCRCFG1) 18 bpp RGB 666 */
#define   LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_HCRCFG1) 18 bpp RGB 666 PACKED */
#define   LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_HCRCFG1) 19 bpp TRGB 1666 */
#define   LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_HCRCFG1) 19 bpp TRGB 1666 PACKED */
#define   LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_HCRCFG1) 24 bpp RGB 888 */
#define   LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_HCRCFG1) 24 bpp RGB 888 PACKED */
#define   LCDC_HCRCFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_HCRCFG1) 25 bpp TRGB 1888 */
#define   LCDC_HCRCFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_HCRCFG1) 32 bpp ARGB 8888 */
#define   LCDC_HCRCFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_HCRCFG1) 32 bpp RGBA 8888 */
#define LCDC_HCRCFG1_CLUTMODE_Pos 8
#define LCDC_HCRCFG1_CLUTMODE_Msk (0x3u << LCDC_HCRCFG1_CLUTMODE_Pos) /**< \brief (LCDC_HCRCFG1) Color Lookup table input mode selection */
#define   LCDC_HCRCFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_HCRCFG1) color lookup table mode set to 1 bit per pixel */
#define   LCDC_HCRCFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_HCRCFG1) color lookup table mode set to 2 bits per pixel */
#define   LCDC_HCRCFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_HCRCFG1) color lookup table mode set to 4 bits per pixel */
#define   LCDC_HCRCFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_HCRCFG1) color lookup table mode set to 8 bits per pixel */
/* -------- LCDC_HCRCFG2 : (LCDC Offset: 0x00000474) Hardware Cursor Configuration 2 Register -------- */
#define LCDC_HCRCFG2_XPOS_Pos 0
#define LCDC_HCRCFG2_XPOS_Msk (0x7ffu << LCDC_HCRCFG2_XPOS_Pos) /**< \brief (LCDC_HCRCFG2) Horizontal Window Position */
#define LCDC_HCRCFG2_XPOS(value) ((LCDC_HCRCFG2_XPOS_Msk & ((value) << LCDC_HCRCFG2_XPOS_Pos)))
#define LCDC_HCRCFG2_YPOS_Pos 16
#define LCDC_HCRCFG2_YPOS_Msk (0x7ffu << LCDC_HCRCFG2_YPOS_Pos) /**< \brief (LCDC_HCRCFG2) Vertical Window Position */
#define LCDC_HCRCFG2_YPOS(value) ((LCDC_HCRCFG2_YPOS_Msk & ((value) << LCDC_HCRCFG2_YPOS_Pos)))
/* -------- LCDC_HCRCFG3 : (LCDC Offset: 0x00000478) Hardware Cursor Configuration 3 Register -------- */
#define LCDC_HCRCFG3_XSIZE_Pos 0
#define LCDC_HCRCFG3_XSIZE_Msk (0x7ffu << LCDC_HCRCFG3_XSIZE_Pos) /**< \brief (LCDC_HCRCFG3) Horizontal Window Size */
#define LCDC_HCRCFG3_XSIZE(value) ((LCDC_HCRCFG3_XSIZE_Msk & ((value) << LCDC_HCRCFG3_XSIZE_Pos)))
#define LCDC_HCRCFG3_YSIZE_Pos 16
#define LCDC_HCRCFG3_YSIZE_Msk (0x7ffu << LCDC_HCRCFG3_YSIZE_Pos) /**< \brief (LCDC_HCRCFG3) Vertical Window Size */
#define LCDC_HCRCFG3_YSIZE(value) ((LCDC_HCRCFG3_YSIZE_Msk & ((value) << LCDC_HCRCFG3_YSIZE_Pos)))
/* -------- LCDC_HCRCFG4 : (LCDC Offset: 0x0000047C) Hardware Cursor Configuration 4 Register -------- */
#define LCDC_HCRCFG4_XSTRIDE_Pos 0
#define LCDC_HCRCFG4_XSTRIDE_Msk (0xffffffffu << LCDC_HCRCFG4_XSTRIDE_Pos) /**< \brief (LCDC_HCRCFG4) Horizontal Stride */
#define LCDC_HCRCFG4_XSTRIDE(value) ((LCDC_HCRCFG4_XSTRIDE_Msk & ((value) << LCDC_HCRCFG4_XSTRIDE_Pos)))
/* -------- LCDC_HCRCFG6 : (LCDC Offset: 0x00000484) Hardware Cursor Configuration 6 Register -------- */
#define LCDC_HCRCFG6_BDEF_Pos 0
#define LCDC_HCRCFG6_BDEF_Msk (0xffu << LCDC_HCRCFG6_BDEF_Pos) /**< \brief (LCDC_HCRCFG6) Blue Default */
#define LCDC_HCRCFG6_BDEF(value) ((LCDC_HCRCFG6_BDEF_Msk & ((value) << LCDC_HCRCFG6_BDEF_Pos)))
#define LCDC_HCRCFG6_GDEF_Pos 8
#define LCDC_HCRCFG6_GDEF_Msk (0xffu << LCDC_HCRCFG6_GDEF_Pos) /**< \brief (LCDC_HCRCFG6) Green Default */
#define LCDC_HCRCFG6_GDEF(value) ((LCDC_HCRCFG6_GDEF_Msk & ((value) << LCDC_HCRCFG6_GDEF_Pos)))
#define LCDC_HCRCFG6_RDEF_Pos 16
#define LCDC_HCRCFG6_RDEF_Msk (0xffu << LCDC_HCRCFG6_RDEF_Pos) /**< \brief (LCDC_HCRCFG6) Red Default */
#define LCDC_HCRCFG6_RDEF(value) ((LCDC_HCRCFG6_RDEF_Msk & ((value) << LCDC_HCRCFG6_RDEF_Pos)))
/* -------- LCDC_HCRCFG7 : (LCDC Offset: 0x00000488) Hardware Cursor Configuration 7 Register -------- */
#define LCDC_HCRCFG7_BKEY_Pos 0
#define LCDC_HCRCFG7_BKEY_Msk (0xffu << LCDC_HCRCFG7_BKEY_Pos) /**< \brief (LCDC_HCRCFG7) Blue Color Component Chroma Key */
#define LCDC_HCRCFG7_BKEY(value) ((LCDC_HCRCFG7_BKEY_Msk & ((value) << LCDC_HCRCFG7_BKEY_Pos)))
#define LCDC_HCRCFG7_GKEY_Pos 8
#define LCDC_HCRCFG7_GKEY_Msk (0xffu << LCDC_HCRCFG7_GKEY_Pos) /**< \brief (LCDC_HCRCFG7) Green Color Component Chroma Key */
#define LCDC_HCRCFG7_GKEY(value) ((LCDC_HCRCFG7_GKEY_Msk & ((value) << LCDC_HCRCFG7_GKEY_Pos)))
#define LCDC_HCRCFG7_RKEY_Pos 16
#define LCDC_HCRCFG7_RKEY_Msk (0xffu << LCDC_HCRCFG7_RKEY_Pos) /**< \brief (LCDC_HCRCFG7) Red Color Component Chroma Key */
#define LCDC_HCRCFG7_RKEY(value) ((LCDC_HCRCFG7_RKEY_Msk & ((value) << LCDC_HCRCFG7_RKEY_Pos)))
/* -------- LCDC_HCRCFG8 : (LCDC Offset: 0x0000048C) Hardware Cursor Configuration 8 Register -------- */
#define LCDC_HCRCFG8_BMASK_Pos 0
#define LCDC_HCRCFG8_BMASK_Msk (0xffu << LCDC_HCRCFG8_BMASK_Pos) /**< \brief (LCDC_HCRCFG8) Blue Color Component Chroma Key Mask */
#define LCDC_HCRCFG8_BMASK(value) ((LCDC_HCRCFG8_BMASK_Msk & ((value) << LCDC_HCRCFG8_BMASK_Pos)))
#define LCDC_HCRCFG8_GMASK_Pos 8
#define LCDC_HCRCFG8_GMASK_Msk (0xffu << LCDC_HCRCFG8_GMASK_Pos) /**< \brief (LCDC_HCRCFG8) Green Color Component Chroma Key Mask */
#define LCDC_HCRCFG8_GMASK(value) ((LCDC_HCRCFG8_GMASK_Msk & ((value) << LCDC_HCRCFG8_GMASK_Pos)))
#define LCDC_HCRCFG8_RMASK_Pos 16
#define LCDC_HCRCFG8_RMASK_Msk (0xffu << LCDC_HCRCFG8_RMASK_Pos) /**< \brief (LCDC_HCRCFG8) Red Color Component Chroma Key Mask */
#define LCDC_HCRCFG8_RMASK(value) ((LCDC_HCRCFG8_RMASK_Msk & ((value) << LCDC_HCRCFG8_RMASK_Pos)))
/* -------- LCDC_HCRCFG9 : (LCDC Offset: 0x00000490) Hardware Cursor Configuration 9 Register -------- */
#define LCDC_HCRCFG9_CRKEY (0x1u << 0) /**< \brief (LCDC_HCRCFG9) Blender Chroma Key Enable */
#define LCDC_HCRCFG9_INV (0x1u << 1) /**< \brief (LCDC_HCRCFG9) Blender Inverted Blender Output Enable */
#define LCDC_HCRCFG9_ITER2BL (0x1u << 2) /**< \brief (LCDC_HCRCFG9) Blender Iterated Color Enable */
#define LCDC_HCRCFG9_ITER (0x1u << 3) /**< \brief (LCDC_HCRCFG9) Blender Use Iterated Color */
#define LCDC_HCRCFG9_REVALPHA (0x1u << 4) /**< \brief (LCDC_HCRCFG9) Blender Reverse Alpha */
#define LCDC_HCRCFG9_GAEN (0x1u << 5) /**< \brief (LCDC_HCRCFG9) Blender Global Alpha Enable */
#define LCDC_HCRCFG9_LAEN (0x1u << 6) /**< \brief (LCDC_HCRCFG9) Blender Local Alpha Enable */
#define LCDC_HCRCFG9_OVR (0x1u << 7) /**< \brief (LCDC_HCRCFG9) Blender Overlay Layer Enable */
#define LCDC_HCRCFG9_DMA (0x1u << 8) /**< \brief (LCDC_HCRCFG9) Blender DMA Layer Enable */
#define LCDC_HCRCFG9_REP (0x1u << 9) /**< \brief (LCDC_HCRCFG9) Use Replication logic to expand RGB color to 24 bits */
#define LCDC_HCRCFG9_DSTKEY (0x1u << 10) /**< \brief (LCDC_HCRCFG9) Destination Chroma Keying */
#define LCDC_HCRCFG9_GA_Pos 16
#define LCDC_HCRCFG9_GA_Msk (0xffu << LCDC_HCRCFG9_GA_Pos) /**< \brief (LCDC_HCRCFG9) Blender Global Alpha */
#define LCDC_HCRCFG9_GA(value) ((LCDC_HCRCFG9_GA_Msk & ((value) << LCDC_HCRCFG9_GA_Pos)))
/* -------- LCDC_PPCHER : (LCDC Offset: 0x00000540) Post Processing Channel Enable Register -------- */
#define LCDC_PPCHER_CHEN (0x1u << 0) /**< \brief (LCDC_PPCHER) Channel Enable Register */
#define LCDC_PPCHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_PPCHER) Update Overlay Attributes Enable Register */
#define LCDC_PPCHER_A2QEN (0x1u << 2) /**< \brief (LCDC_PPCHER) Add Head Pointer Enable Register */
/* -------- LCDC_PPCHDR : (LCDC Offset: 0x00000544) Post Processing Channel Disable Register -------- */
#define LCDC_PPCHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_PPCHDR) Channel Disable Register */
#define LCDC_PPCHDR_CHRST (0x1u << 8) /**< \brief (LCDC_PPCHDR) Channel Reset Register */
/* -------- LCDC_PPCHSR : (LCDC Offset: 0x00000548) Post Processing Channel Status Register -------- */
#define LCDC_PPCHSR_CHSR (0x1u << 0) /**< \brief (LCDC_PPCHSR) Channel Status Register */
#define LCDC_PPCHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_PPCHSR) Update Overlay Attributes In Progress */
#define LCDC_PPCHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_PPCHSR) Add To Queue Pending Register */
/* -------- LCDC_PPIER : (LCDC Offset: 0x0000054C) Post Processing Interrupt Enable Register -------- */
#define LCDC_PPIER_DMA (0x1u << 2) /**< \brief (LCDC_PPIER) End of DMA Transfer Interrupt Enable Register */
#define LCDC_PPIER_DSCR (0x1u << 3) /**< \brief (LCDC_PPIER) Descriptor Loaded Interrupt Enable Register */
#define LCDC_PPIER_ADD (0x1u << 4) /**< \brief (LCDC_PPIER) Head Descriptor Loaded Interrupt Enable Register */
#define LCDC_PPIER_DONE (0x1u << 5) /**< \brief (LCDC_PPIER) End of List Interrupt Enable Register */
/* -------- LCDC_PPIDR : (LCDC Offset: 0x00000550) Post Processing Interrupt Disable Register -------- */
#define LCDC_PPIDR_DMA (0x1u << 2) /**< \brief (LCDC_PPIDR) End of DMA Transfer Interrupt Disable Register */
#define LCDC_PPIDR_DSCR (0x1u << 3) /**< \brief (LCDC_PPIDR) Descriptor Loaded Interrupt Disable Register */
#define LCDC_PPIDR_ADD (0x1u << 4) /**< \brief (LCDC_PPIDR) Head Descriptor Loaded Interrupt Disable Register */
#define LCDC_PPIDR_DONE (0x1u << 5) /**< \brief (LCDC_PPIDR) End of List Interrupt Disable Register */
/* -------- LCDC_PPIMR : (LCDC Offset: 0x00000554) Post Processing Interrupt Mask Register -------- */
#define LCDC_PPIMR_DMA (0x1u << 2) /**< \brief (LCDC_PPIMR) End of DMA Transfer Interrupt Mask Register */
#define LCDC_PPIMR_DSCR (0x1u << 3) /**< \brief (LCDC_PPIMR) Descriptor Loaded Interrupt Mask Register */
#define LCDC_PPIMR_ADD (0x1u << 4) /**< \brief (LCDC_PPIMR) Head Descriptor Loaded Interrupt Mask Register */
#define LCDC_PPIMR_DONE (0x1u << 5) /**< \brief (LCDC_PPIMR) End of List Interrupt Mask Register */
/* -------- LCDC_PPISR : (LCDC Offset: 0x00000558) Post Processing Interrupt Status Register -------- */
#define LCDC_PPISR_DMA (0x1u << 2) /**< \brief (LCDC_PPISR) End of DMA Transfer */
#define LCDC_PPISR_DSCR (0x1u << 3) /**< \brief (LCDC_PPISR) DMA Descriptor Loaded */
#define LCDC_PPISR_ADD (0x1u << 4) /**< \brief (LCDC_PPISR) Head Descriptor Loaded */
#define LCDC_PPISR_DONE (0x1u << 5) /**< \brief (LCDC_PPISR) End Of List Detected */
/* -------- LCDC_PPHEAD : (LCDC Offset: 0x0000055C) Post Processing Head Register -------- */
#define LCDC_PPHEAD_HEAD_Pos 2
#define LCDC_PPHEAD_HEAD_Msk (0x3fffffffu << LCDC_PPHEAD_HEAD_Pos) /**< \brief (LCDC_PPHEAD) DMA Head Pointer */
#define LCDC_PPHEAD_HEAD(value) ((LCDC_PPHEAD_HEAD_Msk & ((value) << LCDC_PPHEAD_HEAD_Pos)))
/* -------- LCDC_PPADDR : (LCDC Offset: 0x00000560) Post Processing Address Register -------- */
#define LCDC_PPADDR_ADDR_Pos 0
#define LCDC_PPADDR_ADDR_Msk (0xffffffffu << LCDC_PPADDR_ADDR_Pos) /**< \brief (LCDC_PPADDR) DMA Transfer start address */
#define LCDC_PPADDR_ADDR(value) ((LCDC_PPADDR_ADDR_Msk & ((value) << LCDC_PPADDR_ADDR_Pos)))
/* -------- LCDC_PPCTRL : (LCDC Offset: 0x00000564) Post Processing Control Register -------- */
#define LCDC_PPCTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_PPCTRL) Transfer Descriptor Fetch Enable */
#define LCDC_PPCTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_PPCTRL) End of DMA Transfer Interrupt Enable */
#define LCDC_PPCTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_PPCTRL) Descriptor Loaded Interrupt Enable */
#define LCDC_PPCTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_PPCTRL) Add Head Descriptor to Queue Interrupt Enable */
#define LCDC_PPCTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_PPCTRL) End of List Interrupt Enable */
/* -------- LCDC_PPNEXT : (LCDC Offset: 0x00000568) Post Processing Next Register -------- */
#define LCDC_PPNEXT_NEXT_Pos 0
#define LCDC_PPNEXT_NEXT_Msk (0xffffffffu << LCDC_PPNEXT_NEXT_Pos) /**< \brief (LCDC_PPNEXT) DMA Descriptor Next Address */
#define LCDC_PPNEXT_NEXT(value) ((LCDC_PPNEXT_NEXT_Msk & ((value) << LCDC_PPNEXT_NEXT_Pos)))
/* -------- LCDC_PPCFG0 : (LCDC Offset: 0x0000056C) Post Processing Configuration Register 0 -------- */
#define LCDC_PPCFG0_SIF (0x1u << 0) /**< \brief (LCDC_PPCFG0) Source Interface */
#define LCDC_PPCFG0_BLEN_Pos 4
#define LCDC_PPCFG0_BLEN_Msk (0x3u << LCDC_PPCFG0_BLEN_Pos) /**< \brief (LCDC_PPCFG0) AHB Burst Length */
#define   LCDC_PPCFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_PPCFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_PPCFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define   LCDC_PPCFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
#define LCDC_PPCFG0_DLBO (0x1u << 8) /**< \brief (LCDC_PPCFG0) Defined Length Burst Only For Channel Bus Transaction. */
/* -------- LCDC_PPCFG1 : (LCDC Offset: 0x00000570) Post Processing Configuration Register 1 -------- */
#define LCDC_PPCFG1_PPMODE_Pos 0
#define LCDC_PPCFG1_PPMODE_Msk (0x7u << LCDC_PPCFG1_PPMODE_Pos) /**< \brief (LCDC_PPCFG1) Post Processing Output Format selection */
#define   LCDC_PPCFG1_PPMODE_PPMODE_RGB_16BPP (0x0u << 0) /**< \brief (LCDC_PPCFG1) RGB 16 bpp */
#define   LCDC_PPCFG1_PPMODE_PPMODE_RGB_24BPP_PACKED (0x1u << 0) /**< \brief (LCDC_PPCFG1) RGB 24 bpp PACKED */
#define   LCDC_PPCFG1_PPMODE_PPMODE_RGB_24BPP_UNPACKED (0x2u << 0) /**< \brief (LCDC_PPCFG1) RGB 24 bpp UNPACKED */
#define   LCDC_PPCFG1_PPMODE_PPMODE_YCbCr_422_MODE0 (0x3u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 0) */
#define   LCDC_PPCFG1_PPMODE_PPMODE_YCbCr_422_MODE1 (0x4u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 1) */
#define   LCDC_PPCFG1_PPMODE_PPMODE_YCbCr_422_MODE2 (0x5u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 2) */
#define   LCDC_PPCFG1_PPMODE_PPMODE_YCbCr_422_MODE3 (0x6u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 3) */
#define LCDC_PPCFG1_ITUBT601 (0x1u << 4) /**< \brief (LCDC_PPCFG1) Color Space Conversion Luminance */
/* -------- LCDC_PPCFG2 : (LCDC Offset: 0x00000574) Post Processing Configuration Register 2 -------- */
#define LCDC_PPCFG2_XSTRIDE_Pos 0
#define LCDC_PPCFG2_XSTRIDE_Msk (0xffffffffu << LCDC_PPCFG2_XSTRIDE_Pos) /**< \brief (LCDC_PPCFG2) Horizontal Stride */
#define LCDC_PPCFG2_XSTRIDE(value) ((LCDC_PPCFG2_XSTRIDE_Msk & ((value) << LCDC_PPCFG2_XSTRIDE_Pos)))
/* -------- LCDC_PPCFG3 : (LCDC Offset: 0x00000578) Post Processing Configuration Register 3 -------- */
#define LCDC_PPCFG3_CSCYR_Pos 0
#define LCDC_PPCFG3_CSCYR_Msk (0x3ffu << LCDC_PPCFG3_CSCYR_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion R coefficient for Luminance component, signed format, step set to 1/1024 */
#define LCDC_PPCFG3_CSCYR(value) ((LCDC_PPCFG3_CSCYR_Msk & ((value) << LCDC_PPCFG3_CSCYR_Pos)))
#define LCDC_PPCFG3_CSCYG_Pos 10
#define LCDC_PPCFG3_CSCYG_Msk (0x3ffu << LCDC_PPCFG3_CSCYG_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion G coefficient for Luminance component, signed format, step set to 1/512 */
#define LCDC_PPCFG3_CSCYG(value) ((LCDC_PPCFG3_CSCYG_Msk & ((value) << LCDC_PPCFG3_CSCYG_Pos)))
#define LCDC_PPCFG3_CSCYB_Pos 20
#define LCDC_PPCFG3_CSCYB_Msk (0x3ffu << LCDC_PPCFG3_CSCYB_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion B coefficient for Luminance component, signed format, step set to 1/1024 */
#define LCDC_PPCFG3_CSCYB(value) ((LCDC_PPCFG3_CSCYB_Msk & ((value) << LCDC_PPCFG3_CSCYB_Pos)))
#define LCDC_PPCFG3_CSCYOFF (0x1u << 30) /**< \brief (LCDC_PPCFG3) Color Space Conversion Luminance Offset */
/* -------- LCDC_PPCFG4 : (LCDC Offset: 0x0000057C) Post Processing Configuration Register 4 -------- */
#define LCDC_PPCFG4_CSCUR_Pos 0
#define LCDC_PPCFG4_CSCUR_Msk (0x3ffu << LCDC_PPCFG4_CSCUR_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion R coefficient for Chrominance B component, signed format. (step 1/1024) */
#define LCDC_PPCFG4_CSCUR(value) ((LCDC_PPCFG4_CSCUR_Msk & ((value) << LCDC_PPCFG4_CSCUR_Pos)))
#define LCDC_PPCFG4_CSCUG_Pos 10
#define LCDC_PPCFG4_CSCUG_Msk (0x3ffu << LCDC_PPCFG4_CSCUG_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion G coefficient for Chrominance B component, signed format. (step 1/512) */
#define LCDC_PPCFG4_CSCUG(value) ((LCDC_PPCFG4_CSCUG_Msk & ((value) << LCDC_PPCFG4_CSCUG_Pos)))
#define LCDC_PPCFG4_CSCUB_Pos 20
#define LCDC_PPCFG4_CSCUB_Msk (0x3ffu << LCDC_PPCFG4_CSCUB_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion B coefficient for Chrominance B component, signed format. (step 1/512) */
#define LCDC_PPCFG4_CSCUB(value) ((LCDC_PPCFG4_CSCUB_Msk & ((value) << LCDC_PPCFG4_CSCUB_Pos)))
#define LCDC_PPCFG4_CSCUOFF (0x1u << 30) /**< \brief (LCDC_PPCFG4) Color Space Conversion Chrominance B Offset */
/* -------- LCDC_PPCFG5 : (LCDC Offset: 0x00000580) Post Processing Configuration Register 5 -------- */
#define LCDC_PPCFG5_CSCVR_Pos 0
#define LCDC_PPCFG5_CSCVR_Msk (0x3ffu << LCDC_PPCFG5_CSCVR_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion R coefficient for Chrominance R component, signed format. (step 1/1024) */
#define LCDC_PPCFG5_CSCVR(value) ((LCDC_PPCFG5_CSCVR_Msk & ((value) << LCDC_PPCFG5_CSCVR_Pos)))
#define LCDC_PPCFG5_CSCVG_Pos 10
#define LCDC_PPCFG5_CSCVG_Msk (0x3ffu << LCDC_PPCFG5_CSCVG_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion G coefficient for Chrominance R component, signed format. (step 1/512) */
#define LCDC_PPCFG5_CSCVG(value) ((LCDC_PPCFG5_CSCVG_Msk & ((value) << LCDC_PPCFG5_CSCVG_Pos)))
#define LCDC_PPCFG5_CSCVB_Pos 20
#define LCDC_PPCFG5_CSCVB_Msk (0x3ffu << LCDC_PPCFG5_CSCVB_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion B coefficient for Chrominance R component, signed format. (step 1/1024) */
#define LCDC_PPCFG5_CSCVB(value) ((LCDC_PPCFG5_CSCVB_Msk & ((value) << LCDC_PPCFG5_CSCVB_Pos)))
#define LCDC_PPCFG5_CSCVOFF (0x1u << 30) /**< \brief (LCDC_PPCFG5) Color Space Conversion Chrominance R Offset */
/* -------- LCDC_BASECLUT[256] : (LCDC Offset: 0x600) Base CLUT Register -------- */
#define LCDC_BASECLUT_BCLUT_Pos 0
#define LCDC_BASECLUT_BCLUT_Msk (0xffu << LCDC_BASECLUT_BCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Blue Color entry */
#define LCDC_BASECLUT_BCLUT(value) ((LCDC_BASECLUT_BCLUT_Msk & ((value) << LCDC_BASECLUT_BCLUT_Pos)))
#define LCDC_BASECLUT_GCLUT_Pos 8
#define LCDC_BASECLUT_GCLUT_Msk (0xffu << LCDC_BASECLUT_GCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Green Color entry */
#define LCDC_BASECLUT_GCLUT(value) ((LCDC_BASECLUT_GCLUT_Msk & ((value) << LCDC_BASECLUT_GCLUT_Pos)))
#define LCDC_BASECLUT_RCLUT_Pos 16
#define LCDC_BASECLUT_RCLUT_Msk (0xffu << LCDC_BASECLUT_RCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Red Color entry */
#define LCDC_BASECLUT_RCLUT(value) ((LCDC_BASECLUT_RCLUT_Msk & ((value) << LCDC_BASECLUT_RCLUT_Pos)))
/* -------- LCDC_OVR1CLUT[256] : (LCDC Offset: 0xA00) Overlay 1 CLUT Register -------- */
#define LCDC_OVR1CLUT_BCLUT_Pos 0
#define LCDC_OVR1CLUT_BCLUT_Msk (0xffu << LCDC_OVR1CLUT_BCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Blue Color entry */
#define LCDC_OVR1CLUT_BCLUT(value) ((LCDC_OVR1CLUT_BCLUT_Msk & ((value) << LCDC_OVR1CLUT_BCLUT_Pos)))
#define LCDC_OVR1CLUT_GCLUT_Pos 8
#define LCDC_OVR1CLUT_GCLUT_Msk (0xffu << LCDC_OVR1CLUT_GCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Green Color entry */
#define LCDC_OVR1CLUT_GCLUT(value) ((LCDC_OVR1CLUT_GCLUT_Msk & ((value) << LCDC_OVR1CLUT_GCLUT_Pos)))
#define LCDC_OVR1CLUT_RCLUT_Pos 16
#define LCDC_OVR1CLUT_RCLUT_Msk (0xffu << LCDC_OVR1CLUT_RCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Red Color entry */
#define LCDC_OVR1CLUT_RCLUT(value) ((LCDC_OVR1CLUT_RCLUT_Msk & ((value) << LCDC_OVR1CLUT_RCLUT_Pos)))
#define LCDC_OVR1CLUT_ACLUT_Pos 24
#define LCDC_OVR1CLUT_ACLUT_Msk (0xffu << LCDC_OVR1CLUT_ACLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Alpha Color entry */
#define LCDC_OVR1CLUT_ACLUT(value) ((LCDC_OVR1CLUT_ACLUT_Msk & ((value) << LCDC_OVR1CLUT_ACLUT_Pos)))
/* -------- LCDC_OVR2CLUT[256] : (LCDC Offset: 0xE00) Overlay 2 CLUT Register -------- */
#define LCDC_OVR2CLUT_BCLUT_Pos 0
#define LCDC_OVR2CLUT_BCLUT_Msk (0xffu << LCDC_OVR2CLUT_BCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Blue Color entry */
#define LCDC_OVR2CLUT_BCLUT(value) ((LCDC_OVR2CLUT_BCLUT_Msk & ((value) << LCDC_OVR2CLUT_BCLUT_Pos)))
#define LCDC_OVR2CLUT_GCLUT_Pos 8
#define LCDC_OVR2CLUT_GCLUT_Msk (0xffu << LCDC_OVR2CLUT_GCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Green Color entry */
#define LCDC_OVR2CLUT_GCLUT(value) ((LCDC_OVR2CLUT_GCLUT_Msk & ((value) << LCDC_OVR2CLUT_GCLUT_Pos)))
#define LCDC_OVR2CLUT_RCLUT_Pos 16
#define LCDC_OVR2CLUT_RCLUT_Msk (0xffu << LCDC_OVR2CLUT_RCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Red Color entry */
#define LCDC_OVR2CLUT_RCLUT(value) ((LCDC_OVR2CLUT_RCLUT_Msk & ((value) << LCDC_OVR2CLUT_RCLUT_Pos)))
#define LCDC_OVR2CLUT_ACLUT_Pos 24
#define LCDC_OVR2CLUT_ACLUT_Msk (0xffu << LCDC_OVR2CLUT_ACLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Alpha Color entry */
#define LCDC_OVR2CLUT_ACLUT(value) ((LCDC_OVR2CLUT_ACLUT_Msk & ((value) << LCDC_OVR2CLUT_ACLUT_Pos)))
/* -------- LCDC_HEOCLUT[256] : (LCDC Offset: 0x1200) High End Overlay CLUT Register -------- */
#define LCDC_HEOCLUT_BCLUT_Pos 0
#define LCDC_HEOCLUT_BCLUT_Msk (0xffu << LCDC_HEOCLUT_BCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Blue Color entry */
#define LCDC_HEOCLUT_BCLUT(value) ((LCDC_HEOCLUT_BCLUT_Msk & ((value) << LCDC_HEOCLUT_BCLUT_Pos)))
#define LCDC_HEOCLUT_GCLUT_Pos 8
#define LCDC_HEOCLUT_GCLUT_Msk (0xffu << LCDC_HEOCLUT_GCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Green Color entry */
#define LCDC_HEOCLUT_GCLUT(value) ((LCDC_HEOCLUT_GCLUT_Msk & ((value) << LCDC_HEOCLUT_GCLUT_Pos)))
#define LCDC_HEOCLUT_RCLUT_Pos 16
#define LCDC_HEOCLUT_RCLUT_Msk (0xffu << LCDC_HEOCLUT_RCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Red Color entry */
#define LCDC_HEOCLUT_RCLUT(value) ((LCDC_HEOCLUT_RCLUT_Msk & ((value) << LCDC_HEOCLUT_RCLUT_Pos)))
#define LCDC_HEOCLUT_ACLUT_Pos 24
#define LCDC_HEOCLUT_ACLUT_Msk (0xffu << LCDC_HEOCLUT_ACLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Alpha Color entry */
#define LCDC_HEOCLUT_ACLUT(value) ((LCDC_HEOCLUT_ACLUT_Msk & ((value) << LCDC_HEOCLUT_ACLUT_Pos)))
/* -------- LCDC_HCRCLUT[256] : (LCDC Offset: 0x1600) Hardware Cursor CLUT Register -------- */
#define LCDC_HCRCLUT_BCLUT_Pos 0
#define LCDC_HCRCLUT_BCLUT_Msk (0xffu << LCDC_HCRCLUT_BCLUT_Pos) /**< \brief (LCDC_HCRCLUT[256]) Blue Color entry */
#define LCDC_HCRCLUT_BCLUT(value) ((LCDC_HCRCLUT_BCLUT_Msk & ((value) << LCDC_HCRCLUT_BCLUT_Pos)))
#define LCDC_HCRCLUT_GCLUT_Pos 8
#define LCDC_HCRCLUT_GCLUT_Msk (0xffu << LCDC_HCRCLUT_GCLUT_Pos) /**< \brief (LCDC_HCRCLUT[256]) Green Color entry */
#define LCDC_HCRCLUT_GCLUT(value) ((LCDC_HCRCLUT_GCLUT_Msk & ((value) << LCDC_HCRCLUT_GCLUT_Pos)))
#define LCDC_HCRCLUT_RCLUT_Pos 16
#define LCDC_HCRCLUT_RCLUT_Msk (0xffu << LCDC_HCRCLUT_RCLUT_Pos) /**< \brief (LCDC_HCRCLUT[256]) Red Color entry */
#define LCDC_HCRCLUT_RCLUT(value) ((LCDC_HCRCLUT_RCLUT_Msk & ((value) << LCDC_HCRCLUT_RCLUT_Pos)))
#define LCDC_HCRCLUT_ACLUT_Pos 24
#define LCDC_HCRCLUT_ACLUT_Msk (0xffu << LCDC_HCRCLUT_ACLUT_Pos) /**< \brief (LCDC_HCRCLUT[256]) Alpha Color entry */
#define LCDC_HCRCLUT_ACLUT(value) ((LCDC_HCRCLUT_ACLUT_Msk & ((value) << LCDC_HCRCLUT_ACLUT_Pos)))

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_MATRIX AHB Bus Matrix */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief MatrixPr hardware registers */
typedef struct {
  RwReg     MATRIX_PRAS;     /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */
  RwReg     MATRIX_PRBS;     /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */
} MatrixPr;
/** \brief Matrix hardware registers */
#define MATRIXPR_NUMBER 16
typedef struct {
  RwReg     MATRIX_MCFG[16]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
  RwReg     MATRIX_SCFG[16]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
  MatrixPr  MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 15 */
  RwReg     MATRIX_MRCR;     /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
  RoReg     Reserved1[3];
  RwReg     MATRIX_SFR[16];  /**< \brief (Matrix Offset: 0x0110) Special Function Register */
  RoReg     Reserved2[37];
  RwReg     MATRIX_WPMR;     /**< \brief (Matrix Offset: 0x01E4) Write Protect Mode Register */
  RoReg     MATRIX_WPSR;     /**< \brief (Matrix Offset: 0x01E8) Write Protect Status Register */
} Matrix;
#endif /* __ASSEMBLY__ */
/* -------- MATRIX_MCFG[16] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
#define MATRIX_MCFG_ULBT_Pos 0
#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[16]) Undefined Length Burst Type */
#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
/* -------- MATRIX_SCFG[16] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[16]) Maximum Bus Grant Duration for Masters */
#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[16]) Default Master Type */
#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[16]) Fixed Default Master */
#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */
#define MATRIX_PRAS_M0PR_Pos 0
#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */
#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)))
#define MATRIX_PRAS_M1PR_Pos 4
#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */
#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)))
#define MATRIX_PRAS_M2PR_Pos 8
#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */
#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)))
#define MATRIX_PRAS_M3PR_Pos 12
#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */
#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)))
#define MATRIX_PRAS_M4PR_Pos 16
#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */
#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)))
#define MATRIX_PRAS_M5PR_Pos 20
#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */
#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)))
#define MATRIX_PRAS_M6PR_Pos 24
#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */
#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)))
#define MATRIX_PRAS_M7PR_Pos 28
#define MATRIX_PRAS_M7PR_Msk (0x3u << MATRIX_PRAS_M7PR_Pos) /**< \brief (MATRIX_PRAS) Master 7 Priority */
#define MATRIX_PRAS_M7PR(value) ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos)))
/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */
#define MATRIX_PRBS_M8PR_Pos 0
#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */
#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)))
#define MATRIX_PRBS_M9PR_Pos 4
#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */
#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)))
#define MATRIX_PRBS_M10PR_Pos 8
#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */
#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)))
#define MATRIX_PRBS_M11PR_Pos 12
#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */
#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)))
#define MATRIX_PRBS_M12PR_Pos 16
#define MATRIX_PRBS_M12PR_Msk (0x3u << MATRIX_PRBS_M12PR_Pos) /**< \brief (MATRIX_PRBS) Master 12 Priority */
#define MATRIX_PRBS_M12PR(value) ((MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos)))
#define MATRIX_PRBS_M13PR_Pos 20
#define MATRIX_PRBS_M13PR_Msk (0x3u << MATRIX_PRBS_M13PR_Pos) /**< \brief (MATRIX_PRBS) Master 13 Priority */
#define MATRIX_PRBS_M13PR(value) ((MATRIX_PRBS_M13PR_Msk & ((value) << MATRIX_PRBS_M13PR_Pos)))
#define MATRIX_PRBS_M14PR_Pos 24
#define MATRIX_PRBS_M14PR_Msk (0x3u << MATRIX_PRBS_M14PR_Pos) /**< \brief (MATRIX_PRBS) Master 14 Priority */
#define MATRIX_PRBS_M14PR(value) ((MATRIX_PRBS_M14PR_Msk & ((value) << MATRIX_PRBS_M14PR_Pos)))
#define MATRIX_PRBS_M15PR_Pos 28
#define MATRIX_PRBS_M15PR_Msk (0x3u << MATRIX_PRBS_M15PR_Pos) /**< \brief (MATRIX_PRBS) Master 15 Priority */
#define MATRIX_PRBS_M15PR(value) ((MATRIX_PRBS_M15PR_Msk & ((value) << MATRIX_PRBS_M15PR_Pos)))
/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB7 (0x1u << 7) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB12 (0x1u << 12) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB13 (0x1u << 13) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB14 (0x1u << 14) /**< \brief (MATRIX_MRCR)  */
#define MATRIX_MRCR_RCB15 (0x1u << 15) /**< \brief (MATRIX_MRCR)  */
/* -------- MATRIX_SFR[16] : (MATRIX Offset: 0x0110) Special Function Register -------- */
#define MATRIX_SFR_SFR_Pos 0
#define MATRIX_SFR_SFR_Msk (0xffffffffu << MATRIX_SFR_SFR_Pos) /**< \brief (MATRIX_SFR[16]) Special Function Register Fields */
#define MATRIX_SFR_SFR(value) ((MATRIX_SFR_SFR_Msk & ((value) << MATRIX_SFR_SFR_Pos)))
/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protect Mode Register -------- */
#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect Enable */
#define MATRIX_WPMR_WPKEY_Pos 8
#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protect Status Register -------- */
#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
#define MATRIX_WPSR_WPVSRC_Pos 8
#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR AHB Multi-port DDR-SDRAM Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_MPDDRC AHB Multi-port DDR-SDRAM Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Mpddrc hardware registers */
typedef struct {
  RwReg MPDDRC_MR;             /**< \brief (Mpddrc Offset: 0x00) MPDDRC Mode Register */
  RwReg MPDDRC_RTR;            /**< \brief (Mpddrc Offset: 0x04) MPDDRC Refresh Timer Register */
  RwReg MPDDRC_CR;             /**< \brief (Mpddrc Offset: 0x08) MPDDRC Configuration Register */
  RwReg MPDDRC_TPR0;           /**< \brief (Mpddrc Offset: 0x0C) MPDDRC Timing Parameter 0 Register */
  RwReg MPDDRC_TPR1;           /**< \brief (Mpddrc Offset: 0x10) MPDDRC Timing Parameter 1 Register */
  RwReg MPDDRC_TPR2;           /**< \brief (Mpddrc Offset: 0x14) MPDDRC Timing Parameter 2 Register */
  RoReg Reserved1[1];
  RwReg MPDDRC_LPR;            /**< \brief (Mpddrc Offset: 0x1C) MPDDRC Low-power Register */
  RwReg MPDDRC_MD;             /**< \brief (Mpddrc Offset: 0x20) MPDDRC Memory Device Register */
  RoReg Reserved2[1];
  RwReg MPDDRC_LPDDR2_LPR;     /**< \brief (Mpddrc Offset: 0x28) MPDDRC LPDDR2 Low-power Register */
  RwReg MPDDRC_LPDDR2_CAL_MR4; /**< \brief (Mpddrc Offset: 0x2C) MPDDRC LPDDR2 Calibration and MR4 Register */
  RwReg MPDDRC_LPDDR2_TIM_CAL; /**< \brief (Mpddrc Offset: 0x30) MPDDRC LPDDR2 Timing Calibration Register */
  RwReg MPDDRC_IO_CALIBR;      /**< \brief (Mpddrc Offset: 0x34) MPDDRC IO Calibration */
  RwReg MPDDRC_OCMS;           /**< \brief (Mpddrc Offset: 0x38) MPDDRC OCMS Register */
  WoReg MPDDRC_OCMS_KEY1;      /**< \brief (Mpddrc Offset: 0x3C) MPDDRC OCMS KEY1 Register */
  WoReg MPDDRC_OCMS_KEY2;      /**< \brief (Mpddrc Offset: 0x40) MPDDRC OCMS KEY2 Register */
  RoReg Reserved3[12];
  RwReg MPDDRC_DLL_MOR;        /**< \brief (Mpddrc Offset: 0x74) MPDDRC DLL Master Offset Register */
  RwReg MPDDRC_DLL_SOR;        /**< \brief (Mpddrc Offset: 0x78) MPDDRC DLL Slave Offset Register */
  RoReg MPDDRC_DLL_MSR;        /**< \brief (Mpddrc Offset: 0x7C) MPDDRC DLL Master Status Register */
  RoReg MPDDRC_DLL_SxSR[2];    /**< \brief (Mpddrc Offset: 0x80) MPDDRC DLL Slave 0 Status Register */
  RoReg Reserved4[23];
  RwReg MPDDRC_WPCR;           /**< \brief (Mpddrc Offset: 0xE4) MPDDRC Write Protect Control Register */
  RoReg MPDDRC_WPSR;           /**< \brief (Mpddrc Offset: 0xE8) MPDDRC Write Protect Status Register */
} Mpddrc;
#endif /* __ASSEMBLY__ */
/* -------- MPDDRC_MR : (MPDDRC Offset: 0x00) MPDDRC Mode Register -------- */
#define MPDDRC_MR_MODE_Pos 0
#define MPDDRC_MR_MODE_Msk (0x7u << MPDDRC_MR_MODE_Pos) /**< \brief (MPDDRC_MR) MPDDRC Command Mode */
#define   MPDDRC_MR_MODE_NORMAL_CMD (0x0u << 0) /**< \brief (MPDDRC_MR) Normal Mode. Any access to the MPDDRC will be decoded normally. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */
#define   MPDDRC_MR_MODE_NOP_CMD (0x1u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an NOP command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */
#define   MPDDRC_MR_MODE_PRCGALL_CMD (0x2u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an "All Banks Precharge" command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. */
#define   MPDDRC_MR_MODE_LMR_CMD (0x3u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues a "Load Mode Register" command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */
#define   MPDDRC_MR_MODE_RFSH_CMD (0x4u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an "Auto-Refresh" Command when the DDR-SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */
#define   MPDDRC_MR_MODE_EXT_LMR_CMD (0x5u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. The write in the DDR-SDRAM must be done in the appropriate bank. */
#define   MPDDRC_MR_MODE_DEEP_CMD (0x6u << 0) /**< \brief (MPDDRC_MR) Deep power mode: Access to deep power-down mode */
#define   MPDDRC_MR_MODE_LPDDR2_CMD (0x7u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an "LPDDR2 Mode Register" command when the Low-power DDR2-SDRAM device is accessed regardless of the cycle. To activate this mode, the "Mode Register" command must be followed by a write to the Low-power DDR2-SDRAM. */
#define MPDDRC_MR_MRS_Pos 8
#define MPDDRC_MR_MRS_Msk (0xffu << MPDDRC_MR_MRS_Pos) /**< \brief (MPDDRC_MR) Mode Register Select LPDDR2 */
#define MPDDRC_MR_MRS(value) ((MPDDRC_MR_MRS_Msk & ((value) << MPDDRC_MR_MRS_Pos)))
/* -------- MPDDRC_RTR : (MPDDRC Offset: 0x04) MPDDRC Refresh Timer Register -------- */
#define MPDDRC_RTR_COUNT_Pos 0
#define MPDDRC_RTR_COUNT_Msk (0xfffu << MPDDRC_RTR_COUNT_Pos) /**< \brief (MPDDRC_RTR) MPDDRC Refresh Timer Count */
#define MPDDRC_RTR_COUNT(value) ((MPDDRC_RTR_COUNT_Msk & ((value) << MPDDRC_RTR_COUNT_Pos)))
#define MPDDRC_RTR_ADJ_REF (0x1u << 16) /**< \brief (MPDDRC_RTR) Adjust Refresh Rate */
#define MPDDRC_RTR_REF_PB (0x1u << 17) /**< \brief (MPDDRC_RTR) Refresh Per Bank */
#define MPDDRC_RTR_MR4_VALUE_Pos 20
#define MPDDRC_RTR_MR4_VALUE_Msk (0x7u << MPDDRC_RTR_MR4_VALUE_Pos) /**< \brief (MPDDRC_RTR) Content of MR4 Register */
#define MPDDRC_RTR_MR4_VALUE(value) ((MPDDRC_RTR_MR4_VALUE_Msk & ((value) << MPDDRC_RTR_MR4_VALUE_Pos)))
/* -------- MPDDRC_CR : (MPDDRC Offset: 0x08) MPDDRC Configuration Register -------- */
#define MPDDRC_CR_NC_Pos 0
#define MPDDRC_CR_NC_Msk (0x3u << MPDDRC_CR_NC_Pos) /**< \brief (MPDDRC_CR) Number of Column Bits. */
#define   MPDDRC_CR_NC_9 (0x0u << 0) /**< \brief (MPDDRC_CR) 9 DDR column bits */
#define   MPDDRC_CR_NC_10 (0x1u << 0) /**< \brief (MPDDRC_CR) 10 DDR column bits */
#define   MPDDRC_CR_NC_11 (0x2u << 0) /**< \brief (MPDDRC_CR) 11 DDR column bits */
#define   MPDDRC_CR_NC_12 (0x3u << 0) /**< \brief (MPDDRC_CR) 12 DDR column bits */
#define   MPDDRC_CR_NC(value) ((MPDDRC_CR_NC_Msk & ((value) << MPDDRC_CR_NC_Pos)))
#define MPDDRC_CR_NR_Pos 2
#define MPDDRC_CR_NR_Msk (0x3u << MPDDRC_CR_NR_Pos) /**< \brief (MPDDRC_CR) Number of Row Bits */
#define   MPDDRC_CR_NR_11 (0x0u << 2) /**< \brief (MPDDRC_CR) 11 row bits */
#define   MPDDRC_CR_NR_12 (0x1u << 2) /**< \brief (MPDDRC_CR) 12 row bits */
#define   MPDDRC_CR_NR_13 (0x2u << 2) /**< \brief (MPDDRC_CR) 13 row bits */
#define   MPDDRC_CR_NR_14 (0x3u << 2) /**< \brief (MPDDRC_CR) 14 row bits */
#define   MPDDRC_CR_NR(value) ((MPDDRC_CR_NR_Msk & ((value) << MPDDRC_CR_NR_Pos)))
#define MPDDRC_CR_CAS_Pos 4
#define MPDDRC_CR_CAS_Msk (0x7u << MPDDRC_CR_CAS_Pos) /**< \brief (MPDDRC_CR) CAS Latency */
#define   MPDDRC_CR_CAS_2_DDR1 (0x2u << 4) /**< \brief (MPDDRC_CR) DDR1 CAS Latency 2 */
#define   MPDDRC_CR_CAS_3_DDR2 (0x3u << 4) /**< \brief (MPDDRC_CR) DDR2 CAS Latency 3 */
#define   MPDDRC_CR_CAS_3_LPDDR2 (0x3u << 4) /**< \brief (MPDDRC_CR) LPDDR2 CAS Latency 3 */
#define   MPDDRC_CR_CAS_3_DDR1 (0x3u << 4) /**< \brief (MPDDRC_CR) DDR1 CAS Latency 3 */
#define   MPDDRC_CR_CAS_4_DDR2 (0x4u << 4) /**< \brief (MPDDRC_CR) DDR2 CAS Latency 4 */
#define   MPDDRC_CR_CAS_4_LPDDR2 (0x4u << 4) /**< \brief (MPDDRC_CR) LPDDR2 CAS Latency 4 */
#define   MPDDRC_CR_CAS_5_DDR2 (0x5u << 4) /**< \brief (MPDDRC_CR) DDR2 CAS Latency 5 */
#define   MPDDRC_CR_CAS_5_LPDDR2 (0x5u << 4) /**< \brief (MPDDRC_CR) LPDDR2 CAS Latency 5 */
#define   MPDDRC_CR_CAS_6_DDR2 (0x6u << 4) /**< \brief (MPDDRC_CR) DDR2 CAS Latency 6 */
#define   MPDDRC_CR_CAS_2_5_DDR1 (0x6u << 4) /**< \brief (MPDDRC_CR) DDR1 CAS Latency 2.5 */
#define   MPDDRC_CR_CAS(value) ((MPDDRC_CR_CAS_Msk & ((value) << MPDDRC_CR_CAS_Pos)))
#define MPDDRC_CR_DLL (0x1u << 7) /**< \brief (MPDDRC_CR) Reset DLL */
#define   MPDDRC_CR_DLL_RESET_DISABLED (0x0u << 7) /**< \brief (MPDDRC_CR) Disable DLL reset. */
#define   MPDDRC_CR_DLL_RESET_ENABLED (0x1u << 7) /**< \brief (MPDDRC_CR) Enable DLL reset. */
#define MPDDRC_CR_DIC_DS (0x1u << 8) /**< \brief (MPDDRC_CR) Output Driver Impedance Control (Drive Strength) */
#define MPDDRC_CR_DIS_DLL (0x1u << 9) /**< \brief (MPDDRC_CR) DISABLE DLL */
#define MPDDRC_CR_ZQ_Pos 10
#define MPDDRC_CR_ZQ_Msk (0x3u << MPDDRC_CR_ZQ_Pos) /**< \brief (MPDDRC_CR) ZQ Calibration */
#define   MPDDRC_CR_ZQ_INIT (0x0u << 10) /**< \brief (MPDDRC_CR) Calibration command after initialization */
#define   MPDDRC_CR_ZQ_LONG (0x1u << 10) /**< \brief (MPDDRC_CR) Long calibration */
#define   MPDDRC_CR_ZQ_SHORT (0x2u << 10) /**< \brief (MPDDRC_CR) Short calibration */
#define   MPDDRC_CR_ZQ_RESET (0x3u << 10) /**< \brief (MPDDRC_CR) ZQ Reset */
#define MPDDRC_CR_OCD_Pos 12
#define MPDDRC_CR_OCD_Msk (0x7u << MPDDRC_CR_OCD_Pos) /**< \brief (MPDDRC_CR) Off-chip Driver */
#define MPDDRC_CR_OCD(value) ((MPDDRC_CR_OCD_Msk & ((value) << MPDDRC_CR_OCD_Pos)))
#define MPDDRC_CR_DQMS (0x1u << 16) /**< \brief (MPDDRC_CR) Mask Data is Shared */
#define   MPDDRC_CR_DQMS_NOT_SHARED (0x0u << 16) /**< \brief (MPDDRC_CR) DQM is not shared with another controller. */
#define   MPDDRC_CR_DQMS_SHARED (0x1u << 16) /**< \brief (MPDDRC_CR) DQM is shared with another controller. */
#define MPDDRC_CR_ENRDM (0x1u << 17) /**< \brief (MPDDRC_CR) Enable Read Measure */
#define   MPDDRC_CR_ENRDM_OFF (0x0u << 17) /**< \brief (MPDDRC_CR) DQS/DDR_DATA phase error correction is disabled. */
#define   MPDDRC_CR_ENRDM_ON (0x1u << 17) /**< \brief (MPDDRC_CR) DQS/DDR_DATA phase error correction is enabled. */
#define MPDDRC_CR_NB (0x1u << 20) /**< \brief (MPDDRC_CR) Number of Banks. */
#define   MPDDRC_CR_NB_4 (0x0u << 20) /**< \brief (MPDDRC_CR) 4 banks */
#define   MPDDRC_CR_NB_8 (0x1u << 20) /**< \brief (MPDDRC_CR) 8 banks */
#define MPDDRC_CR_NDQS (0x1u << 21) /**< \brief (MPDDRC_CR) Not DQS: */
#define   MPDDRC_CR_NDQS_ENABLED (0x0u << 21) /**< \brief (MPDDRC_CR) Not DQS is enabled. */
#define   MPDDRC_CR_NDQS_DISABLED (0x1u << 21) /**< \brief (MPDDRC_CR) Not DQS is disabled. */
#define MPDDRC_CR_DECOD (0x1u << 22) /**< \brief (MPDDRC_CR) Type of Decoding */
#define MPDDRC_CR_UNAL (0x1u << 23) /**< \brief (MPDDRC_CR) Support Unaligned Access */
#define   MPDDRC_CR_UNAL_UNSUPPORTED (0x0u << 23) /**< \brief (MPDDRC_CR) Unaligned access is not supported. */
#define   MPDDRC_CR_UNAL_SUPPORTED (0x1u << 23) /**< \brief (MPDDRC_CR) Unaligned access is supported. */
/* -------- MPDDRC_TPR0 : (MPDDRC Offset: 0x0C) MPDDRC Timing Parameter 0 Register -------- */
#define MPDDRC_TPR0_TRAS_Pos 0
#define MPDDRC_TPR0_TRAS_Msk (0xfu << MPDDRC_TPR0_TRAS_Pos) /**< \brief (MPDDRC_TPR0) Active to Precharge Delay */
#define MPDDRC_TPR0_TRAS(value) ((MPDDRC_TPR0_TRAS_Msk & ((value) << MPDDRC_TPR0_TRAS_Pos)))
#define MPDDRC_TPR0_TRCD_Pos 4
#define MPDDRC_TPR0_TRCD_Msk (0xfu << MPDDRC_TPR0_TRCD_Pos) /**< \brief (MPDDRC_TPR0) Row to Column Delay */
#define MPDDRC_TPR0_TRCD(value) ((MPDDRC_TPR0_TRCD_Msk & ((value) << MPDDRC_TPR0_TRCD_Pos)))
#define MPDDRC_TPR0_TWR_Pos 8
#define MPDDRC_TPR0_TWR_Msk (0xfu << MPDDRC_TPR0_TWR_Pos) /**< \brief (MPDDRC_TPR0) Write Recovery Delay */
#define MPDDRC_TPR0_TWR(value) ((MPDDRC_TPR0_TWR_Msk & ((value) << MPDDRC_TPR0_TWR_Pos)))
#define MPDDRC_TPR0_TRC_Pos 12
#define MPDDRC_TPR0_TRC_Msk (0xfu << MPDDRC_TPR0_TRC_Pos) /**< \brief (MPDDRC_TPR0) Row Cycle Delay */
#define MPDDRC_TPR0_TRC(value) ((MPDDRC_TPR0_TRC_Msk & ((value) << MPDDRC_TPR0_TRC_Pos)))
#define MPDDRC_TPR0_TRP_Pos 16
#define MPDDRC_TPR0_TRP_Msk (0xfu << MPDDRC_TPR0_TRP_Pos) /**< \brief (MPDDRC_TPR0) Row Precharge Delay */
#define MPDDRC_TPR0_TRP(value) ((MPDDRC_TPR0_TRP_Msk & ((value) << MPDDRC_TPR0_TRP_Pos)))
#define MPDDRC_TPR0_TRRD_Pos 20
#define MPDDRC_TPR0_TRRD_Msk (0xfu << MPDDRC_TPR0_TRRD_Pos) /**< \brief (MPDDRC_TPR0) Active BankA to Active BankB */
#define MPDDRC_TPR0_TRRD(value) ((MPDDRC_TPR0_TRRD_Msk & ((value) << MPDDRC_TPR0_TRRD_Pos)))
#define MPDDRC_TPR0_TWTR_Pos 24
#define MPDDRC_TPR0_TWTR_Msk (0xfu << MPDDRC_TPR0_TWTR_Pos) /**< \brief (MPDDRC_TPR0) Internal Write to Read Delay */
#define MPDDRC_TPR0_TWTR(value) ((MPDDRC_TPR0_TWTR_Msk & ((value) << MPDDRC_TPR0_TWTR_Pos)))
#define MPDDRC_TPR0_TMRD_Pos 28
#define MPDDRC_TPR0_TMRD_Msk (0xfu << MPDDRC_TPR0_TMRD_Pos) /**< \brief (MPDDRC_TPR0) Load Mode Register Command to Activate or Refresh Command */
#define MPDDRC_TPR0_TMRD(value) ((MPDDRC_TPR0_TMRD_Msk & ((value) << MPDDRC_TPR0_TMRD_Pos)))
/* -------- MPDDRC_TPR1 : (MPDDRC Offset: 0x10) MPDDRC Timing Parameter 1 Register -------- */
#define MPDDRC_TPR1_TRFC_Pos 0
#define MPDDRC_TPR1_TRFC_Msk (0x1fu << MPDDRC_TPR1_TRFC_Pos) /**< \brief (MPDDRC_TPR1) Row Cycle Delay */
#define MPDDRC_TPR1_TRFC(value) ((MPDDRC_TPR1_TRFC_Msk & ((value) << MPDDRC_TPR1_TRFC_Pos)))
#define MPDDRC_TPR1_TXSNR_Pos 8
#define MPDDRC_TPR1_TXSNR_Msk (0xffu << MPDDRC_TPR1_TXSNR_Pos) /**< \brief (MPDDRC_TPR1) Exit Self Refresh Delay to Non Read Command */
#define MPDDRC_TPR1_TXSNR(value) ((MPDDRC_TPR1_TXSNR_Msk & ((value) << MPDDRC_TPR1_TXSNR_Pos)))
#define MPDDRC_TPR1_TXSRD_Pos 16
#define MPDDRC_TPR1_TXSRD_Msk (0xffu << MPDDRC_TPR1_TXSRD_Pos) /**< \brief (MPDDRC_TPR1) Exit Self Refresh Delay to Read Command */
#define MPDDRC_TPR1_TXSRD(value) ((MPDDRC_TPR1_TXSRD_Msk & ((value) << MPDDRC_TPR1_TXSRD_Pos)))
#define MPDDRC_TPR1_TXP_Pos 24
#define MPDDRC_TPR1_TXP_Msk (0xfu << MPDDRC_TPR1_TXP_Pos) /**< \brief (MPDDRC_TPR1) Exit Power-down Delay to First Command */
#define MPDDRC_TPR1_TXP(value) ((MPDDRC_TPR1_TXP_Msk & ((value) << MPDDRC_TPR1_TXP_Pos)))
/* -------- MPDDRC_TPR2 : (MPDDRC Offset: 0x14) MPDDRC Timing Parameter 2 Register -------- */
#define MPDDRC_TPR2_TXARD_Pos 0
#define MPDDRC_TPR2_TXARD_Msk (0xfu << MPDDRC_TPR2_TXARD_Pos) /**< \brief (MPDDRC_TPR2) Exit Active Power Down Delay to Read Command in Mode "Fast Exit". */
#define MPDDRC_TPR2_TXARD(value) ((MPDDRC_TPR2_TXARD_Msk & ((value) << MPDDRC_TPR2_TXARD_Pos)))
#define MPDDRC_TPR2_TXARDS_Pos 4
#define MPDDRC_TPR2_TXARDS_Msk (0xfu << MPDDRC_TPR2_TXARDS_Pos) /**< \brief (MPDDRC_TPR2) Exit Active Power Down Delay to Read Command in Mode "Slow Exit". */
#define MPDDRC_TPR2_TXARDS(value) ((MPDDRC_TPR2_TXARDS_Msk & ((value) << MPDDRC_TPR2_TXARDS_Pos)))
#define MPDDRC_TPR2_TRPA_Pos 8
#define MPDDRC_TPR2_TRPA_Msk (0xfu << MPDDRC_TPR2_TRPA_Pos) /**< \brief (MPDDRC_TPR2) Row Precharge All Delay */
#define MPDDRC_TPR2_TRPA(value) ((MPDDRC_TPR2_TRPA_Msk & ((value) << MPDDRC_TPR2_TRPA_Pos)))
#define MPDDRC_TPR2_TRTP_Pos 12
#define MPDDRC_TPR2_TRTP_Msk (0x7u << MPDDRC_TPR2_TRTP_Pos) /**< \brief (MPDDRC_TPR2) Read to Precharge */
#define MPDDRC_TPR2_TRTP(value) ((MPDDRC_TPR2_TRTP_Msk & ((value) << MPDDRC_TPR2_TRTP_Pos)))
#define MPDDRC_TPR2_TFAW_Pos 16
#define MPDDRC_TPR2_TFAW_Msk (0xfu << MPDDRC_TPR2_TFAW_Pos) /**< \brief (MPDDRC_TPR2) Four Active Windows */
#define MPDDRC_TPR2_TFAW(value) ((MPDDRC_TPR2_TFAW_Msk & ((value) << MPDDRC_TPR2_TFAW_Pos)))
/* -------- MPDDRC_LPR : (MPDDRC Offset: 0x1C) MPDDRC Low-power Register -------- */
#define MPDDRC_LPR_LPCB_Pos 0
#define MPDDRC_LPR_LPCB_Msk (0x3u << MPDDRC_LPR_LPCB_Pos) /**< \brief (MPDDRC_LPR) Low-power Command Bit */
#define   MPDDRC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (MPDDRC_LPR) Low-power Feature is inhibited. No power-down, self refresh and deep-power modes are issued to the DDR-SDRAM device. */
#define   MPDDRC_LPR_LPCB_SELFREFRESH (0x1u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a Self Refresh command to the DDR-SDRAM device, the clock(s) is/are de-activated and the CKE signal is set low. The DDR-SDRAM device leaves the self refresh mode when accessed and reenters it after the access. */
#define   MPDDRC_LPR_LPCB_POWERDOWN (0x2u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a Power-down Command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the power-down mode when accessed and reenters it after the access. */
#define   MPDDRC_LPR_LPCB_DEEP_PWD (0x3u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a Deep Power-down command to the Low-power DDR-SDRAM device. */
#define MPDDRC_LPR_CLK_FR (0x1u << 2) /**< \brief (MPDDRC_LPR) Clock Frozen Command Bit */
#define   MPDDRC_LPR_CLK_FR_DISABLED (0x0u << 2) /**< \brief (MPDDRC_LPR) Clock(s) is/are not frozen. */
#define   MPDDRC_LPR_CLK_FR_ENABLED (0x1u << 2) /**< \brief (MPDDRC_LPR) Clock(s) is/are frozen. */
#define MPDDRC_LPR_LPDDR2_PWOFF (0x1u << 3) /**< \brief (MPDDRC_LPR) LPDDR2 Power Off Bit */
#define   MPDDRC_LPR_LPDDR2_PWOFF_DISABLED (0x0u << 3) /**< \brief (MPDDRC_LPR) No power off sequence applied to LPDDR2. */
#define   MPDDRC_LPR_LPDDR2_PWOFF_ENABLED (0x1u << 3) /**< \brief (MPDDRC_LPR) A power off sequence is applied to the LPDDR2 device. CKE is forced low. */
#define MPDDRC_LPR_PASR_Pos 4
#define MPDDRC_LPR_PASR_Msk (0x7u << MPDDRC_LPR_PASR_Pos) /**< \brief (MPDDRC_LPR) Partial Array Self Refresh */
#define MPDDRC_LPR_PASR(value) ((MPDDRC_LPR_PASR_Msk & ((value) << MPDDRC_LPR_PASR_Pos)))
#define MPDDRC_LPR_DS_Pos 8
#define MPDDRC_LPR_DS_Msk (0x7u << MPDDRC_LPR_DS_Pos) /**< \brief (MPDDRC_LPR) Drive Strength */
#define MPDDRC_LPR_DS(value) ((MPDDRC_LPR_DS_Msk & ((value) << MPDDRC_LPR_DS_Pos)))
#define MPDDRC_LPR_TIMEOUT_Pos 12
#define MPDDRC_LPR_TIMEOUT_Msk (0x3u << MPDDRC_LPR_TIMEOUT_Pos) /**< \brief (MPDDRC_LPR) Enter Low-power Mode */
#define   MPDDRC_LPR_TIMEOUT_0 (0x0u << 12) /**< \brief (MPDDRC_LPR) The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. */
#define   MPDDRC_LPR_TIMEOUT_64 (0x1u << 12) /**< \brief (MPDDRC_LPR) The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */
#define   MPDDRC_LPR_TIMEOUT_128 (0x2u << 12) /**< \brief (MPDDRC_LPR) The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */
#define MPDDRC_LPR_APDE (0x1u << 16) /**< \brief (MPDDRC_LPR) Active Power Down Exit Time */
#define   MPDDRC_LPR_APDE_FAST (0x0u << 16) /**< \brief (MPDDRC_LPR) Fast Exit. */
#define   MPDDRC_LPR_APDE_SLOW (0x1u << 16) /**< \brief (MPDDRC_LPR) Low Exit. */
#define MPDDRC_LPR_UPD_MR_Pos 20
#define MPDDRC_LPR_UPD_MR_Msk (0x3u << MPDDRC_LPR_UPD_MR_Pos) /**< \brief (MPDDRC_LPR) Update Load Mode Register and Extended Mode Register */
#define MPDDRC_LPR_UPD_MR(value) ((MPDDRC_LPR_UPD_MR_Msk & ((value) << MPDDRC_LPR_UPD_MR_Pos)))
/* -------- MPDDRC_MD : (MPDDRC Offset: 0x20) MPDDRC Memory Device Register -------- */
#define MPDDRC_MD_MD_Pos 0
#define MPDDRC_MD_MD_Msk (0x7u << MPDDRC_MD_MD_Pos) /**< \brief (MPDDRC_MD) Memory Device */
#define   MPDDRC_MD_MD_DDR_SDRAM (0x2u << 0) /**< \brief (MPDDRC_MD) DDR1-SDRAM */
#define   MPDDRC_MD_MD_LPDDR_SDRAM (0x3u << 0) /**< \brief (MPDDRC_MD) Low-power DDR1-SDRAM */
#define   MPDDRC_MD_MD_DDR2_SDRAM (0x6u << 0) /**< \brief (MPDDRC_MD) DDR2-SDRAM */
#define   MPDDRC_MD_MD_LPDDR2_SDRAM (0x7u << 0) /**< \brief (MPDDRC_MD) Low-Power DDR2-SDRAM */
#define MPDDRC_MD_DBW (0x1u << 4) /**< \brief (MPDDRC_MD) Data Bus Width */
/* -------- MPDDRC_LPDDR2_LPR : (MPDDRC Offset: 0x28) MPDDRC LPDDR2 Low-power Register -------- */
#define MPDDRC_LPDDR2_LPR_BK_MASK_Pos 0
#define MPDDRC_LPDDR2_LPR_BK_MASK_Msk (0xffu << MPDDRC_LPDDR2_LPR_BK_MASK_Pos) /**< \brief (MPDDRC_LPDDR2_LPR)  */
#define MPDDRC_LPDDR2_LPR_BK_MASK(value) ((MPDDRC_LPDDR2_LPR_BK_MASK_Msk & ((value) << MPDDRC_LPDDR2_LPR_BK_MASK_Pos)))
#define MPDDRC_LPDDR2_LPR_SEG_MASK_Pos 8
#define MPDDRC_LPDDR2_LPR_SEG_MASK_Msk (0xffffu << MPDDRC_LPDDR2_LPR_SEG_MASK_Pos) /**< \brief (MPDDRC_LPDDR2_LPR) Segment Mask Bit */
#define MPDDRC_LPDDR2_LPR_SEG_MASK(value) ((MPDDRC_LPDDR2_LPR_SEG_MASK_Msk & ((value) << MPDDRC_LPDDR2_LPR_SEG_MASK_Pos)))
#define MPDDRC_LPDDR2_LPR_DS_Pos 24
#define MPDDRC_LPDDR2_LPR_DS_Msk (0xfu << MPDDRC_LPDDR2_LPR_DS_Pos) /**< \brief (MPDDRC_LPDDR2_LPR) Drive strength */
#define MPDDRC_LPDDR2_LPR_DS(value) ((MPDDRC_LPDDR2_LPR_DS_Msk & ((value) << MPDDRC_LPDDR2_LPR_DS_Pos)))
/* -------- MPDDRC_LPDDR2_CAL_MR4 : (MPDDRC Offset: 0x2C) MPDDRC LPDDR2 Calibration and MR4 Register -------- */
#define MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Pos 0
#define MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Msk (0xffffu << MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Pos) /**< \brief (MPDDRC_LPDDR2_CAL_MR4) LPDDR2 Calibration Timer Count */
#define MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL(value) ((MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Msk & ((value) << MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Pos)))
#define MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Pos 16
#define MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Msk (0xffffu << MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Pos) /**< \brief (MPDDRC_LPDDR2_CAL_MR4) Mode Register 4 Read Interval */
#define MPDDRC_LPDDR2_CAL_MR4_MR4_READ(value) ((MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Msk & ((value) << MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Pos)))
/* -------- MPDDRC_LPDDR2_TIM_CAL : (MPDDRC Offset: 0x30) MPDDRC LPDDR2 Timing Calibration Register -------- */
#define MPDDRC_LPDDR2_TIM_CAL_ZQCS_Pos 0
#define MPDDRC_LPDDR2_TIM_CAL_ZQCS_Msk (0xffu << MPDDRC_LPDDR2_TIM_CAL_ZQCS_Pos) /**< \brief (MPDDRC_LPDDR2_TIM_CAL) ZQ Calibration Short */
#define MPDDRC_LPDDR2_TIM_CAL_ZQCS(value) ((MPDDRC_LPDDR2_TIM_CAL_ZQCS_Msk & ((value) << MPDDRC_LPDDR2_TIM_CAL_ZQCS_Pos)))
/* -------- MPDDRC_IO_CALIBR : (MPDDRC Offset: 0x34) MPDDRC IO Calibration -------- */
#define MPDDRC_IO_CALIBR_RDIV_Pos 0
#define MPDDRC_IO_CALIBR_RDIV_Msk (0x7u << MPDDRC_IO_CALIBR_RDIV_Pos) /**< \brief (MPDDRC_IO_CALIBR) Resistor Divider */
#define   MPDDRC_IO_CALIBR_RDIV_RZQ_34 (0x1u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ = 34,3 Ohm */
#define   MPDDRC_IO_CALIBR_RDIV_RZQ_40 (0x2u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ = 40 Ohm */
#define   MPDDRC_IO_CALIBR_RDIV_RZQ_48 (0x3u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ =48 Ohm */
#define   MPDDRC_IO_CALIBR_RDIV_RZQ_60 (0x4u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ =60 Ohm */
#define   MPDDRC_IO_CALIBR_RDIV_RZQ_80 (0x6u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ = 80 Ohm */
#define   MPDDRC_IO_CALIBR_RDIV_RZQ_120 (0x7u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ = 120 Ohm */
#define MPDDRC_IO_CALIBR_TZQIO_Pos 8
#define MPDDRC_IO_CALIBR_TZQIO_Msk (0x1fu << MPDDRC_IO_CALIBR_TZQIO_Pos) /**< \brief (MPDDRC_IO_CALIBR) IO Calibration */
#define MPDDRC_IO_CALIBR_TZQIO(value) ((MPDDRC_IO_CALIBR_TZQIO_Msk & ((value) << MPDDRC_IO_CALIBR_TZQIO_Pos)))
#define MPDDRC_IO_CALIBR_CALCODEP_Pos 16
#define MPDDRC_IO_CALIBR_CALCODEP_Msk (0xfu << MPDDRC_IO_CALIBR_CALCODEP_Pos) /**< \brief (MPDDRC_IO_CALIBR) Number of Transistor P */
#define MPDDRC_IO_CALIBR_CALCODEP(value) ((MPDDRC_IO_CALIBR_CALCODEP_Msk & ((value) << MPDDRC_IO_CALIBR_CALCODEP_Pos)))
#define MPDDRC_IO_CALIBR_CALCODEN_Pos 20
#define MPDDRC_IO_CALIBR_CALCODEN_Msk (0xfu << MPDDRC_IO_CALIBR_CALCODEN_Pos) /**< \brief (MPDDRC_IO_CALIBR) Number of Transistor N */
#define MPDDRC_IO_CALIBR_CALCODEN(value) ((MPDDRC_IO_CALIBR_CALCODEN_Msk & ((value) << MPDDRC_IO_CALIBR_CALCODEN_Pos)))
/* -------- MPDDRC_OCMS_KEY1 : (MPDDRC Offset: 0x3C) MPDDRC OCMS KEY1 Register -------- */
#define MPDDRC_OCMS_KEY1_KEY1n_Pos 0
#define MPDDRC_OCMS_KEY1_KEY1n_Msk (0xffu << MPDDRC_OCMS_KEY1_KEY1n_Pos) /**< \brief (MPDDRC_OCMS_KEY1)  */
#define MPDDRC_OCMS_KEY1_KEY1n(value) ((MPDDRC_OCMS_KEY1_KEY1n_Msk & ((value) << MPDDRC_OCMS_KEY1_KEY1n_Pos)))
#define MPDDRC_OCMS_KEY1_KEY1_Pos 8
#define MPDDRC_OCMS_KEY1_KEY1_Msk (0xffffffu << MPDDRC_OCMS_KEY1_KEY1_Pos) /**< \brief (MPDDRC_OCMS_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
#define MPDDRC_OCMS_KEY1_KEY1(value) ((MPDDRC_OCMS_KEY1_KEY1_Msk & ((value) << MPDDRC_OCMS_KEY1_KEY1_Pos)))
/* -------- MPDDRC_OCMS_KEY2 : (MPDDRC Offset: 0x40) MPDDRC OCMS KEY2 Register -------- */
#define MPDDRC_OCMS_KEY2_KEY2_Pos 0
#define MPDDRC_OCMS_KEY2_KEY2_Msk (0xffffffffu << MPDDRC_OCMS_KEY2_KEY2_Pos) /**< \brief (MPDDRC_OCMS_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
#define MPDDRC_OCMS_KEY2_KEY2(value) ((MPDDRC_OCMS_KEY2_KEY2_Msk & ((value) << MPDDRC_OCMS_KEY2_KEY2_Pos)))
/* -------- MPDDRC_DLL_MOR : (MPDDRC Offset: 0x74) MPDDRC DLL Master Offset Register -------- */
#define MPDDRC_DLL_MOR_MOFF_Pos 0
#define MPDDRC_DLL_MOR_MOFF_Msk (0xfu << MPDDRC_DLL_MOR_MOFF_Pos) /**< \brief (MPDDRC_DLL_MOR) DLL Master Delay Line Offset */
#define MPDDRC_DLL_MOR_MOFF(value) ((MPDDRC_DLL_MOR_MOFF_Msk & ((value) << MPDDRC_DLL_MOR_MOFF_Pos)))
#define MPDDRC_DLL_MOR_CLK90OFF_Pos 8
#define MPDDRC_DLL_MOR_CLK90OFF_Msk (0x1fu << MPDDRC_DLL_MOR_CLK90OFF_Pos) /**< \brief (MPDDRC_DLL_MOR) DLL CLK90 Delay Line Offset */
#define MPDDRC_DLL_MOR_CLK90OFF(value) ((MPDDRC_DLL_MOR_CLK90OFF_Msk & ((value) << MPDDRC_DLL_MOR_CLK90OFF_Pos)))
#define MPDDRC_DLL_MOR_SELOFF (0x1u << 16) /**< \brief (MPDDRC_DLL_MOR) DLL Offset Selection */
/* -------- MPDDRC_DLL_MSR : (MPDDRC Offset: 0x7C) MPDDRC DLL Master Status Register -------- */
#define MPDDRC_DLL_MSR_MDINC (0x1u << 0) /**< \brief (MPDDRC_DLL_MSR) DLL Master Delay Increment */
#define MPDDRC_DLL_MSR_MDDEC (0x1u << 1) /**< \brief (MPDDRC_DLL_MSR) DLL Master Delay Decrement */
#define MPDDRC_DLL_MSR_MDOVF (0x1u << 2) /**< \brief (MPDDRC_DLL_MSR) DLL Master Delay Overflow Flag */
#define MPDDRC_DLL_MSR_MDVAL_Pos 8
#define MPDDRC_DLL_MSR_MDVAL_Msk (0xffu << MPDDRC_DLL_MSR_MDVAL_Pos) /**< \brief (MPDDRC_DLL_MSR) DLL Master Delay Value */
/* -------- MPDDRC_DLL_S0SR : (MPDDRC Offset: 0x80) MPDDRC DLL Slave 0 Status Register -------- */
#define MPDDRC_DLL_S0SR_SDCOVF (0x1u << 0) /**< \brief (MPDDRC_DLL_S0SR) DLL Slave x Delay Correction Overflow Flag */
#define MPDDRC_DLL_S0SR_SDCUDF (0x1u << 1) /**< \brief (MPDDRC_DLL_S0SR) DLL Slave x Delay Correction Underflow Flag */
#define MPDDRC_DLL_S0SR_SDERF (0x1u << 2) /**< \brief (MPDDRC_DLL_S0SR) DLL Slave x Delay Correction Error Flag */
#define MPDDRC_DLL_S0SR_SDVAL_Pos 8
#define MPDDRC_DLL_S0SR_SDVAL_Msk (0xffu << MPDDRC_DLL_S0SR_SDVAL_Pos) /**< \brief (MPDDRC_DLL_S0SR) DLL Slave x Delay Value */
#define MPDDRC_DLL_S0SR_SDCVAL_Pos 16
#define MPDDRC_DLL_S0SR_SDCVAL_Msk (0xffu << MPDDRC_DLL_S0SR_SDCVAL_Pos) /**< \brief (MPDDRC_DLL_S0SR) DLL Slave x Delay Correction Value */
/* -------- MPDDRC_DLL_S1SR : (MPDDRC Offset: 0x84) MPDDRC DLL Slave 1 Status Register -------- */
#define MPDDRC_DLL_S1SR_SDCOVF (0x1u << 0) /**< \brief (MPDDRC_DLL_S1SR) DLL Slave x Delay Correction Overflow Flag */
#define MPDDRC_DLL_S1SR_SDCUDF (0x1u << 1) /**< \brief (MPDDRC_DLL_S1SR) DLL Slave x Delay Correction Underflow Flag */
#define MPDDRC_DLL_S1SR_SDERF (0x1u << 2) /**< \brief (MPDDRC_DLL_S1SR) DLL Slave x Delay Correction Error Flag */
#define MPDDRC_DLL_S1SR_SDVAL_Pos 8
#define MPDDRC_DLL_S1SR_SDVAL_Msk (0xffu << MPDDRC_DLL_S1SR_SDVAL_Pos) /**< \brief (MPDDRC_DLL_S1SR) DLL Slave x Delay Value */
#define MPDDRC_DLL_S1SR_SDCVAL_Pos 16
#define MPDDRC_DLL_S1SR_SDCVAL_Msk (0xffu << MPDDRC_DLL_S1SR_SDCVAL_Pos) /**< \brief (MPDDRC_DLL_S1SR) DLL Slave x Delay Correction Value */
/* -------- MPDDRC_WPCR : (MPDDRC Offset: 0xE4) MPDDRC Write Protect Control Register -------- */
#define MPDDRC_WPCR_WPEN (0x1u << 0) /**< \brief (MPDDRC_WPCR) Write Protection Enable */
#define MPDDRC_WPCR_WPKEY_Pos 8
#define MPDDRC_WPCR_WPKEY_Msk (0xffffffu << MPDDRC_WPCR_WPKEY_Pos) /**< \brief (MPDDRC_WPCR) Write Protection KEY */
#define MPDDRC_WPCR_WPKEY(value) ((MPDDRC_WPCR_WPKEY_Msk & ((value) << MPDDRC_WPCR_WPKEY_Pos)))
/* -------- MPDDRC_WPSR : (MPDDRC Offset: 0xE8) MPDDRC Write Protect Status Register -------- */
#define MPDDRC_WPSR_WPVS (0x1u << 0) /**< \brief (MPDDRC_WPSR) Write Protection Enable */
#define MPDDRC_WPSR_WPVSRC_Pos 8
#define MPDDRC_WPSR_WPVSRC_Msk (0xffffu << MPDDRC_WPSR_WPVSRC_Pos) /**< \brief (MPDDRC_WPSR) Write Protection Violation Source */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_PIO Parallel Input/Output Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Pio hardware registers */
typedef struct {
  WoReg PIO_PER;       /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
  WoReg PIO_PDR;       /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
  RoReg PIO_PSR;       /**< \brief (Pio Offset: 0x0008) PIO Status Register */
  RoReg Reserved1[1];
  WoReg PIO_OER;       /**< \brief (Pio Offset: 0x0010) Output Enable Register */
  WoReg PIO_ODR;       /**< \brief (Pio Offset: 0x0014) Output Disable Register */
  RoReg PIO_OSR;       /**< \brief (Pio Offset: 0x0018) Output Status Register */
  RoReg Reserved2[1];
  WoReg PIO_IFER;      /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
  WoReg PIO_IFDR;      /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
  RoReg PIO_IFSR;      /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
  RoReg Reserved3[1];
  WoReg PIO_SODR;      /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
  WoReg PIO_CODR;      /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
  RwReg PIO_ODSR;      /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
  RoReg PIO_PDSR;      /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
  WoReg PIO_IER;       /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
  WoReg PIO_IDR;       /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
  RoReg PIO_IMR;       /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
  RoReg PIO_ISR;       /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
  WoReg PIO_MDER;      /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
  WoReg PIO_MDDR;      /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
  RoReg PIO_MDSR;      /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
  RoReg Reserved4[1];
  WoReg PIO_PUDR;      /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
  WoReg PIO_PUER;      /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
  RoReg PIO_PUSR;      /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
  RoReg Reserved5[1];
  RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
  RoReg Reserved6[2];
  WoReg PIO_IFSCDR;    /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
  WoReg PIO_IFSCER;    /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
  RoReg PIO_IFSCSR;    /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
  RwReg PIO_SCDR;      /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
  WoReg PIO_PPDDR;     /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
  WoReg PIO_PPDER;     /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
  RoReg PIO_PPDSR;     /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
  RoReg Reserved7[1];
  WoReg PIO_OWER;      /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
  WoReg PIO_OWDR;      /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
  RoReg PIO_OWSR;      /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
  RoReg Reserved8[1];
  WoReg PIO_AIMER;     /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
  WoReg PIO_AIMDR;     /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
  RoReg PIO_AIMMR;     /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
  RoReg Reserved9[1];
  WoReg PIO_ESR;       /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
  WoReg PIO_LSR;       /**< \brief (Pio Offset: 0x00C4) Level Select Register */
  RoReg PIO_ELSR;      /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
  RoReg Reserved10[1];
  WoReg PIO_FELLSR;    /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
  WoReg PIO_REHLSR;    /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
  RoReg PIO_FRLHSR;    /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
  RoReg Reserved11[1];
  RoReg PIO_LOCKSR;    /**< \brief (Pio Offset: 0x00E0) Lock Status */
  RwReg PIO_WPMR;      /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
  RoReg PIO_WPSR;      /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
  RoReg Reserved12[5];
  RwReg PIO_SCHMITT;   /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
  RoReg Reserved13[5];
  RwReg PIO_DRIVER1;   /**< \brief (Pio Offset: 0x0118) I/O Drive Register 1 */
  RwReg PIO_DRIVER2;   /**< \brief (Pio Offset: 0x011C) I/O Drive Register 2 */
} Pio;
#endif /* __ASSEMBLY__ */
/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
#define PIO_SCDR_DIV_Pos 0
#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR)  */
#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */
#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */
/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */
#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */
/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */
#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */
/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
#define PIO_WPMR_WPKEY_Pos 8
#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
#define PIO_WPSR_WPVSRC_Pos 8
#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT)  */
#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT)  */
/* -------- PIO_DRIVER1 : (PIO Offset: 0x0118) I/O Drive Register 1 -------- */
#define PIO_DRIVER1_LINE0_Pos 0
#define PIO_DRIVER1_LINE0_Msk (0x3u << PIO_DRIVER1_LINE0_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 0 */
#define   PIO_DRIVER1_LINE0_HI_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE0_ME_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE0_LO_DRIVE (0x2u << 0) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE1_Pos 2
#define PIO_DRIVER1_LINE1_Msk (0x3u << PIO_DRIVER1_LINE1_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 1 */
#define   PIO_DRIVER1_LINE1_HI_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE1_ME_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE1_LO_DRIVE (0x2u << 2) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE2_Pos 4
#define PIO_DRIVER1_LINE2_Msk (0x3u << PIO_DRIVER1_LINE2_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 2 */
#define   PIO_DRIVER1_LINE2_HI_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE2_ME_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE2_LO_DRIVE (0x2u << 4) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE3_Pos 6
#define PIO_DRIVER1_LINE3_Msk (0x3u << PIO_DRIVER1_LINE3_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 3 */
#define   PIO_DRIVER1_LINE3_HI_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE3_ME_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE3_LO_DRIVE (0x2u << 6) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE4_Pos 8
#define PIO_DRIVER1_LINE4_Msk (0x3u << PIO_DRIVER1_LINE4_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 4 */
#define   PIO_DRIVER1_LINE4_HI_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE4_ME_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE4_LO_DRIVE (0x2u << 8) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE5_Pos 10
#define PIO_DRIVER1_LINE5_Msk (0x3u << PIO_DRIVER1_LINE5_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 5 */
#define   PIO_DRIVER1_LINE5_HI_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE5_ME_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE5_LO_DRIVE (0x2u << 10) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE6_Pos 12
#define PIO_DRIVER1_LINE6_Msk (0x3u << PIO_DRIVER1_LINE6_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 6 */
#define   PIO_DRIVER1_LINE6_HI_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE6_ME_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE6_LO_DRIVE (0x2u << 12) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE7_Pos 14
#define PIO_DRIVER1_LINE7_Msk (0x3u << PIO_DRIVER1_LINE7_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 7 */
#define   PIO_DRIVER1_LINE7_HI_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE7_ME_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE7_LO_DRIVE (0x2u << 14) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE8_Pos 16
#define PIO_DRIVER1_LINE8_Msk (0x3u << PIO_DRIVER1_LINE8_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 8 */
#define   PIO_DRIVER1_LINE8_HI_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE8_ME_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE8_LO_DRIVE (0x2u << 16) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE9_Pos 18
#define PIO_DRIVER1_LINE9_Msk (0x3u << PIO_DRIVER1_LINE9_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 9 */
#define   PIO_DRIVER1_LINE9_HI_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE9_ME_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE9_LO_DRIVE (0x2u << 18) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE10_Pos 20
#define PIO_DRIVER1_LINE10_Msk (0x3u << PIO_DRIVER1_LINE10_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 10 */
#define   PIO_DRIVER1_LINE10_HI_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE10_ME_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE10_LO_DRIVE (0x2u << 20) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE11_Pos 22
#define PIO_DRIVER1_LINE11_Msk (0x3u << PIO_DRIVER1_LINE11_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 11 */
#define   PIO_DRIVER1_LINE11_HI_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE11_ME_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE11_LO_DRIVE (0x2u << 22) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE12_Pos 24
#define PIO_DRIVER1_LINE12_Msk (0x3u << PIO_DRIVER1_LINE12_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 12 */
#define   PIO_DRIVER1_LINE12_HI_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE12_ME_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE12_LO_DRIVE (0x2u << 24) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE13_Pos 26
#define PIO_DRIVER1_LINE13_Msk (0x3u << PIO_DRIVER1_LINE13_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 13 */
#define   PIO_DRIVER1_LINE13_HI_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE13_ME_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE13_LO_DRIVE (0x2u << 26) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE14_Pos 28
#define PIO_DRIVER1_LINE14_Msk (0x3u << PIO_DRIVER1_LINE14_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 14 */
#define   PIO_DRIVER1_LINE14_HI_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE14_ME_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE14_LO_DRIVE (0x2u << 28) /**< \brief (PIO_DRIVER1) Low drive */
#define PIO_DRIVER1_LINE15_Pos 30
#define PIO_DRIVER1_LINE15_Msk (0x3u << PIO_DRIVER1_LINE15_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 15 */
#define   PIO_DRIVER1_LINE15_HI_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER1) High drive */
#define   PIO_DRIVER1_LINE15_ME_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER1) Medium drive */
#define   PIO_DRIVER1_LINE15_LO_DRIVE (0x2u << 30) /**< \brief (PIO_DRIVER1) Low drive */
/* -------- PIO_DRIVER2 : (PIO Offset: 0x011C) I/O Drive Register 2 -------- */
#define PIO_DRIVER2_LINE16_Pos 0
#define PIO_DRIVER2_LINE16_Msk (0x3u << PIO_DRIVER2_LINE16_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 16 */
#define   PIO_DRIVER2_LINE16_HI_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE16_ME_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE16_LO_DRIVE (0x2u << 0) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE17_Pos 2
#define PIO_DRIVER2_LINE17_Msk (0x3u << PIO_DRIVER2_LINE17_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 17 */
#define   PIO_DRIVER2_LINE17_HI_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE17_ME_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE17_LO_DRIVE (0x2u << 2) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE18_Pos 4
#define PIO_DRIVER2_LINE18_Msk (0x3u << PIO_DRIVER2_LINE18_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 18 */
#define   PIO_DRIVER2_LINE18_HI_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE18_ME_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE18_LO_DRIVE (0x2u << 4) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE19_Pos 6
#define PIO_DRIVER2_LINE19_Msk (0x3u << PIO_DRIVER2_LINE19_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 19 */
#define   PIO_DRIVER2_LINE19_HI_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE19_ME_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE19_LO_DRIVE (0x2u << 6) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE20_Pos 8
#define PIO_DRIVER2_LINE20_Msk (0x3u << PIO_DRIVER2_LINE20_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 20 */
#define   PIO_DRIVER2_LINE20_HI_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE20_ME_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE20_LO_DRIVE (0x2u << 8) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE21_Pos 10
#define PIO_DRIVER2_LINE21_Msk (0x3u << PIO_DRIVER2_LINE21_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 21 */
#define   PIO_DRIVER2_LINE21_HI_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE21_ME_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE21_LO_DRIVE (0x2u << 10) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE22_Pos 12
#define PIO_DRIVER2_LINE22_Msk (0x3u << PIO_DRIVER2_LINE22_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 22 */
#define   PIO_DRIVER2_LINE22_HI_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE22_ME_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE22_LO_DRIVE (0x2u << 12) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE23_Pos 14
#define PIO_DRIVER2_LINE23_Msk (0x3u << PIO_DRIVER2_LINE23_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 23 */
#define   PIO_DRIVER2_LINE23_HI_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE23_ME_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE23_LO_DRIVE (0x2u << 14) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE24_Pos 16
#define PIO_DRIVER2_LINE24_Msk (0x3u << PIO_DRIVER2_LINE24_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 24 */
#define   PIO_DRIVER2_LINE24_HI_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE24_ME_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE24_LO_DRIVE (0x2u << 16) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE25_Pos 18
#define PIO_DRIVER2_LINE25_Msk (0x3u << PIO_DRIVER2_LINE25_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 25 */
#define   PIO_DRIVER2_LINE25_HI_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE25_ME_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE25_LO_DRIVE (0x2u << 18) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE26_Pos 20
#define PIO_DRIVER2_LINE26_Msk (0x3u << PIO_DRIVER2_LINE26_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 26 */
#define   PIO_DRIVER2_LINE26_HI_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE26_ME_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE26_LO_DRIVE (0x2u << 20) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE27_Pos 22
#define PIO_DRIVER2_LINE27_Msk (0x3u << PIO_DRIVER2_LINE27_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 27 */
#define   PIO_DRIVER2_LINE27_HI_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE27_ME_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE27_LO_DRIVE (0x2u << 22) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE28_Pos 24
#define PIO_DRIVER2_LINE28_Msk (0x3u << PIO_DRIVER2_LINE28_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 28 */
#define   PIO_DRIVER2_LINE28_HI_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE28_ME_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE28_LO_DRIVE (0x2u << 24) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE29_Pos 26
#define PIO_DRIVER2_LINE29_Msk (0x3u << PIO_DRIVER2_LINE29_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 29 */
#define   PIO_DRIVER2_LINE29_HI_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE29_ME_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE29_LO_DRIVE (0x2u << 26) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE30_Pos 28
#define PIO_DRIVER2_LINE30_Msk (0x3u << PIO_DRIVER2_LINE30_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 30 */
#define   PIO_DRIVER2_LINE30_HI_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE30_ME_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE30_LO_DRIVE (0x2u << 28) /**< \brief (PIO_DRIVER2) Low drive */
#define PIO_DRIVER2_LINE31_Pos 30
#define PIO_DRIVER2_LINE31_Msk (0x3u << PIO_DRIVER2_LINE31_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 31 */
#define   PIO_DRIVER2_LINE31_HI_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER2) High drive */
#define   PIO_DRIVER2_LINE31_ME_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER2) Medium drive */
#define   PIO_DRIVER2_LINE31_LO_DRIVE (0x2u << 30) /**< \brief (PIO_DRIVER2) Low drive */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Periodic Interval Timer */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_PIT Periodic Interval Timer */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Pit hardware registers */
typedef struct {
  RwReg PIT_MR;   /**< \brief (Pit Offset: 0x00) Mode Register */
  RoReg PIT_SR;   /**< \brief (Pit Offset: 0x04) Status Register */
  RoReg PIT_PIVR; /**< \brief (Pit Offset: 0x08) Periodic Interval Value Register */
  RoReg PIT_PIIR; /**< \brief (Pit Offset: 0x0C) Periodic Interval Image Register */
} Pit;
#endif /* __ASSEMBLY__ */
/* -------- PIT_MR : (PIT Offset: 0x00) Mode Register -------- */
#define PIT_MR_PIV_Pos 0
#define PIT_MR_PIV_Msk (0xfffffu << PIT_MR_PIV_Pos) /**< \brief (PIT_MR) Periodic Interval Value */
#define PIT_MR_PIV(value) ((PIT_MR_PIV_Msk & ((value) << PIT_MR_PIV_Pos)))
#define PIT_MR_PITEN (0x1u << 24) /**< \brief (PIT_MR) Period Interval Timer Enabled */
#define PIT_MR_PITIEN (0x1u << 25) /**< \brief (PIT_MR) Periodic Interval Timer Interrupt Enable */
/* -------- PIT_SR : (PIT Offset: 0x04) Status Register -------- */
#define PIT_SR_PITS (0x1u << 0) /**< \brief (PIT_SR) Periodic Interval Timer Status */
/* -------- PIT_PIVR : (PIT Offset: 0x08) Periodic Interval Value Register -------- */
#define PIT_PIVR_CPIV_Pos 0
#define PIT_PIVR_CPIV_Msk (0xfffffu << PIT_PIVR_CPIV_Pos) /**< \brief (PIT_PIVR) Current Periodic Interval Value */
#define PIT_PIVR_PICNT_Pos 20
#define PIT_PIVR_PICNT_Msk (0xfffu << PIT_PIVR_PICNT_Pos) /**< \brief (PIT_PIVR) Periodic Interval Counter */
/* -------- PIT_PIIR : (PIT Offset: 0x0C) Periodic Interval Image Register -------- */
#define PIT_PIIR_CPIV_Pos 0
#define PIT_PIIR_CPIV_Msk (0xfffffu << PIT_PIIR_CPIV_Pos) /**< \brief (PIT_PIIR) Current Periodic Interval Value */
#define PIT_PIIR_PICNT_Pos 20
#define PIT_PIIR_PICNT_Msk (0xfffu << PIT_PIIR_PICNT_Pos) /**< \brief (PIT_PIIR) Periodic Interval Counter */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Power Management Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_PMC Power Management Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Pmc hardware registers */
typedef struct {
  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
  RoReg Reserved1[1];
  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
  RwReg CKGR_UCKR;     /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
  RoReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
  RoReg Reserved2[1];
  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
  RoReg Reserved3[1];
  RwReg PMC_USB;       /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
  RwReg PMC_SMD;       /**< \brief (Pmc Offset: 0x003C) Soft Modem Clock Register */
  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
  RoReg Reserved4[5];
  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
  RoReg Reserved5[4];
  WoReg PMC_PLLICPR;   /**< \brief (Pmc Offset: 0x0080) PLL Charge Pump Current Register */
  RoReg Reserved6[24];
  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
  RoReg Reserved7[5];
  WoReg PMC_PCER1;     /**< \brief (Pmc Offset: 0x00100) Peripheral Clock Enable Register 1 */
  WoReg PMC_PCDR1;     /**< \brief (Pmc Offset: 0x00104) Peripheral Clock Disable Register 1 */
  RoReg PMC_PCSR1;     /**< \brief (Pmc Offset: 0x00108) Peripheral Clock Status Register 1 */
  RwReg PMC_PCR;       /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */
} Pmc;
#endif /* __ASSEMBLY__ */
/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
#define PMC_SCER_DDRCK (0x1u << 2) /**< \brief (PMC_SCER) DDR Clock Enable */
#define PMC_SCER_SMDCK (0x1u << 4) /**< \brief (PMC_SCER) SMD Clock Enable */
#define PMC_SCER_UHP (0x1u << 6) /**< \brief (PMC_SCER) USB Host OHCI Clocks Enable */
#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Clock Enable */
#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
#define PMC_SCDR_PCK (0x1u << 0) /**< \brief (PMC_SCDR) Processor Clock Disable */
#define PMC_SCDR_DDRCK (0x1u << 2) /**< \brief (PMC_SCDR) DDR Clock Disable */
#define PMC_SCDR_SMDCK (0x1u << 4) /**< \brief (PMC_SCDR) SMD Clock Disable */
#define PMC_SCDR_UHP (0x1u << 6) /**< \brief (PMC_SCDR) USB Host OHCI Clock Disable */
#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Clock Enable */
#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
#define PMC_SCSR_PCK (0x1u << 0) /**< \brief (PMC_SCSR) Processor Clock Status */
#define PMC_SCSR_DDRCK (0x1u << 2) /**< \brief (PMC_SCSR) DDR Clock Status */
#define PMC_SCSR_SMDCK (0x1u << 4) /**< \brief (PMC_SCSR) SMD Clock Status */
#define PMC_SCSR_UHP (0x1u << 6) /**< \brief (PMC_SCSR) USB Host Port Clock Status */
#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */
#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
#define CKGR_UCKR_UPLLCOUNT_Pos 20
#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
#define CKGR_UCKR_BIASEN (0x1u << 24) /**< \brief (CKGR_UCKR) UTMI BIAS Enable */
#define CKGR_UCKR_BIASCOUNT_Pos 28
#define CKGR_UCKR_BIASCOUNT_Msk (0xfu << CKGR_UCKR_BIASCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI BIAS Start-up Time */
#define CKGR_UCKR_BIASCOUNT(value) ((CKGR_UCKR_BIASCOUNT_Msk & ((value) << CKGR_UCKR_BIASCOUNT_Pos)))
/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
#define CKGR_MOR_MOSCXTST_Pos 8
#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
#define CKGR_MOR_KEY_Pos 16
#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
#define CKGR_MCFR_MAINF_Pos 0
#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
#define CKGR_PLLAR_DIVA_Pos 0
#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider A */
#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
#define CKGR_PLLAR_PLLACOUNT_Pos 8
#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
#define CKGR_PLLAR_OUTA_Pos 14
#define CKGR_PLLAR_OUTA_Msk (0xfu << CKGR_PLLAR_OUTA_Pos) /**< \brief (CKGR_PLLAR) PLLA Clock Frequency Range */
#define CKGR_PLLAR_OUTA(value) ((CKGR_PLLAR_OUTA_Msk & ((value) << CKGR_PLLAR_OUTA_Pos)))
#define CKGR_PLLAR_MULA_Pos 18
#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
#define CKGR_PLLAR_STUCKTO1 (0x1u << 29) /**< \brief (CKGR_PLLAR)  */
/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
#define PMC_MCKR_CSS_Pos 0
#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master/Processor Clock Source Selection */
#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLACK/PLLADIV2 is selected */
#define   PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */
#define PMC_MCKR_PRES_Pos 4
#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Master/Processor Clock Prescaler */
#define   PMC_MCKR_PRES_CLOCK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
#define   PMC_MCKR_PRES_CLOCK_DIV2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
#define   PMC_MCKR_PRES_CLOCK_DIV4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
#define   PMC_MCKR_PRES_CLOCK_DIV8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
#define   PMC_MCKR_PRES_CLOCK_DIV16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
#define   PMC_MCKR_PRES_CLOCK_DIV32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
#define   PMC_MCKR_PRES_CLOCK_DIV64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
#define PMC_MCKR_MDIV_Pos 8
#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */
#define   PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1.Warning: SysClk DDR and DDRCK are not available. */
#define   PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */
#define   PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */
#define   PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */
#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA divisor by 2 */
#define   PMC_MCKR_PLLADIV2_NOT_DIV2 (0x0u << 12) /**< \brief (PMC_MCKR) PLLA clock frequency is divided by 1. */
#define   PMC_MCKR_PLLADIV2_DIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA clock frequency is divided by 2. */
/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB OHCI Input Clock Selection */
#define PMC_USB_USBDIV_Pos 8
#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB OHCI Clock. */
#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
/* -------- PMC_SMD : (PMC Offset: 0x003C) Soft Modem Clock Register -------- */
#define PMC_SMD_SMDS (0x1u << 0) /**< \brief (PMC_SMD) SMD input clock selection */
#define PMC_SMD_SMDDIV_Pos 8
#define PMC_SMD_SMDDIV_Msk (0x1fu << PMC_SMD_SMDDIV_Pos) /**< \brief (PMC_SMD) Divider for SMD Clock. */
#define PMC_SMD_SMDDIV(value) ((PMC_SMD_SMDDIV_Msk & ((value) << PMC_SMD_SMDDIV_Pos)))
/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
#define PMC_PCK_CSS_Pos 0
#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLACK/PLLADIV2 is selected */
#define   PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */
#define   PMC_PCK_CSS_MCK_CLK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
#define PMC_PCK_PRES_Pos 4
#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
#define   PMC_PCK_PRES_CLOCK (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
#define   PMC_PCK_PRES_CLOCK_DIV2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
#define   PMC_PCK_PRES_CLOCK_DIV4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
#define   PMC_PCK_PRES_CLOCK_DIV8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
#define   PMC_PCK_PRES_CLOCK_DIV16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
#define   PMC_PCK_PRES_CLOCK_DIV32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
#define   PMC_PCK_PRES_CLOCK_DIV64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Enable */
#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UPLL Clock Status */
#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
/* -------- PMC_PLLICPR : (PMC Offset: 0x0080) PLL Charge Pump Current Register -------- */
#define PMC_PLLICPR_ICPLLA (0x1u << 0) /**< \brief (PMC_PLLICPR) Charge Pump Current */
/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
#define PMC_WPMR_WPKEY_Pos 8
#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
#define PMC_WPSR_WPVSRC_Pos 8
#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
/* -------- PMC_PCER1 : (PMC Offset: 0x00100) Peripheral Clock Enable Register 1 -------- */
#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */
#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */
#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */
#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */
#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */
#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */
#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */
#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */
#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */
#define PMC_PCER1_PID53_Pos 20
#define PMC_PCER1_PID53_Msk (0x3u << PMC_PCER1_PID53_Pos) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */
#define PMC_PCER1_PID53(value) ((PMC_PCER1_PID53_Msk & ((value) << PMC_PCER1_PID53_Pos)))
#define PMC_PCER1_PID54 (0x1u << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */
#define PMC_PCER1_PID55 (0x1u << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */
#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */
#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */
#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */
#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */
#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */
#define PMC_PCER1_PID61 (0x1u << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */
#define PMC_PCER1_PID62 (0x1u << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */
#define PMC_PCER1_PID63 (0x1u << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */
/* -------- PMC_PCDR1 : (PMC Offset: 0x00104) Peripheral Clock Disable Register 1 -------- */
#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */
#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */
#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */
#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */
#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */
#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */
#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */
#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */
#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */
#define PMC_PCDR1_PID53_Pos 20
#define PMC_PCDR1_PID53_Msk (0x3u << PMC_PCDR1_PID53_Pos) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */
#define PMC_PCDR1_PID53(value) ((PMC_PCDR1_PID53_Msk & ((value) << PMC_PCDR1_PID53_Pos)))
#define PMC_PCDR1_PID54 (0x1u << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */
#define PMC_PCDR1_PID55 (0x1u << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */
#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */
#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */
#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */
#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */
#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */
#define PMC_PCDR1_PID61 (0x1u << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */
#define PMC_PCDR1_PID62 (0x1u << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */
#define PMC_PCDR1_PID63 (0x1u << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */
/* -------- PMC_PCSR1 : (PMC Offset: 0x00108) Peripheral Clock Status Register 1 -------- */
#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */
#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */
#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */
#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */
#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */
#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */
#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */
#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */
#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */
#define PMC_PCSR1_PID53_Pos 20
#define PMC_PCSR1_PID53_Msk (0x3u << PMC_PCSR1_PID53_Pos) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */
#define PMC_PCSR1_PID54 (0x1u << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */
#define PMC_PCSR1_PID55 (0x1u << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */
#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */
#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */
#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */
#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */
#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */
#define PMC_PCSR1_PID61 (0x1u << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */
#define PMC_PCSR1_PID62 (0x1u << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */
#define PMC_PCSR1_PID63 (0x1u << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */
/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
#define PMC_PCR_PID_Pos 0
#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */
#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */
#define PMC_PCR_DIV_Pos 16
#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */
#define   PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */
#define   PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */
#define   PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */
#define   PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/8 */
#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_PWM Pulse Width Modulation Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief PwmCh_num hardware registers */
typedef struct {
  RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
  RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
  RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
  RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
  RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
  RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
  RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
  RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
} PwmCh_num;
/** \brief PwmCmp hardware registers */
typedef struct {
  RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
  RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
  RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
  RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
} PwmCmp;
/** \brief Pwm hardware registers */
#define PWMCMP_NUMBER 8
#define PWMCH_NUM_NUMBER 4
typedef struct {
  RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
  WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
  WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
  RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
  WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
  WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
  RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
  RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
  RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
  RoReg      Reserved1[1];
  RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
  RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
  WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
  WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
  WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
  RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
  RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
  RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
  RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
  WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
  WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
  WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
  WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
  RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
  RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
  WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
  RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
  RwReg      PWM_FPE;       /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
  RoReg      Reserved2[3];
  RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
  RoReg      Reserved3[11];
  RwReg      PWM_SMMR;      /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
  RoReg      Reserved4[12];
  WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
  RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
  RoReg      Reserved5[17];
  PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
  RoReg      Reserved6[20];
  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
} Pwm;
#endif /* __ASSEMBLY__ */
/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
#define PWM_CLK_DIVA_Pos 0
#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
#define PWM_CLK_PREA_Pos 8
#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
#define PWM_CLK_DIVB_Pos 16
#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
#define PWM_CLK_PREB_Pos 24
#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
#define PWM_SCM_UPDM_Pos 16
#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
#define PWM_SCM_PTRCS_Pos 21
#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
#define PWM_SCUP_UPR_Pos 0
#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
#define PWM_SCUP_UPRCNT_Pos 4
#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
#define PWM_SCUPUPD_UPRUPD_Pos 0
#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
#define PWM_FMR_FPOL_Pos 0
#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to ) */
#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
#define PWM_FMR_FMOD_Pos 8
#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to ) */
#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
#define PWM_FMR_FFIL_Pos 16
#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to ) */
#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
#define PWM_FSR_FIV_Pos 0
#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to ) */
#define PWM_FSR_FS_Pos 8
#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to ) */
/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
#define PWM_FCR_FCLR_Pos 0
#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to ) */
#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
#define PWM_FPE_FPE0_Pos 0
#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to ) */
#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
#define PWM_FPE_FPE1_Pos 8
#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to ) */
#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
#define PWM_FPE_FPE2_Pos 16
#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to ) */
#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
#define PWM_FPE_FPE3_Pos 24
#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to ) */
#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
#define PWM_WPCR_WPCMD_Pos 0
#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
#define PWM_WPCR_WPKEY_Pos 8
#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
#define PWM_WPSR_WPVSRC_Pos 16
#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
#define PWM_CMPV_CV_Pos 0
#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
#define PWM_CMPVUPD_CVUPD_Pos 0
#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
#define PWM_CMPM_CTR_Pos 4
#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
#define PWM_CMPM_CPR_Pos 8
#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
#define PWM_CMPM_CPRCNT_Pos 12
#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
#define PWM_CMPM_CUPR_Pos 16
#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
#define PWM_CMPM_CUPRCNT_Pos 20
#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
#define PWM_CMPMUPD_CTRUPD_Pos 4
#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
#define PWM_CMPMUPD_CPRUPD_Pos 8
#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
#define PWM_CMPMUPD_CUPRUPD_Pos 16
#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
#define PWM_CMR_CPRE_Pos 0
#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
#define PWM_CDTY_CDTY_Pos 0
#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
#define PWM_CDTYUPD_CDTYUPD_Pos 0
#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
#define PWM_CPRD_CPRD_Pos 0
#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
#define PWM_CPRDUPD_CPRDUPD_Pos 0
#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
#define PWM_CCNT_CNT_Pos 0
#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
#define PWM_DT_DTH_Pos 0
#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
#define PWM_DT_DTL_Pos 16
#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
#define PWM_DTUPD_DTHUPD_Pos 0
#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
#define PWM_DTUPD_DTLUPD_Pos 16
#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Reset Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_RSTC Reset Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Rstc hardware registers */
typedef struct {
  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
} Rstc;
#endif /* __ASSEMBLY__ */
/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
#define RSTC_CR_KEY_Pos 24
#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
#define RSTC_SR_RSTTYP_Pos 8
#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
#define RSTC_MR_ERSTL_Pos 8
#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
#define RSTC_MR_KEY_Pos 24
#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Real-time Clock */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_RTC Real-time Clock */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Rtc hardware registers */
typedef struct {
  RwReg RTC_CR;     /**< \brief (Rtc Offset: 0x00) Control Register */
  RwReg RTC_MR;     /**< \brief (Rtc Offset: 0x04) Mode Register */
  RwReg RTC_TIMR;   /**< \brief (Rtc Offset: 0x08) Time Register */
  RwReg RTC_CALR;   /**< \brief (Rtc Offset: 0x0C) Calendar Register */
  RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
  RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
  RoReg RTC_SR;     /**< \brief (Rtc Offset: 0x18) Status Register */
  WoReg RTC_SCCR;   /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
  WoReg RTC_IER;    /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
  WoReg RTC_IDR;    /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
  RoReg RTC_IMR;    /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
  RoReg RTC_VER;    /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
} Rtc;
#endif /* __ASSEMBLY__ */
/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
#define RTC_CR_TIMEVSEL_Pos 8
#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
#define RTC_CR_CALEVSEL_Pos 16
#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
#define RTC_TIMR_SEC_Pos 0
#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
#define RTC_TIMR_MIN_Pos 8
#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
#define RTC_TIMR_HOUR_Pos 16
#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
#define RTC_CALR_CENT_Pos 0
#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
#define RTC_CALR_YEAR_Pos 8
#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
#define RTC_CALR_MONTH_Pos 16
#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
#define RTC_CALR_DAY_Pos 21
#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
#define RTC_CALR_DATE_Pos 24
#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
#define RTC_TIMALR_SEC_Pos 0
#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
#define RTC_TIMALR_MIN_Pos 8
#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
#define RTC_TIMALR_HOUR_Pos 16
#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
#define RTC_CALALR_MONTH_Pos 16
#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
#define RTC_CALALR_DATE_Pos 24
#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_RTT Real Time Timer */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Rtc hardware registers */
typedef struct {
  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
} Rtt;
#endif /* __ASSEMBLY__ */
/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
#define RTT_MR_RTPRES_Pos 0
#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
#define RTT_AR_ALMV_Pos 0
#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
#define RTT_VR_CRTV_Pos 0
#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Slow Clock Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_SCKC Slow Clock Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Sckc hardware registers */
typedef struct {
  RwReg SCKC_CR; /**< \brief (Sckc Offset: 0x0) Slow Clock Configuration Register */
} Sckc;
#endif /* __ASSEMBLY__ */
/* -------- SCKC_CR : (SCKC Offset: 0x0) Slow Clock Configuration Register -------- */
#define SCKC_CR_RCEN (0x1u << 0) /**< \brief (SCKC_CR) Internal 32 kHz RC Oscillator */
#define SCKC_CR_OSC32EN (0x1u << 1) /**< \brief (SCKC_CR) 32,768 Hz Oscillator */
#define SCKC_CR_OSC32BYP (0x1u << 2) /**< \brief (SCKC_CR) 32,768Hz Oscillator Bypass */
#define SCKC_CR_OSCSEL (0x1u << 3) /**< \brief (SCKC_CR) Slow Clock Selector */
#define   SCKC_CR_OSCSEL_RC (0x0u << 3) /**< \brief (SCKC_CR) Slow clock is internal 32 kHz RC oscillator. */
#define   SCKC_CR_OSCSEL_XTAL (0x1u << 3) /**< \brief (SCKC_CR) Slow clock is 32,768 Hz oscillator. */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Special Function Registers */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_SFR Special Function Registers */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Sfr hardware registers */
typedef struct {
  RoReg Reserved1[4];
  RwReg SFR_OHCIICR;    /**< \brief (Sfr Offset: 0x10) OHCI Interrupt Configuration Register */
  RoReg SFR_OHCIISR;    /**< \brief (Sfr Offset: 0x14) OHCI Interrupt Status Register */
  RoReg Reserved2[2];
  RwReg SFR_AHB;        /**< \brief (Sfr Offset: 0x20) AHB Configuration Register */
  RwReg SFR_BRIDGE;     /**< \brief (Sfr Offset: 0x24) Bridge Configuration Register */
  RwReg SFR_SECURE;     /**< \brief (Sfr Offset: 0x28) Security Configuration Register */
  RoReg Reserved3[1];
  RwReg SFR_UTMICKTRIM; /**< \brief (Sfr Offset: 0x30) UTMI Clock Trimming Register */
  RwReg SFR_UTMIHSTRIM; /**< \brief (Sfr Offset: 0x34) UTMI High Speed Trimming Register */
  RwReg SFR_UTMIFSTRIM; /**< \brief (Sfr Offset: 0x38) UTMI Full Speed Trimming Register */
  RwReg SFR_UTMISWAP;   /**< \brief (Sfr Offset: 0x3C) UTMI DP/DM Pin Swapping Register */
  RwReg SFR_EBICFG;     /**< \brief (Sfr Offset: 0x40) EBI Configuration Register */
} Sfr;
#endif /* __ASSEMBLY__ */
/* -------- SFR_OHCIICR : (SFR Offset: 0x10) OHCI Interrupt Configuration Register -------- */
#define SFR_OHCIICR_RES0 (0x1u << 0) /**< \brief (SFR_OHCIICR) USB PORTx RESET */
#define SFR_OHCIICR_RES1 (0x1u << 1) /**< \brief (SFR_OHCIICR) USB PORTx RESET */
#define SFR_OHCIICR_RES2 (0x1u << 2) /**< \brief (SFR_OHCIICR) USB PORTx RESET */
#define SFR_OHCIICR_ARIE (0x1u << 4) /**< \brief (SFR_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */
#define SFR_OHCIICR_APPSTART (0x1u << 5) /**< \brief (SFR_OHCIICR) Reserved */
#define SFR_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (SFR_OHCIICR) OHCI USB DEVICE PULL-UP DISABLE */
/* -------- SFR_OHCIISR : (SFR Offset: 0x14) OHCI Interrupt Status Register -------- */
#define SFR_OHCIISR_RIS0 (0x1u << 0) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 0 */
#define SFR_OHCIISR_RIS1 (0x1u << 1) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 1 */
#define SFR_OHCIISR_RIS2 (0x1u << 2) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 2 */
/* -------- SFR_AHB : (SFR Offset: 0x20) AHB Configuration Register -------- */
#define SFR_AHB_PFETCH10 (0x1u << 10) /**< \brief (SFR_AHB) AHB MASTERx 10 Converter Prefetch */
#define   SFR_AHB_PFETCH10_INCR4 (0x0u << 10) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 4 beats. */
#define   SFR_AHB_PFETCH10_INCR8 (0x1u << 10) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 8 beats. */
#define SFR_AHB_PFETCH11 (0x1u << 11) /**< \brief (SFR_AHB) AHB MASTERx 11 Converter Prefetch */
#define   SFR_AHB_PFETCH11_INCR4 (0x0u << 11) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 4 beats. */
#define   SFR_AHB_PFETCH11_INCR8 (0x1u << 11) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 8 beats. */
#define SFR_AHB_PFETCH12 (0x1u << 12) /**< \brief (SFR_AHB) AHB MASTERx 12 Converter Prefetch */
#define   SFR_AHB_PFETCH12_INCR4 (0x0u << 12) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 4 beats. */
#define   SFR_AHB_PFETCH12_INCR8 (0x1u << 12) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 8 beats. */
#define SFR_AHB_PFETCH13 (0x1u << 13) /**< \brief (SFR_AHB) AHB MASTERx 13 Converter Prefetch */
#define   SFR_AHB_PFETCH13_INCR4 (0x0u << 13) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 4 beats. */
#define   SFR_AHB_PFETCH13_INCR8 (0x1u << 13) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 8 beats. */
#define SFR_AHB_PFETCH14 (0x1u << 14) /**< \brief (SFR_AHB) AHB MASTERx 14 Converter Prefetch */
#define   SFR_AHB_PFETCH14_INCR4 (0x0u << 14) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 4 beats. */
#define   SFR_AHB_PFETCH14_INCR8 (0x1u << 14) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 8 beats. */
#define SFR_AHB_DLBOPT10 (0x1u << 26) /**< \brief (SFR_AHB) AHB MASTERx 10 Converter Define Length Burst Optimization */
#define SFR_AHB_DLBOPT11 (0x1u << 27) /**< \brief (SFR_AHB) AHB MASTERx 11 Converter Define Length Burst Optimization */
#define SFR_AHB_DLBOPT12 (0x1u << 28) /**< \brief (SFR_AHB) AHB MASTERx 12 Converter Define Length Burst Optimization */
#define SFR_AHB_DLBOPT13 (0x1u << 29) /**< \brief (SFR_AHB) AHB MASTERx 13 Converter Define Length Burst Optimization */
#define SFR_AHB_DLBOPT14 (0x1u << 30) /**< \brief (SFR_AHB) AHB MASTERx 14 Converter Define Length Burst Optimization */
/* -------- SFR_BRIDGE : (SFR Offset: 0x24) Bridge Configuration Register -------- */
#define SFR_BRIDGE_APBTURBO (0x1u << 0) /**< \brief (SFR_BRIDGE) AHB to APB Bridge mode */
#define SFR_BRIDGE_AXI2AHBSEL (0x1u << 8) /**< \brief (SFR_BRIDGE) AXI to AHB bridge for DDR controller selection */
#define   SFR_BRIDGE_AXI2AHBSEL_SINGLE (0x0u << 8) /**< \brief (SFR_BRIDGE) use single port bridge. */
#define   SFR_BRIDGE_AXI2AHBSEL_DUAL (0x1u << 8) /**< \brief (SFR_BRIDGE) use dual port bridge. */
/* -------- SFR_SECURE : (SFR Offset: 0x28) Security Configuration Register -------- */
#define SFR_SECURE_ROM (0x1u << 0) /**< \brief (SFR_SECURE) Disable Access to ROM Code */
#define SFR_SECURE_FUSE (0x1u << 8) /**< \brief (SFR_SECURE) Disable Access to Fuse Controller */
/* -------- SFR_UTMICKTRIM : (SFR Offset: 0x30) UTMI Clock Trimming Register -------- */
#define SFR_UTMICKTRIM_FREQ_Pos 0
#define SFR_UTMICKTRIM_FREQ_Msk (0x3u << SFR_UTMICKTRIM_FREQ_Pos) /**< \brief (SFR_UTMICKTRIM) UTMI Reference Clock Frequency */
#define   SFR_UTMICKTRIM_FREQ_12 (0x0u << 0) /**< \brief (SFR_UTMICKTRIM) 12 MHz reference clock */
#define   SFR_UTMICKTRIM_FREQ_16 (0x1u << 0) /**< \brief (SFR_UTMICKTRIM) 16 MHz reference clock */
#define   SFR_UTMICKTRIM_FREQ_24 (0x2u << 0) /**< \brief (SFR_UTMICKTRIM) 24 MHz reference clock */
#define   SFR_UTMICKTRIM_FREQ_48 (0x3u << 0) /**< \brief (SFR_UTMICKTRIM) 48 MHz reference clock */
#define SFR_UTMICKTRIM_VBG_Pos 16
#define SFR_UTMICKTRIM_VBG_Msk (0xfu << SFR_UTMICKTRIM_VBG_Pos) /**< \brief (SFR_UTMICKTRIM) UTMI Band Gap Voltage Trimming */
#define SFR_UTMICKTRIM_VBG(value) ((SFR_UTMICKTRIM_VBG_Msk & ((value) << SFR_UTMICKTRIM_VBG_Pos)))
/* -------- SFR_UTMIHSTRIM : (SFR Offset: 0x34) UTMI High Speed Trimming Register -------- */
#define SFR_UTMIHSTRIM_SQUELCH_Pos 0
#define SFR_UTMIHSTRIM_SQUELCH_Msk (0x7u << SFR_UTMIHSTRIM_SQUELCH_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS SQUELCH Voltage Trimming */
#define SFR_UTMIHSTRIM_SQUELCH(value) ((SFR_UTMIHSTRIM_SQUELCH_Msk & ((value) << SFR_UTMIHSTRIM_SQUELCH_Pos)))
#define SFR_UTMIHSTRIM_DISC_Pos 4
#define SFR_UTMIHSTRIM_DISC_Msk (0x7u << SFR_UTMIHSTRIM_DISC_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI Disconnect Voltage Trimming */
#define SFR_UTMIHSTRIM_DISC(value) ((SFR_UTMIHSTRIM_DISC_Msk & ((value) << SFR_UTMIHSTRIM_DISC_Pos)))
#define SFR_UTMIHSTRIM_SLOPE0_Pos 8
#define SFR_UTMIHSTRIM_SLOPE0_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE0_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */
#define SFR_UTMIHSTRIM_SLOPE0(value) ((SFR_UTMIHSTRIM_SLOPE0_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE0_Pos)))
#define SFR_UTMIHSTRIM_SLOPE1_Pos 12
#define SFR_UTMIHSTRIM_SLOPE1_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE1_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */
#define SFR_UTMIHSTRIM_SLOPE1(value) ((SFR_UTMIHSTRIM_SLOPE1_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE1_Pos)))
#define SFR_UTMIHSTRIM_SLOPE2_Pos 16
#define SFR_UTMIHSTRIM_SLOPE2_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE2_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */
#define SFR_UTMIHSTRIM_SLOPE2(value) ((SFR_UTMIHSTRIM_SLOPE2_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE2_Pos)))
/* -------- SFR_UTMIFSTRIM : (SFR Offset: 0x38) UTMI Full Speed Trimming Register -------- */
#define SFR_UTMIFSTRIM_RISE_Pos 0
#define SFR_UTMIFSTRIM_RISE_Msk (0x7u << SFR_UTMIFSTRIM_RISE_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver output rising slope trimming */
#define SFR_UTMIFSTRIM_RISE(value) ((SFR_UTMIFSTRIM_RISE_Msk & ((value) << SFR_UTMIFSTRIM_RISE_Pos)))
#define SFR_UTMIFSTRIM_FALL_Pos 4
#define SFR_UTMIFSTRIM_FALL_Msk (0x7u << SFR_UTMIFSTRIM_FALL_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver output falling slope trimming */
#define SFR_UTMIFSTRIM_FALL(value) ((SFR_UTMIFSTRIM_FALL_Msk & ((value) << SFR_UTMIFSTRIM_FALL_Pos)))
#define SFR_UTMIFSTRIM_XCVR_Pos 8
#define SFR_UTMIFSTRIM_XCVR_Msk (0x3u << SFR_UTMIFSTRIM_XCVR_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver crossover voltage trimming */
#define SFR_UTMIFSTRIM_XCVR(value) ((SFR_UTMIFSTRIM_XCVR_Msk & ((value) << SFR_UTMIFSTRIM_XCVR_Pos)))
#define SFR_UTMIFSTRIM_ZN_Pos 16
#define SFR_UTMIFSTRIM_ZN_Msk (0x7u << SFR_UTMIFSTRIM_ZN_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver NMOS impedance trimming */
#define SFR_UTMIFSTRIM_ZN(value) ((SFR_UTMIFSTRIM_ZN_Msk & ((value) << SFR_UTMIFSTRIM_ZN_Pos)))
#define SFR_UTMIFSTRIM_ZP_Pos 20
#define SFR_UTMIFSTRIM_ZP_Msk (0x7u << SFR_UTMIFSTRIM_ZP_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver PMOS impedance trimming */
#define SFR_UTMIFSTRIM_ZP(value) ((SFR_UTMIFSTRIM_ZP_Msk & ((value) << SFR_UTMIFSTRIM_ZP_Pos)))
/* -------- SFR_UTMISWAP : (SFR Offset: 0x3C) UTMI DP/DM Pin Swapping Register -------- */
#define SFR_UTMISWAP_PORT0 (0x1u << 0) /**< \brief (SFR_UTMISWAP) PORT 0 DP/DM Pin Swapping */
#define   SFR_UTMISWAP_PORT0_NORMAL (0x0u << 0) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */
#define   SFR_UTMISWAP_PORT0_SWAPPED (0x1u << 0) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */
#define SFR_UTMISWAP_PORT1 (0x1u << 1) /**< \brief (SFR_UTMISWAP) PORT 1 DP/DM Pin Swapping */
#define   SFR_UTMISWAP_PORT1_NORMAL (0x0u << 1) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */
#define   SFR_UTMISWAP_PORT1_SWAPPED (0x1u << 1) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */
#define SFR_UTMISWAP_PORT2 (0x1u << 2) /**< \brief (SFR_UTMISWAP) PORT 2 DP/DM Pin Swapping */
#define   SFR_UTMISWAP_PORT2_NORMAL (0x0u << 2) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */
#define   SFR_UTMISWAP_PORT2_SWAPPED (0x1u << 2) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */
/* -------- SFR_EBICFG : (SFR Offset: 0x40) EBI Configuration Register -------- */
#define SFR_EBICFG_DRIVE0_Pos 0
#define SFR_EBICFG_DRIVE0_Msk (0x3u << SFR_EBICFG_DRIVE0_Pos) /**< \brief (SFR_EBICFG) EBI Pins Drive Level */
#define   SFR_EBICFG_DRIVE0_LOW (0x0u << 0) /**< \brief (SFR_EBICFG) Low drive level */
#define   SFR_EBICFG_DRIVE0_MEDIUM (0x2u << 0) /**< \brief (SFR_EBICFG) Medium drive level */
#define   SFR_EBICFG_DRIVE0_HIGH (0x3u << 0) /**< \brief (SFR_EBICFG) High drive level */
#define SFR_EBICFG_PULL0_Pos 2
#define SFR_EBICFG_PULL0_Msk (0x3u << SFR_EBICFG_PULL0_Pos) /**< \brief (SFR_EBICFG) EBI Pins Pull Value */
#define   SFR_EBICFG_PULL0_UP (0x0u << 2) /**< \brief (SFR_EBICFG) Pull-up */
#define   SFR_EBICFG_PULL0_NONE (0x1u << 2) /**< \brief (SFR_EBICFG) No Pull */
#define   SFR_EBICFG_PULL0_DOWN (0x3u << 2) /**< \brief (SFR_EBICFG) Pull-down */
#define SFR_EBICFG_SCH0 (0x1u << 4) /**< \brief (SFR_EBICFG) EBI Pins Schmitt Trigger */
#define SFR_EBICFG_DRIVE1_Pos 8
#define SFR_EBICFG_DRIVE1_Msk (0x3u << SFR_EBICFG_DRIVE1_Pos) /**< \brief (SFR_EBICFG) EBI Pins Drive Level */
#define   SFR_EBICFG_DRIVE1_LOW (0x0u << 8) /**< \brief (SFR_EBICFG) Low drive level */
#define   SFR_EBICFG_DRIVE1_MEDIUM (0x2u << 8) /**< \brief (SFR_EBICFG) Medium drive level */
#define   SFR_EBICFG_DRIVE1_HIGH (0x3u << 8) /**< \brief (SFR_EBICFG) High drive level */
#define SFR_EBICFG_PULL1_Pos 10
#define SFR_EBICFG_PULL1_Msk (0x3u << SFR_EBICFG_PULL1_Pos) /**< \brief (SFR_EBICFG) EBI Pins Pull Value */
#define   SFR_EBICFG_PULL1_UP (0x0u << 10) /**< \brief (SFR_EBICFG) Pull-up */
#define   SFR_EBICFG_PULL1_NONE (0x1u << 10) /**< \brief (SFR_EBICFG) No Pull */
#define   SFR_EBICFG_PULL1_DOWN (0x3u << 10) /**< \brief (SFR_EBICFG) Pull-down */
#define SFR_EBICFG_SCH1 (0x1u << 12) /**< \brief (SFR_EBICFG) EBI Pins Schmitt Trigger */
#define SFR_EBICFG_BMS (0x1u << 16) /**< \brief (SFR_EBICFG) BMS Sampled Value (Read Only) */
#define   SFR_EBICFG_BMS_ROM (0x0u << 16) /**< \brief (SFR_EBICFG) Boot on ROM. */
#define   SFR_EBICFG_BMS_EBI (0x1u << 16) /**< \brief (SFR_EBICFG) Boot on EBI. */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Secure Hash Algorithm */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_SHA Secure Hash Algorithm */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Sha hardware registers */
typedef struct {
  WoReg SHA_CR;          /**< \brief (Sha Offset: 0x00) Control Register */
  RwReg SHA_MR;          /**< \brief (Sha Offset: 0x04) Mode Register */
  RoReg Reserved1[2];
  WoReg SHA_IER;         /**< \brief (Sha Offset: 0x10) Interrupt Enable Register */
  WoReg SHA_IDR;         /**< \brief (Sha Offset: 0x14) Interrupt Disable Register */
  RoReg SHA_IMR;         /**< \brief (Sha Offset: 0x18) Interrupt Mask Register */
  RoReg SHA_ISR;         /**< \brief (Sha Offset: 0x1C) Interrupt Status Register */
  RoReg Reserved2[8];
  WoReg SHA_IDATAR[16];  /**< \brief (Sha Offset: 0x40) Input Data 0 Register */
  RwReg SHA_IODATAR[16]; /**< \brief (Sha Offset: 0x80) Input/Output Data 0 Register */
} Sha;
#endif /* __ASSEMBLY__ */
/* -------- SHA_CR : (SHA Offset: 0x00) Control Register -------- */
#define SHA_CR_START (0x1u << 0) /**< \brief (SHA_CR) Start Processing */
#define SHA_CR_FIRST (0x1u << 4) /**< \brief (SHA_CR) First Block of a Message */
#define SHA_CR_SWRST (0x1u << 8) /**< \brief (SHA_CR) Software Reset */
/* -------- SHA_MR : (SHA Offset: 0x04) Mode Register -------- */
#define SHA_MR_SMOD_Pos 0
#define SHA_MR_SMOD_Msk (0x3u << SHA_MR_SMOD_Pos) /**< \brief (SHA_MR) Start Mode */
#define   SHA_MR_SMOD_MANUAL_START (0x0u << 0) /**< \brief (SHA_MR) Manual Mode */
#define   SHA_MR_SMOD_AUTO_START (0x1u << 0) /**< \brief (SHA_MR) Auto Mode */
#define   SHA_MR_SMOD_IDATAR0_START (0x2u << 0) /**< \brief (SHA_MR) SHA_IDATAR0 access only Auto Mode */
#define SHA_MR_PROCDLY (0x1u << 4) /**< \brief (SHA_MR) Processing Delay */
#define   SHA_MR_PROCDLY_SHORTEST (0x0u << 4) /**< \brief (SHA_MR) SHA processing runtime is the shortest one */
#define   SHA_MR_PROCDLY_LONGEST (0x1u << 4) /**< \brief (SHA_MR) SHA processing runtime is the longest one */
#define SHA_MR_ALGO_Pos 8
#define SHA_MR_ALGO_Msk (0x7u << SHA_MR_ALGO_Pos) /**< \brief (SHA_MR) SHA Algorithm. */
#define   SHA_MR_ALGO_SHA1 (0x0u << 8) /**< \brief (SHA_MR) SHA1 algorithm processed */
#define   SHA_MR_ALGO_SHA256 (0x1u << 8) /**< \brief (SHA_MR) SHA256 algorithm processed */
#define   SHA_MR_ALGO_SHA384 (0x2u << 8) /**< \brief (SHA_MR) SHA384 algorithm processed */
#define   SHA_MR_ALGO_SHA512 (0x3u << 8) /**< \brief (SHA_MR) SHA512 algorithm processed */
#define   SHA_MR_ALGO_SHA224 (0x4u << 8) /**< \brief (SHA_MR) SHA224 algorithm processed */
#define SHA_MR_DUALBUFF (0x1u << 16) /**< \brief (SHA_MR) Dual Input BUFFer */
#define   SHA_MR_DUALBUFF_INACTIVE (0x0u << 16) /**< \brief (SHA_MR) SHA_IDATARx and SHA_IODATARx cannot be written during processing of previous block. */
#define   SHA_MR_DUALBUFF_ACTIVE (0x1u << 16) /**< \brief (SHA_MR) SHA_IDATARx and SHA_IODATARx can be written during processing of previous block when SMOD=0x2. It speeds up the overall runtime of large files. */
/* -------- SHA_IER : (SHA Offset: 0x10) Interrupt Enable Register -------- */
#define SHA_IER_DATRDY (0x1u << 0) /**< \brief (SHA_IER) Data Ready Interrupt Enable */
#define SHA_IER_URAD (0x1u << 8) /**< \brief (SHA_IER) Unspecified Register Access Detection Interrupt Enable */
/* -------- SHA_IDR : (SHA Offset: 0x14) Interrupt Disable Register -------- */
#define SHA_IDR_DATRDY (0x1u << 0) /**< \brief (SHA_IDR) Data Ready Interrupt Disable */
#define SHA_IDR_URAD (0x1u << 8) /**< \brief (SHA_IDR) Unspecified Register Access Detection Interrupt Disable */
/* -------- SHA_IMR : (SHA Offset: 0x18) Interrupt Mask Register -------- */
#define SHA_IMR_DATRDY (0x1u << 0) /**< \brief (SHA_IMR) Data Ready Interrupt Mask */
#define SHA_IMR_URAD (0x1u << 8) /**< \brief (SHA_IMR) Unspecified Register Access Detection Interrupt Mask */
/* -------- SHA_ISR : (SHA Offset: 0x1C) Interrupt Status Register -------- */
#define SHA_ISR_DATRDY (0x1u << 0) /**< \brief (SHA_ISR) Data Ready */
#define SHA_ISR_URAD (0x1u << 8) /**< \brief (SHA_ISR) Unspecified Register Access Detection Status */
#define SHA_ISR_URAT_Pos 12
#define SHA_ISR_URAT_Msk (0x7u << SHA_ISR_URAT_Pos) /**< \brief (SHA_ISR) Unspecified Register Access Type */
/* -------- SHA_IDATAR[16] : (SHA Offset: 0x40) Input Data 0 Register -------- */
#define SHA_IDATAR_IDATA_Pos 0
#define SHA_IDATAR_IDATA_Msk (0xffffffffu << SHA_IDATAR_IDATA_Pos) /**< \brief (SHA_IDATAR[16]) Input Data */
#define SHA_IDATAR_IDATA(value) ((SHA_IDATAR_IDATA_Msk & ((value) << SHA_IDATAR_IDATA_Pos)))
/* -------- SHA_IODATAR[16] : (SHA Offset: 0x80) Input/Output Data 0 Register -------- */
#define SHA_IODATAR_IODATA_Pos 0
#define SHA_IODATAR_IODATA_Msk (0xffffffffu << SHA_IODATAR_IODATA_Pos) /**< \brief (SHA_IODATAR[16]) Input/Output Data */
#define SHA_IODATAR_IODATA(value) ((SHA_IODATAR_IODATA_Msk & ((value) << SHA_IODATAR_IODATA_Pos)))

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Shutdown Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_SHDWC Shutdown Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Shdwc hardware registers */
typedef struct {
  WoReg SHDW_CR; /**< \brief (Shdwc Offset: 0x00) Shutdown Control Register */
  RwReg SHDW_MR; /**< \brief (Shdwc Offset: 0x04) Shutdown Mode Register */
  RoReg SHDW_SR; /**< \brief (Shdwc Offset: 0x08) Shutdown Status Register */
} Shdwc;
#endif /* __ASSEMBLY__ */
/* -------- SHDW_CR : (SHDWC Offset: 0x00) Shutdown Control Register -------- */
#define SHDW_CR_SHDW (0x1u << 0) /**< \brief (SHDW_CR) Shutdown Command */
#define SHDW_CR_KEY_Pos 24
#define SHDW_CR_KEY_Msk (0xffu << SHDW_CR_KEY_Pos) /**< \brief (SHDW_CR) Password */
#define SHDW_CR_KEY(value) ((SHDW_CR_KEY_Msk & ((value) << SHDW_CR_KEY_Pos)))
/* -------- SHDW_MR : (SHDWC Offset: 0x04) Shutdown Mode Register -------- */
#define SHDW_MR_WKMODE0_Pos 0
#define SHDW_MR_WKMODE0_Msk (0x3u << SHDW_MR_WKMODE0_Pos) /**< \brief (SHDW_MR) Wake-up Mode 0 */
#define SHDW_MR_WKMODE0(value) ((SHDW_MR_WKMODE0_Msk & ((value) << SHDW_MR_WKMODE0_Pos)))
#define SHDW_MR_CPTWK0_Pos 4
#define SHDW_MR_CPTWK0_Msk (0xfu << SHDW_MR_CPTWK0_Pos) /**< \brief (SHDW_MR) Counter on Wake-up 0 */
#define SHDW_MR_CPTWK0(value) ((SHDW_MR_CPTWK0_Msk & ((value) << SHDW_MR_CPTWK0_Pos)))
#define SHDW_MR_WKMODE1_Pos 8
#define SHDW_MR_WKMODE1_Msk (0x3u << SHDW_MR_WKMODE1_Pos) /**< \brief (SHDW_MR)  */
#define SHDW_MR_WKMODE1(value) ((SHDW_MR_WKMODE1_Msk & ((value) << SHDW_MR_WKMODE1_Pos)))
#define SHDW_MR_CPTWK1_Pos 12
#define SHDW_MR_CPTWK1_Msk (0xfu << SHDW_MR_CPTWK1_Pos) /**< \brief (SHDW_MR)  */
#define SHDW_MR_CPTWK1(value) ((SHDW_MR_CPTWK1_Msk & ((value) << SHDW_MR_CPTWK1_Pos)))
#define SHDW_MR_RTTWKEN (0x1u << 16) /**< \brief (SHDW_MR)  */
#define SHDW_MR_RTCWKEN (0x1u << 17) /**< \brief (SHDW_MR) Real-time Clock Wake-up Enable */
/* -------- SHDW_SR : (SHDWC Offset: 0x08) Shutdown Status Register -------- */
#define SHDW_SR_WAKEUP0 (0x1u << 0) /**< \brief (SHDW_SR) Wake-up 0 Status */
#define SHDW_SR_WAKEUP1 (0x1u << 1) /**< \brief (SHDW_SR)  */
#define SHDW_SR_FWKUP (0x1u << 2) /**< \brief (SHDW_SR)  */
#define SHDW_SR_RTTWK (0x1u << 16) /**< \brief (SHDW_SR)  */
#define SHDW_SR_RTCWK (0x1u << 17) /**< \brief (SHDW_SR) Real-time Clock Wake-up */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_SMC Static Memory Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief SmcCs_number hardware registers */
typedef struct {
  RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
  RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
  RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
  RwReg         SMC_TIMINGS;      /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */
  RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */
} SmcCs_number;
/** \brief SmcPmecc hardware registers */
typedef struct {
  RwReg         SMC_PMECC[11];    /**< \brief (SmcPmecc Offset: 0x0) PMECC Redundancy x Register */
  RoReg         Reserved1[5];
} SmcPmecc;
/** \brief SmcRem hardware registers */
typedef struct {
  RwReg         SMC_REM[12];      /**< \brief (SmcRem Offset: 0x0) PMECC Remainder x Register */
  RoReg         Reserved2[4];
} SmcRem;
/** \brief Smc hardware registers */
#define SMCPMECC_NUMBER 8
#define SMCREM_NUMBER 8
#define SMCCS_NUMBER_NUMBER 4
typedef struct {
  RwReg         SMC_CFG;          /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */
  WoReg         SMC_CTRL;         /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */
  RoReg         SMC_SR;           /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */
  WoReg         SMC_IER;          /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */
  WoReg         SMC_IDR;          /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */
  RoReg         SMC_IMR;          /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */
  RwReg         SMC_ADDR;         /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */
  RwReg         SMC_BANK;         /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */
  WoReg         SMC_ECC_CTRL;     /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */
  RwReg         SMC_ECC_MD;       /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */
  RoReg         SMC_ECC_SR1;      /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */
  RoReg         SMC_ECC_PR0;      /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */
  RoReg         SMC_ECC_PR1;      /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */
  RoReg         SMC_ECC_SR2;      /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */
  RoReg         SMC_ECC_PR2;      /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */
  RoReg         SMC_ECC_PR3;      /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */
  RoReg         SMC_ECC_PR4;      /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */
  RoReg         SMC_ECC_PR5;      /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */
  RoReg         SMC_ECC_PR6;      /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */
  RoReg         SMC_ECC_PR7;      /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */
  RoReg         SMC_ECC_PR8;      /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */
  RoReg         SMC_ECC_PR9;      /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */
  RoReg         SMC_ECC_PR10;     /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */
  RoReg         SMC_ECC_PR11;     /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */
  RoReg         SMC_ECC_PR12;     /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */
  RoReg         SMC_ECC_PR13;     /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */
  RoReg         SMC_ECC_PR14;     /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */
  RoReg         SMC_ECC_PR15;     /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */
  RwReg         SMC_PMECCFG;      /**< \brief (Smc Offset: 0x70) PMECC Configuration Register */
  RwReg         SMC_PMECCSAREA;   /**< \brief (Smc Offset: 0x74) PMECC Spare Area Size Register */
  RwReg         SMC_PMECCSADDR;   /**< \brief (Smc Offset: 0x78) PMECC Start Address Register */
  RwReg         SMC_PMECCEADDR;   /**< \brief (Smc Offset: 0x7C) PMECC End Address Register */
  RoReg         Reserved1[1];
  WoReg         SMC_PMECCTRL;     /**< \brief (Smc Offset: 0x84) PMECC Control Register */
  RoReg         SMC_PMECCSR;      /**< \brief (Smc Offset: 0x88) PMECC Status Register */
  WoReg         SMC_PMECCIER;     /**< \brief (Smc Offset: 0x8C) PMECC Interrupt Enable register */
  WoReg         SMC_PMECCIDR;     /**< \brief (Smc Offset: 0x90) PMECC Interrupt Disable Register */
  RoReg         SMC_PMECCIMR;     /**< \brief (Smc Offset: 0x94) PMECC Interrupt Mask Register */
  RoReg         SMC_PMECCISR;     /**< \brief (Smc Offset: 0x98) PMECC Interrupt Status Register */
  RoReg         Reserved2[5];
  SmcPmecc      SMC_PMECC[SMCPMECC_NUMBER]; /**< \brief (Smc Offset: 0xB0) sec_num = 0 .. 7 */
  SmcRem        SMC_REM[SMCREM_NUMBER]; /**< \brief (Smc Offset: 0x2B0) sec_num = 0 .. 7 */
  RoReg         Reserved3[20];
  RwReg         SMC_ELCFG;        /**< \brief (Smc Offset: 0x500) PMECCError Location Configuration Register */
  RoReg         SMC_ELPRIM;       /**< \brief (Smc Offset: 0x504) PMECC Error Location Primitive Register */
  WoReg         SMC_ELEN;         /**< \brief (Smc Offset: 0x508) PMECC Error Location Enable Register */
  WoReg         SMC_ELDIS;        /**< \brief (Smc Offset: 0x50C) PMECC Error Location Disable Register */
  RoReg         SMC_ELSR;         /**< \brief (Smc Offset: 0x510) PMECC Error Location Status Register */
  WoReg         SMC_ELIER;        /**< \brief (Smc Offset: 0x514) PMECC Error Location Interrupt Enable register */
  WoReg         SMC_ELIDR;        /**< \brief (Smc Offset: 0x518) PMECC Error Location Interrupt Disable Register */
  RoReg         SMC_ELIMR;        /**< \brief (Smc Offset: 0x51C) PMECC Error Location Interrupt Mask Register */
  RoReg         SMC_ELISR;        /**< \brief (Smc Offset: 0x520) PMECC Error Location Interrupt Status Register */
  RoReg         Reserved4[1];
  RwReg         SMC_SIGMA0;       /**< \brief (Smc Offset: 0x528) PMECC Error Location SIGMA 0 Register */
  RwReg         SMC_SIGMA1;       /**< \brief (Smc Offset: 0x52C) PMECC Error Location SIGMA 1 Register */
  RwReg         SMC_SIGMA2;       /**< \brief (Smc Offset: 0x530) PMECC Error Location SIGMA 2 Register */
  RwReg         SMC_SIGMA3;       /**< \brief (Smc Offset: 0x534) PMECC Error Location SIGMA 3 Register */
  RwReg         SMC_SIGMA4;       /**< \brief (Smc Offset: 0x538) PMECC Error Location SIGMA 4 Register */
  RwReg         SMC_SIGMA5;       /**< \brief (Smc Offset: 0x53C) PMECC Error Location SIGMA 5 Register */
  RwReg         SMC_SIGMA6;       /**< \brief (Smc Offset: 0x540) PMECC Error Location SIGMA 6 Register */
  RwReg         SMC_SIGMA7;       /**< \brief (Smc Offset: 0x544) PMECC Error Location SIGMA 7 Register */
  RwReg         SMC_SIGMA8;       /**< \brief (Smc Offset: 0x548) PMECC Error Location SIGMA 8 Register */
  RwReg         SMC_SIGMA9;       /**< \brief (Smc Offset: 0x54C) PMECC Error Location SIGMA 9 Register */
  RwReg         SMC_SIGMA10;      /**< \brief (Smc Offset: 0x550) PMECC Error Location SIGMA 10 Register */
  RwReg         SMC_SIGMA11;      /**< \brief (Smc Offset: 0x554) PMECC Error Location SIGMA 11 Register */
  RwReg         SMC_SIGMA12;      /**< \brief (Smc Offset: 0x558) PMECC Error Location SIGMA 12 Register */
  RwReg         SMC_SIGMA13;      /**< \brief (Smc Offset: 0x55C) PMECC Error Location SIGMA 13 Register */
  RwReg         SMC_SIGMA14;      /**< \brief (Smc Offset: 0x560) PMECC Error Location SIGMA 14 Register */
  RwReg         SMC_SIGMA15;      /**< \brief (Smc Offset: 0x564) PMECC Error Location SIGMA 15 Register */
  RwReg         SMC_SIGMA16;      /**< \brief (Smc Offset: 0x568) PMECC Error Location SIGMA 16 Register */
  RwReg         SMC_SIGMA17;      /**< \brief (Smc Offset: 0x56C) PMECC Error Location SIGMA 17 Register */
  RwReg         SMC_SIGMA18;      /**< \brief (Smc Offset: 0x570) PMECC Error Location SIGMA 18 Register */
  RwReg         SMC_SIGMA19;      /**< \brief (Smc Offset: 0x574) PMECC Error Location SIGMA 19 Register */
  RwReg         SMC_SIGMA20;      /**< \brief (Smc Offset: 0x578) PMECC Error Location SIGMA 20 Register */
  RwReg         SMC_SIGMA21;      /**< \brief (Smc Offset: 0x57C) PMECC Error Location SIGMA 21 Register */
  RwReg         SMC_SIGMA22;      /**< \brief (Smc Offset: 0x580) PMECC Error Location SIGMA 22 Register */
  RwReg         SMC_SIGMA23;      /**< \brief (Smc Offset: 0x584) PMECC Error Location SIGMA 23 Register */
  RwReg         SMC_SIGMA24;      /**< \brief (Smc Offset: 0x588) PMECC Error Location SIGMA 24 Register */
  RoReg         SMC_ERRLOC[24];   /**< \brief (Smc Offset: 0x58C) PMECC Error Location 0 Register */
  RoReg         Reserved5[5];
  SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x600) CS_number = 0 .. 3 */
  RoReg         Reserved6[20];
  RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x6A0) SMC OCMS Register */
  WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x6A4) SMC OCMS KEY1 Register */
  WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x6A8) SMC OCMS KEY2 Register */
  RoReg         Reserved7[14];
  WoReg         SMC_WPCR;         /**< \brief (Smc Offset: 0x6E4) SMC Write Protection Control Register */
  RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0x6E8) SMC Write Protection Status Register */
} Smc;
#endif /* __ASSEMBLY__ */
/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */
#define SMC_CFG_PAGESIZE_Pos 0
#define SMC_CFG_PAGESIZE_Msk (0x7u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG)  */
#define   SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
#define   SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
#define   SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
#define   SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */
#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */
#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */
#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */
#define SMC_CFG_DTOCYC_Pos 16
#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */
#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos)))
#define SMC_CFG_DTOMUL_Pos 20
#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */
#define   SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */
#define   SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */
#define   SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */
#define   SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */
#define   SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */
#define   SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */
#define   SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */
#define   SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */
#define SMC_CFG_NFCSPARESIZE_Pos 24
#define SMC_CFG_NFCSPARESIZE_Msk (0x7fu << SMC_CFG_NFCSPARESIZE_Pos) /**< \brief (SMC_CFG) NAND Flash Spare Area Size Retrieved by the Host Controller */
#define SMC_CFG_NFCSPARESIZE(value) ((SMC_CFG_NFCSPARESIZE_Msk & ((value) << SMC_CFG_NFCSPARESIZE_Pos)))
/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */
#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */
#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */
/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */
#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller Status (this field cannot be reset) */
#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */
#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */
#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */
#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */
#define SMC_SR_NFCSID_Pos 12
#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */
#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */
#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */
#define SMC_SR_ECCRDY (0x1u << 18) /**< \brief (SMC_SR) Hamming ECC Ready */
#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */
#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */
#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */
#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */
#define SMC_SR_RB_EDGE3 (0x1u << 27) /**< \brief (SMC_SR) Ready/Busy Line 3 Edge Detected */
/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */
#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */
#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */
#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */
#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */
#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */
#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */
#define SMC_IER_RB_EDGE3 (0x1u << 27) /**< \brief (SMC_IER) Ready/Busy Line 3 Interrupt Enable */
/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */
#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */
#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */
#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */
#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */
#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */
#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */
#define SMC_IDR_RB_EDGE3 (0x1u << 27) /**< \brief (SMC_IDR) Ready/Busy Line 3 Interrupt Disable */
/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */
#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */
#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */
#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */
#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */
#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */
#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */
#define SMC_IMR_RB_EDGE3 (0x1u << 27) /**< \brief (SMC_IMR) Ready/Busy Line 3 Interrupt Mask */
/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */
#define SMC_ADDR_ADDR_CYCLE0_Pos 0
#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address Cycle 0 */
#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos)))
/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */
#define SMC_BANK_BANK (0x1u << 0) /**< \brief (SMC_BANK) Bank Identifier */
/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */
#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */
#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */
/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */
#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0
#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */
#define   SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
#define   SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
#define   SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
#define   SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
#define SMC_ECC_MD_TYPCORREC_Pos 4
#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */
#define   SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes  (for 8 or 16-bit NAND Flash) */
#define   SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
#define   SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
#define SMC_ECC_MD_HAMMING (0x1u << 8) /**< \brief (SMC_ECC_MD) Hamming Error Correcting Code Selected */
/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */
#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */
#define SMC_ECC_SR1_ECCERR0_Pos 1
#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */
#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th Bytes or the 512nd and the 1023rd Bytes */
#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th Bytes or between the 512nd and the 1023rd Bytes */
#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th Bytes or between the 512nd and the 1023rd Bytes */
#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th Bytes or between the 1024th and the 1535th Bytes */
#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th Bytes or between the 1024th and the 1535th Bytes */
#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th Bytes or between the 1024th and the 1535th Bytes */
#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd Bytes or between the 1536th and the 2047th Bytes */
#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd Bytes or between the 1536th and the 2047th Bytes */
#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd Bytes or between the 1536th and the 2047th Bytes */
#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th Bytes or between the 2048th and the 2559th Bytes */
#define SMC_ECC_SR1_ECCERR4_Pos 17
#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th Bytes or between the 2048th and the 2559th Bytes */
#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th Bytes or between the 2560th and the 3071st Bytes */
#define SMC_ECC_SR1_ECCERR5_Pos 21
#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th Bytes or between the 2560th and the 3071st Bytes */
#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st Bytes or between the 3072nd and the 3583rd Bytes */
#define SMC_ECC_SR1_ECCERR6_Pos 25
#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st Bytes or between the 3072nd and the 3583rd Bytes */
#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th Bytes or between the 3584th and the 4095th Bytes */
#define SMC_ECC_SR1_ECCERR7_Pos 29
#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th Bytes or between the 3584th and the 4095th Bytes */
/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */
#define SMC_ECC_PR0_BITADDR_Pos 0
#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */
#define SMC_ECC_PR0_WORDADDR_Pos 4
#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */
/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */
#define SMC_ECC_PR1_NPARITY_Pos 0
#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */
#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd Bytes */
#define SMC_ECC_SR2_ECCERR8_Pos 1
#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd Bytes */
#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th Bytes */
#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th Bytes */
#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th Bytes */
#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th Bytes */
#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th Bytes */
#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th Bytes */
#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st Bytes */
#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st Bytes */
#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st Bytes */
#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th Bytes */
#define SMC_ECC_SR2_ECCERR12_Pos 17
#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th Bytes */
#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd Bytes */
#define SMC_ECC_SR2_ECCERR13_Pos 21
#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd Bytes */
#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th Bytes */
#define SMC_ECC_SR2_ECCERR14_Pos 25
#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th Bytes */
#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th Bytes */
#define SMC_ECC_SR2_ECCERR15_Pos 29
#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th Bytes */
/* -------- SMC_PMECCFG : (SMC Offset: 0x70) PMECC Configuration Register -------- */
#define SMC_PMECCFG_BCH_ERR_Pos 0
#define SMC_PMECCFG_BCH_ERR_Msk (0x7u << SMC_PMECCFG_BCH_ERR_Pos) /**< \brief (SMC_PMECCFG) Error Correcting Capability */
#define   SMC_PMECCFG_BCH_ERR_BCH_ERR2 (0x0u << 0) /**< \brief (SMC_PMECCFG) 2 errors */
#define   SMC_PMECCFG_BCH_ERR_BCH_ERR4 (0x1u << 0) /**< \brief (SMC_PMECCFG) 4 errors */
#define   SMC_PMECCFG_BCH_ERR_BCH_ERR8 (0x2u << 0) /**< \brief (SMC_PMECCFG) 8 errors */
#define   SMC_PMECCFG_BCH_ERR_BCH_ERR12 (0x3u << 0) /**< \brief (SMC_PMECCFG) 12 errors */
#define   SMC_PMECCFG_BCH_ERR_BCH_ERR24 (0x4u << 0) /**< \brief (SMC_PMECCFG) 24 errors */
#define SMC_PMECCFG_SECTORSZ (0x1u << 4) /**< \brief (SMC_PMECCFG) Sector Size */
#define SMC_PMECCFG_PAGESIZE_Pos 8
#define SMC_PMECCFG_PAGESIZE_Msk (0x3u << SMC_PMECCFG_PAGESIZE_Pos) /**< \brief (SMC_PMECCFG) Number of Sectors in the Page */
#define   SMC_PMECCFG_PAGESIZE_PAGESIZE_1SEC (0x0u << 8) /**< \brief (SMC_PMECCFG) 1 sector for main area (512 or 1024 Bytes) */
#define   SMC_PMECCFG_PAGESIZE_PAGESIZE_2SEC (0x1u << 8) /**< \brief (SMC_PMECCFG) 2 sectors for main area (1024 or 2048 Bytes) */
#define   SMC_PMECCFG_PAGESIZE_PAGESIZE_4SEC (0x2u << 8) /**< \brief (SMC_PMECCFG) 4 sectors for main area (2048 or 4096 Bytes) */
#define   SMC_PMECCFG_PAGESIZE_PAGESIZE_8SEC (0x3u << 8) /**< \brief (SMC_PMECCFG) 8 sectors for main area (4096 or 8192 Bytes) */
#define SMC_PMECCFG_NANDWR (0x1u << 12) /**< \brief (SMC_PMECCFG) NAND Write Access */
#define SMC_PMECCFG_SPAREEN (0x1u << 16) /**< \brief (SMC_PMECCFG) Spare Enable */
#define SMC_PMECCFG_AUTO (0x1u << 20) /**< \brief (SMC_PMECCFG) Automatic Mode Enable */
/* -------- SMC_PMECCSAREA : (SMC Offset: 0x74) PMECC Spare Area Size Register -------- */
#define SMC_PMECCSAREA_SPARESIZE_Pos 0
#define SMC_PMECCSAREA_SPARESIZE_Msk (0x1ffu << SMC_PMECCSAREA_SPARESIZE_Pos) /**< \brief (SMC_PMECCSAREA) Spare Area Size */
#define SMC_PMECCSAREA_SPARESIZE(value) ((SMC_PMECCSAREA_SPARESIZE_Msk & ((value) << SMC_PMECCSAREA_SPARESIZE_Pos)))
/* -------- SMC_PMECCSADDR : (SMC Offset: 0x78) PMECC Start Address Register -------- */
#define SMC_PMECCSADDR_STARTADDR_Pos 0
#define SMC_PMECCSADDR_STARTADDR_Msk (0x1ffu << SMC_PMECCSADDR_STARTADDR_Pos) /**< \brief (SMC_PMECCSADDR) ECC Area Start Address */
#define SMC_PMECCSADDR_STARTADDR(value) ((SMC_PMECCSADDR_STARTADDR_Msk & ((value) << SMC_PMECCSADDR_STARTADDR_Pos)))
/* -------- SMC_PMECCEADDR : (SMC Offset: 0x7C) PMECC End Address Register -------- */
#define SMC_PMECCEADDR_ENDADDR_Pos 0
#define SMC_PMECCEADDR_ENDADDR_Msk (0x1ffu << SMC_PMECCEADDR_ENDADDR_Pos) /**< \brief (SMC_PMECCEADDR) ECC Area End Address */
#define SMC_PMECCEADDR_ENDADDR(value) ((SMC_PMECCEADDR_ENDADDR_Msk & ((value) << SMC_PMECCEADDR_ENDADDR_Pos)))
/* -------- SMC_PMECCTRL : (SMC Offset: 0x84) PMECC Control Register -------- */
#define SMC_PMECCTRL_RST (0x1u << 0) /**< \brief (SMC_PMECCTRL) Reset the PMECC Module */
#define SMC_PMECCTRL_DATA (0x1u << 1) /**< \brief (SMC_PMECCTRL) Start a Data Phase */
#define SMC_PMECCTRL_USER (0x1u << 2) /**< \brief (SMC_PMECCTRL) Start a User Mode Phase */
#define SMC_PMECCTRL_ENABLE (0x1u << 4) /**< \brief (SMC_PMECCTRL) PMECC Enable */
#define SMC_PMECCTRL_DISABLE (0x1u << 5) /**< \brief (SMC_PMECCTRL) PMECC Enable */
/* -------- SMC_PMECCSR : (SMC Offset: 0x88) PMECC Status Register -------- */
#define SMC_PMECCSR_BUSY (0x1u << 0) /**< \brief (SMC_PMECCSR) The kernel of the PMECC is busy */
#define SMC_PMECCSR_ENABLE (0x1u << 4) /**< \brief (SMC_PMECCSR) PMECC Enable bit */
/* -------- SMC_PMECCIER : (SMC Offset: 0x8C) PMECC Interrupt Enable register -------- */
#define SMC_PMECCIER_ERRIE (0x1u << 0) /**< \brief (SMC_PMECCIER) Error Interrupt Enable */
/* -------- SMC_PMECCIDR : (SMC Offset: 0x90) PMECC Interrupt Disable Register -------- */
#define SMC_PMECCIDR_ERRID (0x1u << 0) /**< \brief (SMC_PMECCIDR) Error Interrupt Disable */
/* -------- SMC_PMECCIMR : (SMC Offset: 0x94) PMECC Interrupt Mask Register -------- */
#define SMC_PMECCIMR_ERRIM (0x1u << 0) /**< \brief (SMC_PMECCIMR) Error Interrupt Mask */
/* -------- SMC_PMECCISR : (SMC Offset: 0x98) PMECC Interrupt Status Register -------- */
#define SMC_PMECCISR_ERRIS_Pos 0
#define SMC_PMECCISR_ERRIS_Msk (0xffu << SMC_PMECCISR_ERRIS_Pos) /**< \brief (SMC_PMECCISR) Error Interrupt Status Register */
/* -------- SMC_PMECC[11] : (SMC Offset: N/A) PMECC Redundancy x Register -------- */
#define SMC_PMECC_ECC_Pos 0
#define SMC_PMECC_ECC_Msk (0xffffffffu << SMC_PMECC_ECC_Pos) /**< \brief (SMC_PMECC[11]) BCH Redundancy */
/* -------- SMC_REM[12] : (SMC Offset: N/A) PMECC Remainder x Register -------- */
#define SMC_REM_REM2NP1_Pos 0
#define SMC_REM_REM2NP1_Msk (0x3fffu << SMC_REM_REM2NP1_Pos) /**< \brief (SMC_REM[12]) BCH Remainder 2 * N + 1 */
#define SMC_REM_REM2NP3_Pos 16
#define SMC_REM_REM2NP3_Msk (0x3fffu << SMC_REM_REM2NP3_Pos) /**< \brief (SMC_REM[12]) BCH Remainder 2 * N + 3 */
/* -------- SMC_ELCFG : (SMC Offset: 0x500) PMECCError Location Configuration Register -------- */
#define SMC_ELCFG_SECTORSZ (0x1u << 0) /**< \brief (SMC_ELCFG) Sector Size */
#define SMC_ELCFG_ERRNUM_Pos 16
#define SMC_ELCFG_ERRNUM_Msk (0x1fu << SMC_ELCFG_ERRNUM_Pos) /**< \brief (SMC_ELCFG) Number of Errors */
#define SMC_ELCFG_ERRNUM(value) ((SMC_ELCFG_ERRNUM_Msk & ((value) << SMC_ELCFG_ERRNUM_Pos)))
/* -------- SMC_ELEN : (SMC Offset: 0x508) PMECC Error Location Enable Register -------- */
#define SMC_ELEN_ENINIT_Pos 0
#define SMC_ELEN_ENINIT_Msk (0x3fffu << SMC_ELEN_ENINIT_Pos) /**< \brief (SMC_ELEN) Error Location Enable */
#define SMC_ELEN_ENINIT(value) ((SMC_ELEN_ENINIT_Msk & ((value) << SMC_ELEN_ENINIT_Pos)))
/* -------- SMC_ELDIS : (SMC Offset: 0x50C) PMECC Error Location Disable Register -------- */
#define SMC_ELDIS_DIS (0x1u << 0) /**< \brief (SMC_ELDIS) Disable Error Location Engine */
/* -------- SMC_ELSR : (SMC Offset: 0x510) PMECC Error Location Status Register -------- */
#define SMC_ELSR_BUSY (0x1u << 0) /**< \brief (SMC_ELSR) Error Location Engine Busy */
/* -------- SMC_ELIER : (SMC Offset: 0x514) PMECC Error Location Interrupt Enable register -------- */
#define SMC_ELIER_DONE (0x1u << 0) /**< \brief (SMC_ELIER) Computation Terminated Interrupt Enable */
/* -------- SMC_ELIDR : (SMC Offset: 0x518) PMECC Error Location Interrupt Disable Register -------- */
#define SMC_ELIDR_DONE (0x1u << 0) /**< \brief (SMC_ELIDR) Computation Terminated Interrupt Disable */
/* -------- SMC_ELIMR : (SMC Offset: 0x51C) PMECC Error Location Interrupt Mask Register -------- */
#define SMC_ELIMR_DONE (0x1u << 0) /**< \brief (SMC_ELIMR) Computation Terminated Interrupt Mask */
/* -------- SMC_ELISR : (SMC Offset: 0x520) PMECC Error Location Interrupt Status Register -------- */
#define SMC_ELISR_DONE (0x1u << 0) /**< \brief (SMC_ELISR) Computation Terminated Interrupt Status */
#define SMC_ELISR_ERR_CNT_Pos 8
#define SMC_ELISR_ERR_CNT_Msk (0x1fu << SMC_ELISR_ERR_CNT_Pos) /**< \brief (SMC_ELISR) Error Counter value */
/* -------- SMC_SIGMA0 : (SMC Offset: 0x528) PMECC Error Location SIGMA 0 Register -------- */
#define SMC_SIGMA0_SIGMA0_Pos 0
#define SMC_SIGMA0_SIGMA0_Msk (0x3fffu << SMC_SIGMA0_SIGMA0_Pos) /**< \brief (SMC_SIGMA0) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA0_SIGMA0(value) ((SMC_SIGMA0_SIGMA0_Msk & ((value) << SMC_SIGMA0_SIGMA0_Pos)))
/* -------- SMC_SIGMA1 : (SMC Offset: 0x52C) PMECC Error Location SIGMA 1 Register -------- */
#define SMC_SIGMA1_SIGMA1_Pos 0
#define SMC_SIGMA1_SIGMA1_Msk (0x3fffu << SMC_SIGMA1_SIGMA1_Pos) /**< \brief (SMC_SIGMA1) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA1_SIGMA1(value) ((SMC_SIGMA1_SIGMA1_Msk & ((value) << SMC_SIGMA1_SIGMA1_Pos)))
/* -------- SMC_SIGMA2 : (SMC Offset: 0x530) PMECC Error Location SIGMA 2 Register -------- */
#define SMC_SIGMA2_SIGMA2_Pos 0
#define SMC_SIGMA2_SIGMA2_Msk (0x3fffu << SMC_SIGMA2_SIGMA2_Pos) /**< \brief (SMC_SIGMA2) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA2_SIGMA2(value) ((SMC_SIGMA2_SIGMA2_Msk & ((value) << SMC_SIGMA2_SIGMA2_Pos)))
/* -------- SMC_SIGMA3 : (SMC Offset: 0x534) PMECC Error Location SIGMA 3 Register -------- */
#define SMC_SIGMA3_SIGMA3_Pos 0
#define SMC_SIGMA3_SIGMA3_Msk (0x3fffu << SMC_SIGMA3_SIGMA3_Pos) /**< \brief (SMC_SIGMA3) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA3_SIGMA3(value) ((SMC_SIGMA3_SIGMA3_Msk & ((value) << SMC_SIGMA3_SIGMA3_Pos)))
/* -------- SMC_SIGMA4 : (SMC Offset: 0x538) PMECC Error Location SIGMA 4 Register -------- */
#define SMC_SIGMA4_SIGMA4_Pos 0
#define SMC_SIGMA4_SIGMA4_Msk (0x3fffu << SMC_SIGMA4_SIGMA4_Pos) /**< \brief (SMC_SIGMA4) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA4_SIGMA4(value) ((SMC_SIGMA4_SIGMA4_Msk & ((value) << SMC_SIGMA4_SIGMA4_Pos)))
/* -------- SMC_SIGMA5 : (SMC Offset: 0x53C) PMECC Error Location SIGMA 5 Register -------- */
#define SMC_SIGMA5_SIGMA5_Pos 0
#define SMC_SIGMA5_SIGMA5_Msk (0x3fffu << SMC_SIGMA5_SIGMA5_Pos) /**< \brief (SMC_SIGMA5) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA5_SIGMA5(value) ((SMC_SIGMA5_SIGMA5_Msk & ((value) << SMC_SIGMA5_SIGMA5_Pos)))
/* -------- SMC_SIGMA6 : (SMC Offset: 0x540) PMECC Error Location SIGMA 6 Register -------- */
#define SMC_SIGMA6_SIGMA6_Pos 0
#define SMC_SIGMA6_SIGMA6_Msk (0x3fffu << SMC_SIGMA6_SIGMA6_Pos) /**< \brief (SMC_SIGMA6) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA6_SIGMA6(value) ((SMC_SIGMA6_SIGMA6_Msk & ((value) << SMC_SIGMA6_SIGMA6_Pos)))
/* -------- SMC_SIGMA7 : (SMC Offset: 0x544) PMECC Error Location SIGMA 7 Register -------- */
#define SMC_SIGMA7_SIGMA7_Pos 0
#define SMC_SIGMA7_SIGMA7_Msk (0x3fffu << SMC_SIGMA7_SIGMA7_Pos) /**< \brief (SMC_SIGMA7) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA7_SIGMA7(value) ((SMC_SIGMA7_SIGMA7_Msk & ((value) << SMC_SIGMA7_SIGMA7_Pos)))
/* -------- SMC_SIGMA8 : (SMC Offset: 0x548) PMECC Error Location SIGMA 8 Register -------- */
#define SMC_SIGMA8_SIGMA8_Pos 0
#define SMC_SIGMA8_SIGMA8_Msk (0x3fffu << SMC_SIGMA8_SIGMA8_Pos) /**< \brief (SMC_SIGMA8) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA8_SIGMA8(value) ((SMC_SIGMA8_SIGMA8_Msk & ((value) << SMC_SIGMA8_SIGMA8_Pos)))
/* -------- SMC_SIGMA9 : (SMC Offset: 0x54C) PMECC Error Location SIGMA 9 Register -------- */
#define SMC_SIGMA9_SIGMA9_Pos 0
#define SMC_SIGMA9_SIGMA9_Msk (0x3fffu << SMC_SIGMA9_SIGMA9_Pos) /**< \brief (SMC_SIGMA9) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA9_SIGMA9(value) ((SMC_SIGMA9_SIGMA9_Msk & ((value) << SMC_SIGMA9_SIGMA9_Pos)))
/* -------- SMC_SIGMA10 : (SMC Offset: 0x550) PMECC Error Location SIGMA 10 Register -------- */
#define SMC_SIGMA10_SIGMA10_Pos 0
#define SMC_SIGMA10_SIGMA10_Msk (0x3fffu << SMC_SIGMA10_SIGMA10_Pos) /**< \brief (SMC_SIGMA10) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA10_SIGMA10(value) ((SMC_SIGMA10_SIGMA10_Msk & ((value) << SMC_SIGMA10_SIGMA10_Pos)))
/* -------- SMC_SIGMA11 : (SMC Offset: 0x554) PMECC Error Location SIGMA 11 Register -------- */
#define SMC_SIGMA11_SIGMA11_Pos 0
#define SMC_SIGMA11_SIGMA11_Msk (0x3fffu << SMC_SIGMA11_SIGMA11_Pos) /**< \brief (SMC_SIGMA11) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA11_SIGMA11(value) ((SMC_SIGMA11_SIGMA11_Msk & ((value) << SMC_SIGMA11_SIGMA11_Pos)))
/* -------- SMC_SIGMA12 : (SMC Offset: 0x558) PMECC Error Location SIGMA 12 Register -------- */
#define SMC_SIGMA12_SIGMA12_Pos 0
#define SMC_SIGMA12_SIGMA12_Msk (0x3fffu << SMC_SIGMA12_SIGMA12_Pos) /**< \brief (SMC_SIGMA12) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA12_SIGMA12(value) ((SMC_SIGMA12_SIGMA12_Msk & ((value) << SMC_SIGMA12_SIGMA12_Pos)))
/* -------- SMC_SIGMA13 : (SMC Offset: 0x55C) PMECC Error Location SIGMA 13 Register -------- */
#define SMC_SIGMA13_SIGMA13_Pos 0
#define SMC_SIGMA13_SIGMA13_Msk (0x3fffu << SMC_SIGMA13_SIGMA13_Pos) /**< \brief (SMC_SIGMA13) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA13_SIGMA13(value) ((SMC_SIGMA13_SIGMA13_Msk & ((value) << SMC_SIGMA13_SIGMA13_Pos)))
/* -------- SMC_SIGMA14 : (SMC Offset: 0x560) PMECC Error Location SIGMA 14 Register -------- */
#define SMC_SIGMA14_SIGMA14_Pos 0
#define SMC_SIGMA14_SIGMA14_Msk (0x3fffu << SMC_SIGMA14_SIGMA14_Pos) /**< \brief (SMC_SIGMA14) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA14_SIGMA14(value) ((SMC_SIGMA14_SIGMA14_Msk & ((value) << SMC_SIGMA14_SIGMA14_Pos)))
/* -------- SMC_SIGMA15 : (SMC Offset: 0x564) PMECC Error Location SIGMA 15 Register -------- */
#define SMC_SIGMA15_SIGMA15_Pos 0
#define SMC_SIGMA15_SIGMA15_Msk (0x3fffu << SMC_SIGMA15_SIGMA15_Pos) /**< \brief (SMC_SIGMA15) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA15_SIGMA15(value) ((SMC_SIGMA15_SIGMA15_Msk & ((value) << SMC_SIGMA15_SIGMA15_Pos)))
/* -------- SMC_SIGMA16 : (SMC Offset: 0x568) PMECC Error Location SIGMA 16 Register -------- */
#define SMC_SIGMA16_SIGMA16_Pos 0
#define SMC_SIGMA16_SIGMA16_Msk (0x3fffu << SMC_SIGMA16_SIGMA16_Pos) /**< \brief (SMC_SIGMA16) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA16_SIGMA16(value) ((SMC_SIGMA16_SIGMA16_Msk & ((value) << SMC_SIGMA16_SIGMA16_Pos)))
/* -------- SMC_SIGMA17 : (SMC Offset: 0x56C) PMECC Error Location SIGMA 17 Register -------- */
#define SMC_SIGMA17_SIGMA17_Pos 0
#define SMC_SIGMA17_SIGMA17_Msk (0x3fffu << SMC_SIGMA17_SIGMA17_Pos) /**< \brief (SMC_SIGMA17) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA17_SIGMA17(value) ((SMC_SIGMA17_SIGMA17_Msk & ((value) << SMC_SIGMA17_SIGMA17_Pos)))
/* -------- SMC_SIGMA18 : (SMC Offset: 0x570) PMECC Error Location SIGMA 18 Register -------- */
#define SMC_SIGMA18_SIGMA18_Pos 0
#define SMC_SIGMA18_SIGMA18_Msk (0x3fffu << SMC_SIGMA18_SIGMA18_Pos) /**< \brief (SMC_SIGMA18) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA18_SIGMA18(value) ((SMC_SIGMA18_SIGMA18_Msk & ((value) << SMC_SIGMA18_SIGMA18_Pos)))
/* -------- SMC_SIGMA19 : (SMC Offset: 0x574) PMECC Error Location SIGMA 19 Register -------- */
#define SMC_SIGMA19_SIGMA19_Pos 0
#define SMC_SIGMA19_SIGMA19_Msk (0x3fffu << SMC_SIGMA19_SIGMA19_Pos) /**< \brief (SMC_SIGMA19) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA19_SIGMA19(value) ((SMC_SIGMA19_SIGMA19_Msk & ((value) << SMC_SIGMA19_SIGMA19_Pos)))
/* -------- SMC_SIGMA20 : (SMC Offset: 0x578) PMECC Error Location SIGMA 20 Register -------- */
#define SMC_SIGMA20_SIGMA20_Pos 0
#define SMC_SIGMA20_SIGMA20_Msk (0x3fffu << SMC_SIGMA20_SIGMA20_Pos) /**< \brief (SMC_SIGMA20) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA20_SIGMA20(value) ((SMC_SIGMA20_SIGMA20_Msk & ((value) << SMC_SIGMA20_SIGMA20_Pos)))
/* -------- SMC_SIGMA21 : (SMC Offset: 0x57C) PMECC Error Location SIGMA 21 Register -------- */
#define SMC_SIGMA21_SIGMA21_Pos 0
#define SMC_SIGMA21_SIGMA21_Msk (0x3fffu << SMC_SIGMA21_SIGMA21_Pos) /**< \brief (SMC_SIGMA21) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA21_SIGMA21(value) ((SMC_SIGMA21_SIGMA21_Msk & ((value) << SMC_SIGMA21_SIGMA21_Pos)))
/* -------- SMC_SIGMA22 : (SMC Offset: 0x580) PMECC Error Location SIGMA 22 Register -------- */
#define SMC_SIGMA22_SIGMA22_Pos 0
#define SMC_SIGMA22_SIGMA22_Msk (0x3fffu << SMC_SIGMA22_SIGMA22_Pos) /**< \brief (SMC_SIGMA22) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA22_SIGMA22(value) ((SMC_SIGMA22_SIGMA22_Msk & ((value) << SMC_SIGMA22_SIGMA22_Pos)))
/* -------- SMC_SIGMA23 : (SMC Offset: 0x584) PMECC Error Location SIGMA 23 Register -------- */
#define SMC_SIGMA23_SIGMA23_Pos 0
#define SMC_SIGMA23_SIGMA23_Msk (0x3fffu << SMC_SIGMA23_SIGMA23_Pos) /**< \brief (SMC_SIGMA23) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA23_SIGMA23(value) ((SMC_SIGMA23_SIGMA23_Msk & ((value) << SMC_SIGMA23_SIGMA23_Pos)))
/* -------- SMC_SIGMA24 : (SMC Offset: 0x588) PMECC Error Location SIGMA 24 Register -------- */
#define SMC_SIGMA24_SIGMA24_Pos 0
#define SMC_SIGMA24_SIGMA24_Msk (0x3fffu << SMC_SIGMA24_SIGMA24_Pos) /**< \brief (SMC_SIGMA24) Coefficient of degree x in the SIGMA polynomial. */
#define SMC_SIGMA24_SIGMA24(value) ((SMC_SIGMA24_SIGMA24_Msk & ((value) << SMC_SIGMA24_SIGMA24_Pos)))
/* -------- SMC_ERRLOC[24] : (SMC Offset: 0x58C) PMECC Error Location 0 Register -------- */
#define SMC_ERRLOC_ERRLOCN_Pos 0
#define SMC_ERRLOC_ERRLOCN_Msk (0x3fffu << SMC_ERRLOC_ERRLOCN_Pos) /**< \brief (SMC_ERRLOC[24]) Error Position within the Set {sector area, spare area} */
/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
#define SMC_SETUP_NWE_SETUP_Pos 0
#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
#define SMC_SETUP_NCS_WR_SETUP_Pos 8
#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */
#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
#define SMC_SETUP_NRD_SETUP_Pos 16
#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
#define SMC_SETUP_NCS_RD_SETUP_Pos 24
#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */
#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
#define SMC_PULSE_NWE_PULSE_Pos 0
#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
#define SMC_PULSE_NCS_WR_PULSE_Pos 8
#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
#define SMC_PULSE_NRD_PULSE_Pos 16
#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
#define SMC_PULSE_NCS_RD_PULSE_Pos 24
#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
#define SMC_CYCLE_NWE_CYCLE_Pos 0
#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
#define SMC_CYCLE_NRD_CYCLE_Pos 16
#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */
#define SMC_TIMINGS_TCLR_Pos 0
#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */
#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos)))
#define SMC_TIMINGS_TADL_Pos 4
#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */
#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos)))
#define SMC_TIMINGS_TAR_Pos 8
#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */
#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos)))
#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */
#define SMC_TIMINGS_TRR_Pos 16
#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */
#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos)))
#define SMC_TIMINGS_TWB_Pos 24
#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */
#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos)))
#define SMC_TIMINGS_RBNSEL_Pos 28
#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */
#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos)))
#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */
/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
#define   SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */
#define   SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */
#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
#define   SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */
#define   SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */
#define SMC_MODE_EXNW_MODE_Pos 4
#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
#define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
#define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
#define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
#define   SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
#define   SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
#define SMC_MODE_TDF_CYCLES_Pos 16
#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
/* -------- SMC_OCMS : (SMC Offset: 0x6A0) SMC OCMS Register -------- */
#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */
/* -------- SMC_KEY1 : (SMC Offset: 0x6A4) SMC OCMS KEY1 Register -------- */
#define SMC_KEY1_KEY1_Pos 0
#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
/* -------- SMC_KEY2 : (SMC Offset: 0x6A8) SMC OCMS KEY2 Register -------- */
#define SMC_KEY2_KEY2_Pos 0
#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
/* -------- SMC_WPCR : (SMC Offset: 0x6E4) SMC Write Protection Control Register -------- */
#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */
#define SMC_WPCR_WP_KEY_Pos 8
#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */
#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos)))
/* -------- SMC_WPSR : (SMC Offset: 0x6E8) SMC Write Protection Status Register -------- */
#define SMC_WPSR_WP_VS_Pos 0
#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */
#define SMC_WPSR_WP_VSRC_Pos 8
#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_SPI Serial Peripheral Interface */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Spi hardware registers */
typedef struct {
  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
  RoReg Reserved1[4];
  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
  RoReg Reserved2[41];
  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
} Spi;
#endif /* __ASSEMBLY__ */
/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
#define SPI_MR_PCS_Pos 16
#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
#define SPI_MR_DLYBCS_Pos 24
#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
#define SPI_RDR_RD_Pos 0
#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
#define SPI_RDR_PCS_Pos 16
#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
#define SPI_TDR_TD_Pos 0
#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
#define SPI_TDR_PCS_Pos 16
#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR)  */
#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR)  */
#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR)  */
#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR)  */
#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER)  */
#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER)  */
#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER)  */
#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER)  */
#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR)  */
#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR)  */
#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR)  */
#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR)  */
#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR)  */
#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR)  */
#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR)  */
#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR)  */
#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
#define SPI_CSR_BITS_Pos 4
#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
#define SPI_CSR_SCBR_Pos 8
#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
#define SPI_CSR_DLYBS_Pos 16
#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
#define SPI_CSR_DLYBCT_Pos 24
#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
#define SPI_WPMR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */
#define SPI_WPMR_SPIWPKEY_Pos 8
#define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */
#define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos)))
/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
#define SPI_WPSR_SPIWPVS_Pos 0
#define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
#define SPI_WPSR_SPIWPVSRC_Pos 8
#define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_SSC Synchronous Serial Controller */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Ssc hardware registers */
typedef struct {
  WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
  RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
  RoReg Reserved1[2];
  RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
  RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
  RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
  RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
  RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
  WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
  RoReg Reserved2[2];
  RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
  RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
  RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
  RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
  RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
  WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
  WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
  RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
  RoReg Reserved3[37];
  RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
  RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
} Ssc;
#endif /* __ASSEMBLY__ */
/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
#define SSC_CMR_DIV_Pos 0
#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
#define SSC_RCMR_CKS_Pos 0
#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
#define SSC_RCMR_CKO_Pos 2
#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
#define SSC_RCMR_CKG_Pos 6
#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
#define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
#define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
#define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
#define SSC_RCMR_START_Pos 8
#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
#define SSC_RCMR_STTDLY_Pos 16
#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
#define SSC_RCMR_PERIOD_Pos 24
#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
#define SSC_RFMR_DATLEN_Pos 0
#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
#define SSC_RFMR_DATNB_Pos 8
#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
#define SSC_RFMR_FSLEN_Pos 16
#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
#define SSC_RFMR_FSOS_Pos 20
#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
#define SSC_RFMR_FSLEN_EXT_Pos 28
#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
#define SSC_TCMR_CKS_Pos 0
#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
#define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
#define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
#define SSC_TCMR_CKO_Pos 2
#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
#define SSC_TCMR_CKG_Pos 6
#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
#define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
#define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
#define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
#define SSC_TCMR_START_Pos 8
#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
#define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
#define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
#define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
#define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
#define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
#define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
#define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
#define SSC_TCMR_STTDLY_Pos 16
#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
#define SSC_TCMR_PERIOD_Pos 24
#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
#define SSC_TFMR_DATLEN_Pos 0
#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
#define SSC_TFMR_DATNB_Pos 8
#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
#define SSC_TFMR_FSLEN_Pos 16
#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
#define SSC_TFMR_FSOS_Pos 20
#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
#define SSC_TFMR_FSLEN_EXT_Pos 28
#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
#define SSC_RHR_RDAT_Pos 0
#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
#define SSC_THR_TDAT_Pos 0
#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
#define SSC_RSHR_RSDAT_Pos 0
#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
#define SSC_TSHR_TSDAT_Pos 0
#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
#define SSC_RC0R_CP0_Pos 0
#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
#define SSC_RC1R_CP1_Pos 0
#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
#define SSC_WPMR_WPKEY_Pos 8
#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
#define SSC_WPSR_WPVSRC_Pos 8
#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Timer Counter */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_TC Timer Counter */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief TcChannel hardware registers */
typedef struct {
  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
  RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
  RwReg      TC_RAB;        /**< \brief (TcChannel Offset: 0xC) Register AB */
  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
  RoReg      Reserved1[4];
} TcChannel;
/** \brief Tc hardware registers */
#define TCCHANNEL_NUMBER 3
typedef struct {
  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
  RoReg      Reserved1[7];
  RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
} Tc;
#endif /* __ASSEMBLY__ */
/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
#define TC_CMR_TCCLKS_Pos 0
#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
#define TC_CMR_BURST_Pos 4
#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
#define TC_CMR_ETRGEDG_Pos 8
#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
#define TC_CMR_LDRA_Pos 16
#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
#define TC_CMR_LDRB_Pos 18
#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
#define TC_CMR_EEVTEDG_Pos 8
#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
#define TC_CMR_EEVT_Pos 10
#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
#define TC_CMR_WAVSEL_Pos 13
#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
#define TC_CMR_ACPA_Pos 16
#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
#define TC_CMR_ACPC_Pos 18
#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
#define TC_CMR_AEEVT_Pos 20
#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
#define TC_CMR_ASWTRG_Pos 22
#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
#define TC_CMR_BCPB_Pos 24
#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
#define TC_CMR_BCPC_Pos 26
#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
#define TC_CMR_BEEVT_Pos 28
#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
#define TC_CMR_BSWTRG_Pos 30
#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */
#define TC_RAB_RAB_Pos 0
#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */
/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
#define TC_CV_CV_Pos 0
#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
#define TC_RA_RA_Pos 0
#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
#define TC_RB_RB_Pos 0
#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
#define TC_RC_RC_Pos 0
#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
#define TC_BMR_TC0XC0S_Pos 0
#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
#define TC_BMR_TC1XC1S_Pos 2
#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
#define TC_BMR_TC2XC2S_Pos 4
#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
#define TC_WPMR_WPKEY_Pos 8
#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_TDES Triple Data Encryption Standard */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Tdes hardware registers */
typedef struct {
  WoReg TDES_CR;        /**< \brief (Tdes Offset: 0x00) Control Register */
  RwReg TDES_MR;        /**< \brief (Tdes Offset: 0x04) Mode Register */
  RoReg Reserved1[2];
  WoReg TDES_IER;       /**< \brief (Tdes Offset: 0x10) Interrupt Enable Register */
  WoReg TDES_IDR;       /**< \brief (Tdes Offset: 0x14) Interrupt Disable Register */
  RoReg TDES_IMR;       /**< \brief (Tdes Offset: 0x18) Interrupt Mask Register */
  RoReg TDES_ISR;       /**< \brief (Tdes Offset: 0x1C) Interrupt Status Register */
  WoReg TDES_KEY1WR[2]; /**< \brief (Tdes Offset: 0x20) Key 1 Word Register */
  WoReg TDES_KEY2WR[2]; /**< \brief (Tdes Offset: 0x28) Key 2 Word Register */
  WoReg TDES_KEY3WR[2]; /**< \brief (Tdes Offset: 0x30) Key 3 Word Register */
  RoReg Reserved2[2];
  WoReg TDES_IDATAR[2]; /**< \brief (Tdes Offset: 0x40) Input Data Register */
  RoReg Reserved3[2];
  RoReg TDES_ODATAR[2]; /**< \brief (Tdes Offset: 0x50) Output Data Register */
  RoReg Reserved4[2];
  WoReg TDES_IVR[2];    /**< \brief (Tdes Offset: 0x60) Initialization Vector Register */
  RoReg Reserved5[2];
  RwReg TDES_XTEARNDR;  /**< \brief (Tdes Offset: 0x70) XTEA Rounds Register */
} Tdes;
#endif /* __ASSEMBLY__ */
/* -------- TDES_CR : (TDES Offset: 0x00) Control Register -------- */
#define TDES_CR_START (0x1u << 0) /**< \brief (TDES_CR) Start Processing */
#define TDES_CR_SWRST (0x1u << 8) /**< \brief (TDES_CR) Software Reset */
#define TDES_CR_LOADSEED (0x1u << 16) /**< \brief (TDES_CR) Load Seed */
/* -------- TDES_MR : (TDES Offset: 0x04) Mode Register -------- */
#define TDES_MR_CIPHER (0x1u << 0) /**< \brief (TDES_MR) Processing Mode */
#define   TDES_MR_CIPHER_DECRYPT (0x0u << 0) /**< \brief (TDES_MR) Decrypts data. */
#define   TDES_MR_CIPHER_ENCRYPT (0x1u << 0) /**< \brief (TDES_MR) Encrypts data. */
#define TDES_MR_TDESMOD_Pos 1
#define TDES_MR_TDESMOD_Msk (0x3u << TDES_MR_TDESMOD_Pos) /**< \brief (TDES_MR) ALGORITHM mode */
#define TDES_MR_TDESMOD(value) ((TDES_MR_TDESMOD_Msk & ((value) << TDES_MR_TDESMOD_Pos)))
#define TDES_MR_KEYMOD (0x1u << 4) /**< \brief (TDES_MR) Key Mode */
#define TDES_MR_SMOD_Pos 8
#define TDES_MR_SMOD_Msk (0x3u << TDES_MR_SMOD_Pos) /**< \brief (TDES_MR) Start Mode */
#define   TDES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (TDES_MR) Manual Mode */
#define   TDES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (TDES_MR) Auto Mode */
#define   TDES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (TDES_MR) TDES_IDATAR0 access only Auto Mode */
#define TDES_MR_OPMOD_Pos 12
#define TDES_MR_OPMOD_Msk (0x3u << TDES_MR_OPMOD_Pos) /**< \brief (TDES_MR) Operation Mode */
#define   TDES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (TDES_MR) ECB: Electronic Code Book mode */
#define   TDES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (TDES_MR) CBC: Cipher Block Chaining mode */
#define   TDES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (TDES_MR) OFB: Output Feedback mode */
#define   TDES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (TDES_MR) CFB: Cipher Feedback mode */
#define TDES_MR_LOD (0x1u << 15) /**< \brief (TDES_MR) Last Output Data Mode */
#define TDES_MR_CFBS_Pos 16
#define TDES_MR_CFBS_Msk (0x3u << TDES_MR_CFBS_Pos) /**< \brief (TDES_MR) Cipher Feedback Data Size */
#define   TDES_MR_CFBS_SIZE_64BIT (0x0u << 16) /**< \brief (TDES_MR) 64-bit */
#define   TDES_MR_CFBS_SIZE_32BIT (0x1u << 16) /**< \brief (TDES_MR) 32-bit */
#define   TDES_MR_CFBS_SIZE_16BIT (0x2u << 16) /**< \brief (TDES_MR) 16-bit */
#define   TDES_MR_CFBS_SIZE_8BIT (0x3u << 16) /**< \brief (TDES_MR) 8-bit */
#define TDES_MR_CKEY_Pos 20
#define TDES_MR_CKEY_Msk (0xfu << TDES_MR_CKEY_Pos) /**< \brief (TDES_MR) Countermeasure Key */
#define TDES_MR_CKEY(value) ((TDES_MR_CKEY_Msk & ((value) << TDES_MR_CKEY_Pos)))
#define TDES_MR_CMTYP1 (0x1u << 24) /**< \brief (TDES_MR) CounterMeasure Type 1 */
#define   TDES_MR_CMTYP1_NO_PAUSE (0x0u << 24) /**< \brief (TDES_MR) Counter-Measure type 1 is disabled */
#define   TDES_MR_CMTYP1_PAUSE (0x1u << 24) /**< \brief (TDES_MR) Counter-Measure type 1 is enabled */
#define TDES_MR_CMTYP2 (0x1u << 25) /**< \brief (TDES_MR) CounterMeasure Type 2 */
#define   TDES_MR_CMTYP2_NO_DUMMY (0x0u << 25) /**< \brief (TDES_MR) Counter-Measure type 2 is disabled */
#define   TDES_MR_CMTYP2_DUMMY (0x1u << 25) /**< \brief (TDES_MR) Counter-Measure type 2 is enabled */
#define TDES_MR_CMTYP3 (0x1u << 26) /**< \brief (TDES_MR) CounterMeasure Type 3 */
#define   TDES_MR_CMTYP3_NO_RESTART (0x0u << 26) /**< \brief (TDES_MR) Counter-Measure type 3 is disabled */
#define   TDES_MR_CMTYP3_RESTART (0x1u << 26) /**< \brief (TDES_MR) Counter-Measure type 3 is enabled */
#define TDES_MR_CMTYP4 (0x1u << 27) /**< \brief (TDES_MR) CounterMeasure Type 4 */
#define   TDES_MR_CMTYP4_NO_IDLECURRENT (0x0u << 27) /**< \brief (TDES_MR) Counter-Measure type 4 is disabled */
#define   TDES_MR_CMTYP4_IDLECURRENT (0x1u << 27) /**< \brief (TDES_MR) Counter-Measure type 4 is enabled */
#define TDES_MR_CMTYP5 (0x1u << 28) /**< \brief (TDES_MR) CounterMeasure Type 5 */
#define   TDES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (TDES_MR) Counter-Measure type 5 is disabled */
#define   TDES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (TDES_MR) Counter-Measure type 5 is enabled */
/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
#define TDES_IER_DATRDY (0x1u << 0) /**< \brief (TDES_IER) Data Ready Interrupt Enable */
#define TDES_IER_URAD (0x1u << 8) /**< \brief (TDES_IER) Unspecified Register Access Detection Interrupt Enable */
/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
#define TDES_IDR_DATRDY (0x1u << 0) /**< \brief (TDES_IDR) Data Ready Interrupt Disable */
#define TDES_IDR_URAD (0x1u << 8) /**< \brief (TDES_IDR) Unspecified Register Access Detection Interrupt Disable */
/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
#define TDES_IMR_DATRDY (0x1u << 0) /**< \brief (TDES_IMR) Data Ready Interrupt Mask */
#define TDES_IMR_URAD (0x1u << 8) /**< \brief (TDES_IMR) Unspecified Register Access Detection Interrupt Mask */
/* -------- TDES_ISR : (TDES Offset: 0x1C) Interrupt Status Register -------- */
#define TDES_ISR_DATRDY (0x1u << 0) /**< \brief (TDES_ISR) Data Ready */
#define TDES_ISR_URAD (0x1u << 8) /**< \brief (TDES_ISR) Unspecified Register Access Detection Status */
#define TDES_ISR_URAT_Pos 12
#define TDES_ISR_URAT_Msk (0x3u << TDES_ISR_URAT_Pos) /**< \brief (TDES_ISR) Unspecified Register Access */
#define   TDES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (TDES_ISR) Input Data Register written during the data processing when SMOD=0x2 mode. */
#define   TDES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (TDES_ISR) Output Data Register read during the data processing. */
#define   TDES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (TDES_ISR) Mode Register written during the data processing. */
#define   TDES_ISR_URAT_WOR_RD_ACCESS (0x3u << 12) /**< \brief (TDES_ISR) Write-only register read access. */
/* -------- TDES_KEY1WR[2] : (TDES Offset: 0x20) Key 1 Word Register -------- */
#define TDES_KEY1WR_KEY1W_Pos 0
#define TDES_KEY1WR_KEY1W_Msk (0xffffffffu << TDES_KEY1WR_KEY1W_Pos) /**< \brief (TDES_KEY1WR[2]) Key 1 Word */
#define TDES_KEY1WR_KEY1W(value) ((TDES_KEY1WR_KEY1W_Msk & ((value) << TDES_KEY1WR_KEY1W_Pos)))
/* -------- TDES_KEY2WR[2] : (TDES Offset: 0x28) Key 2 Word Register -------- */
#define TDES_KEY2WR_KEY2W_Pos 0
#define TDES_KEY2WR_KEY2W_Msk (0xffffffffu << TDES_KEY2WR_KEY2W_Pos) /**< \brief (TDES_KEY2WR[2]) Key 2 Word */
#define TDES_KEY2WR_KEY2W(value) ((TDES_KEY2WR_KEY2W_Msk & ((value) << TDES_KEY2WR_KEY2W_Pos)))
/* -------- TDES_KEY3WR[2] : (TDES Offset: 0x30) Key 3 Word Register -------- */
#define TDES_KEY3WR_KEY3W_Pos 0
#define TDES_KEY3WR_KEY3W_Msk (0xffffffffu << TDES_KEY3WR_KEY3W_Pos) /**< \brief (TDES_KEY3WR[2]) Key 3 Word */
#define TDES_KEY3WR_KEY3W(value) ((TDES_KEY3WR_KEY3W_Msk & ((value) << TDES_KEY3WR_KEY3W_Pos)))
/* -------- TDES_IDATAR[2] : (TDES Offset: 0x40) Input Data Register -------- */
#define TDES_IDATAR_IDATA_Pos 0
#define TDES_IDATAR_IDATA_Msk (0xffffffffu << TDES_IDATAR_IDATA_Pos) /**< \brief (TDES_IDATAR[2]) Input Data */
#define TDES_IDATAR_IDATA(value) ((TDES_IDATAR_IDATA_Msk & ((value) << TDES_IDATAR_IDATA_Pos)))
/* -------- TDES_ODATAR[2] : (TDES Offset: 0x50) Output Data Register -------- */
#define TDES_ODATAR_ODATA_Pos 0
#define TDES_ODATAR_ODATA_Msk (0xffffffffu << TDES_ODATAR_ODATA_Pos) /**< \brief (TDES_ODATAR[2]) Output Data */
/* -------- TDES_IVR[2] : (TDES Offset: 0x60) Initialization Vector Register -------- */
#define TDES_IVR_IV_Pos 0
#define TDES_IVR_IV_Msk (0xffffffffu << TDES_IVR_IV_Pos) /**< \brief (TDES_IVR[2]) Initialization Vector */
#define TDES_IVR_IV(value) ((TDES_IVR_IV_Msk & ((value) << TDES_IVR_IV_Pos)))

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR True Random Number Generator */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_TRNG True Random Number Generator */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Trng hardware registers */
typedef struct {
  WoReg TRNG_CR;       /**< \brief (Trng Offset: 0x00) Control Register */
  RoReg Reserved1[3];
  WoReg TRNG_IER;      /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */
  WoReg TRNG_IDR;      /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */
  RoReg TRNG_IMR;      /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */
  RoReg TRNG_ISR;      /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */
  RoReg Reserved2[12];
  RoReg TRNG_ODATA;    /**< \brief (Trng Offset: 0x50) Output Data Register */
} Trng;
#endif /* __ASSEMBLY__ */
/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */
#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */
#define TRNG_CR_KEY_Pos 8
#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */
#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))
/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */
#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */
/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */
#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */
/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */
#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */
/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */
#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */
/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */
#define TRNG_ODATA_ODATA_Pos 0
#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_TWI Two-wire Interface */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Twi hardware registers */
typedef struct {
  WoReg TWI_CR;           /**< \brief (Twi Offset: 0x00) Control Register */
  RwReg TWI_MMR;          /**< \brief (Twi Offset: 0x04) Master Mode Register */
  RwReg TWI_SMR;          /**< \brief (Twi Offset: 0x08) Slave Mode Register */
  RwReg TWI_IADR;         /**< \brief (Twi Offset: 0x0C) Internal Address Register */
  RwReg TWI_CWGR;         /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
  RoReg Reserved1[3];
  RoReg TWI_SR;           /**< \brief (Twi Offset: 0x20) Status Register */
  WoReg TWI_IER;          /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
  WoReg TWI_IDR;          /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
  RoReg TWI_IMR;          /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
  RoReg TWI_RHR;          /**< \brief (Twi Offset: 0x30) Receive Holding Register */
  WoReg TWI_THR;          /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
  RoReg Reserved2[43];
  RwReg TWI_WPROT_MODE;   /**< \brief (Twi Offset: 0xE4) Protection Mode Register */
  RoReg TWI_WPROT_STATUS; /**< \brief (Twi Offset: 0xE8) Protection Status Register */
} Twi;
#endif /* __ASSEMBLY__ */
/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
#define TWI_MMR_IADRSZ_Pos 8
#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
#define TWI_MMR_DADR_Pos 16
#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
#define TWI_SMR_SADR_Pos 16
#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
#define TWI_IADR_IADR_Pos 0
#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
#define TWI_CWGR_CLDIV_Pos 0
#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
#define TWI_CWGR_CHDIV_Pos 8
#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
#define TWI_CWGR_CKDIV_Pos 16
#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
#define TWI_RHR_RXDATA_Pos 0
#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
#define TWI_THR_TXDATA_Pos 0
#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
/* -------- TWI_WPROT_MODE : (TWI Offset: 0xE4) Protection Mode Register -------- */
#define TWI_WPROT_MODE_WPROT (0x1u << 0) /**< \brief (TWI_WPROT_MODE) Write protection bit */
#define TWI_WPROT_MODE_SECURITY_CODE_Pos 8
#define TWI_WPROT_MODE_SECURITY_CODE_Msk (0xffffffu << TWI_WPROT_MODE_SECURITY_CODE_Pos) /**< \brief (TWI_WPROT_MODE) Write protection mode security code */
#define TWI_WPROT_MODE_SECURITY_CODE(value) ((TWI_WPROT_MODE_SECURITY_CODE_Msk & ((value) << TWI_WPROT_MODE_SECURITY_CODE_Pos)))
/* -------- TWI_WPROT_STATUS : (TWI Offset: 0xE8) Protection Status Register -------- */
#define TWI_WPROT_STATUS_WPROTERR (0x1u << 0) /**< \brief (TWI_WPROT_STATUS) Write Protection Error */
#define TWI_WPROT_STATUS_WPROTADDR_Pos 8
#define TWI_WPROT_STATUS_WPROTADDR_Msk (0xffffffu << TWI_WPROT_STATUS_WPROTADDR_Pos) /**< \brief (TWI_WPROT_STATUS) Write Protection Error Address */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_UART Universal Asynchronous Receiver Transmitter */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Uart hardware registers */
typedef struct {
  WoReg UART_CR;   /**< \brief (Uart Offset: 0x0000) Control Register */
  RwReg UART_MR;   /**< \brief (Uart Offset: 0x0004) Mode Register */
  WoReg UART_IER;  /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
  WoReg UART_IDR;  /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
  RoReg UART_IMR;  /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
  RoReg UART_SR;   /**< \brief (Uart Offset: 0x0014) Status Register */
  RoReg UART_RHR;  /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
  WoReg UART_THR;  /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
  RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
} Uart;
#endif /* __ASSEMBLY__ */
/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
#define UART_MR_PAR_Pos 9
#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
#define UART_MR_CHMODE_Pos 14
#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
#define UART_RHR_RXCHR_Pos 0
#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
#define UART_THR_TXCHR_Pos 0
#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
#define UART_BRGR_CD_Pos 0
#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR USB High Speed Device Port */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_UDPHS USB High Speed Device Port */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief UdphsDma hardware registers */
typedef struct {
  RwReg     UDPHS_DMANXTDSC;  /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */
  RwReg     UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */
  RwReg     UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */
  RwReg     UDPHS_DMASTATUS;  /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */
} UdphsDma;
/** \brief UdphsEpt hardware registers */
typedef struct {
  RwReg     UDPHS_EPTCFG;     /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */
  RwReg     UDPHS_EPTCTLENB;  /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */
  RwReg     UDPHS_EPTCTLDIS;  /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */
  RwReg     UDPHS_EPTCTL;     /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */
  RoReg     Reserved1[1];
  RwReg     UDPHS_EPTSETSTA;  /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */
  RwReg     UDPHS_EPTCLRSTA;  /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */
  RwReg     UDPHS_EPTSTA;     /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */
} UdphsEpt;
/** \brief Udphs hardware registers */
#define UDPHSEPT_NUMBER 16
#define UDPHSDMA_NUMBER 7
typedef struct {
  RwReg     UDPHS_CTRL;       /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */
  RoReg     UDPHS_FNUM;       /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */
  RoReg     Reserved1[2];
  RwReg     UDPHS_IEN;        /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */
  RoReg     UDPHS_INTSTA;     /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */
  WoReg     UDPHS_CLRINT;     /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */
  WoReg     UDPHS_EPTRST;     /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */
  RoReg     Reserved2[48];
  RwReg     UDPHS_TST;        /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */
  RoReg     Reserved3[3];
  RoReg     UDPHS_IPNAME1;    /**< \brief (Udphs Offset: 0xF0) UDPHS Name1 Register */
  RoReg     UDPHS_IPNAME2;    /**< \brief (Udphs Offset: 0xF4) UDPHS Name2 Register */
  RoReg     UDPHS_IPFEATURES; /**< \brief (Udphs Offset: 0xF8) UDPHS Features Register */
  RoReg     Reserved4[1];
  UdphsEpt  UDPHS_EPT[UDPHSEPT_NUMBER]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 15 */
  UdphsDma  UDPHS_DMA[UDPHSDMA_NUMBER]; /**< \brief (Udphs Offset: 0x300) channel = 0 .. 6 */
} Udphs;
#endif /* __ASSEMBLY__ */
/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */
#define UDPHS_CTRL_DEV_ADDR_Pos 0
#define UDPHS_CTRL_DEV_ADDR_Msk (0x7fu << UDPHS_CTRL_DEV_ADDR_Pos) /**< \brief (UDPHS_CTRL) UDPHS Address */
#define UDPHS_CTRL_DEV_ADDR(value) ((UDPHS_CTRL_DEV_ADDR_Msk & ((value) << UDPHS_CTRL_DEV_ADDR_Pos)))
#define UDPHS_CTRL_FADDR_EN (0x1u << 7) /**< \brief (UDPHS_CTRL) Function Address Enable */
#define UDPHS_CTRL_EN_UDPHS (0x1u << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */
#define UDPHS_CTRL_DETACH (0x1u << 9) /**< \brief (UDPHS_CTRL) Detach Command */
#define UDPHS_CTRL_REWAKEUP (0x1u << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up */
#define UDPHS_CTRL_PULLD_DIS (0x1u << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable */
/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */
#define UDPHS_FNUM_MICRO_FRAME_NUM_Pos 0
#define UDPHS_FNUM_MICRO_FRAME_NUM_Msk (0x7u << UDPHS_FNUM_MICRO_FRAME_NUM_Pos) /**< \brief (UDPHS_FNUM) Microframe Number */
#define UDPHS_FNUM_FRAME_NUMBER_Pos 3
#define UDPHS_FNUM_FRAME_NUMBER_Msk (0x7ffu << UDPHS_FNUM_FRAME_NUMBER_Pos) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats */
#define UDPHS_FNUM_FNUM_ERR (0x1u << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error */
/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */
#define UDPHS_IEN_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable */
#define UDPHS_IEN_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable */
#define UDPHS_IEN_INT_SOF (0x1u << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable */
#define UDPHS_IEN_ENDRESET (0x1u << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable */
#define UDPHS_IEN_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable */
#define UDPHS_IEN_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable */
#define UDPHS_IEN_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable */
#define UDPHS_IEN_EPT_0 (0x1u << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable */
#define UDPHS_IEN_EPT_1 (0x1u << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable */
#define UDPHS_IEN_EPT_2 (0x1u << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable */
#define UDPHS_IEN_EPT_3 (0x1u << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable */
#define UDPHS_IEN_EPT_4 (0x1u << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable */
#define UDPHS_IEN_EPT_5 (0x1u << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable */
#define UDPHS_IEN_EPT_6 (0x1u << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable */
#define UDPHS_IEN_EPT_7 (0x1u << 15) /**< \brief (UDPHS_IEN) Endpoint 7 Interrupt Enable */
#define UDPHS_IEN_EPT_8 (0x1u << 16) /**< \brief (UDPHS_IEN) Endpoint 8 Interrupt Enable */
#define UDPHS_IEN_EPT_9 (0x1u << 17) /**< \brief (UDPHS_IEN) Endpoint 9 Interrupt Enable */
#define UDPHS_IEN_EPT_10 (0x1u << 18) /**< \brief (UDPHS_IEN) Endpoint 10 Interrupt Enable */
#define UDPHS_IEN_EPT_11 (0x1u << 19) /**< \brief (UDPHS_IEN) Endpoint 11 Interrupt Enable */
#define UDPHS_IEN_EPT_12 (0x1u << 20) /**< \brief (UDPHS_IEN) Endpoint 12 Interrupt Enable */
#define UDPHS_IEN_EPT_13 (0x1u << 21) /**< \brief (UDPHS_IEN) Endpoint 13 Interrupt Enable */
#define UDPHS_IEN_EPT_14 (0x1u << 22) /**< \brief (UDPHS_IEN) Endpoint 14 Interrupt Enable */
#define UDPHS_IEN_EPT_15 (0x1u << 23) /**< \brief (UDPHS_IEN) Endpoint 15 Interrupt Enable */
#define UDPHS_IEN_DMA_1 (0x1u << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable */
#define UDPHS_IEN_DMA_2 (0x1u << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable */
#define UDPHS_IEN_DMA_3 (0x1u << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable */
#define UDPHS_IEN_DMA_4 (0x1u << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable */
#define UDPHS_IEN_DMA_5 (0x1u << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable */
#define UDPHS_IEN_DMA_6 (0x1u << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable */
#define UDPHS_IEN_DMA_7 (0x1u << 31) /**< \brief (UDPHS_IEN) DMA Channel 7 Interrupt Enable */
/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */
#define UDPHS_INTSTA_SPEED (0x1u << 0) /**< \brief (UDPHS_INTSTA) Speed Status */
#define UDPHS_INTSTA_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */
#define UDPHS_INTSTA_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */
#define UDPHS_INTSTA_INT_SOF (0x1u << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */
#define UDPHS_INTSTA_ENDRESET (0x1u << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */
#define UDPHS_INTSTA_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */
#define UDPHS_INTSTA_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */
#define UDPHS_INTSTA_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */
#define UDPHS_INTSTA_EPT_0 (0x1u << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt */
#define UDPHS_INTSTA_EPT_1 (0x1u << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt */
#define UDPHS_INTSTA_EPT_2 (0x1u << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt */
#define UDPHS_INTSTA_EPT_3 (0x1u << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt */
#define UDPHS_INTSTA_EPT_4 (0x1u << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt */
#define UDPHS_INTSTA_EPT_5 (0x1u << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt */
#define UDPHS_INTSTA_EPT_6 (0x1u << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt */
#define UDPHS_INTSTA_EPT_7 (0x1u << 15) /**< \brief (UDPHS_INTSTA) Endpoint 7 Interrupt */
#define UDPHS_INTSTA_EPT_8 (0x1u << 16) /**< \brief (UDPHS_INTSTA) Endpoint 8 Interrupt */
#define UDPHS_INTSTA_EPT_9 (0x1u << 17) /**< \brief (UDPHS_INTSTA) Endpoint 9 Interrupt */
#define UDPHS_INTSTA_EPT_10 (0x1u << 18) /**< \brief (UDPHS_INTSTA) Endpoint 10 Interrupt */
#define UDPHS_INTSTA_EPT_11 (0x1u << 19) /**< \brief (UDPHS_INTSTA) Endpoint 11 Interrupt */
#define UDPHS_INTSTA_EPT_12 (0x1u << 20) /**< \brief (UDPHS_INTSTA) Endpoint 12 Interrupt */
#define UDPHS_INTSTA_EPT_13 (0x1u << 21) /**< \brief (UDPHS_INTSTA) Endpoint 13 Interrupt */
#define UDPHS_INTSTA_EPT_14 (0x1u << 22) /**< \brief (UDPHS_INTSTA) Endpoint 14 Interrupt */
#define UDPHS_INTSTA_EPT_15 (0x1u << 23) /**< \brief (UDPHS_INTSTA) Endpoint 15 Interrupt */
#define UDPHS_INTSTA_DMA_1 (0x1u << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */
#define UDPHS_INTSTA_DMA_2 (0x1u << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */
#define UDPHS_INTSTA_DMA_3 (0x1u << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */
#define UDPHS_INTSTA_DMA_4 (0x1u << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */
#define UDPHS_INTSTA_DMA_5 (0x1u << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */
#define UDPHS_INTSTA_DMA_6 (0x1u << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */
#define UDPHS_INTSTA_DMA_7 (0x1u << 31) /**< \brief (UDPHS_INTSTA) DMA Channel 7 Interrupt */
/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */
#define UDPHS_CLRINT_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */
#define UDPHS_CLRINT_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */
#define UDPHS_CLRINT_INT_SOF (0x1u << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */
#define UDPHS_CLRINT_ENDRESET (0x1u << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */
#define UDPHS_CLRINT_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */
#define UDPHS_CLRINT_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */
#define UDPHS_CLRINT_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */
/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */
#define UDPHS_EPTRST_EPT_0 (0x1u << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */
#define UDPHS_EPTRST_EPT_1 (0x1u << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */
#define UDPHS_EPTRST_EPT_2 (0x1u << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */
#define UDPHS_EPTRST_EPT_3 (0x1u << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */
#define UDPHS_EPTRST_EPT_4 (0x1u << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */
#define UDPHS_EPTRST_EPT_5 (0x1u << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */
#define UDPHS_EPTRST_EPT_6 (0x1u << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */
#define UDPHS_EPTRST_EPT_7 (0x1u << 7) /**< \brief (UDPHS_EPTRST) Endpoint 7 Reset */
#define UDPHS_EPTRST_EPT_8 (0x1u << 8) /**< \brief (UDPHS_EPTRST) Endpoint 8 Reset */
#define UDPHS_EPTRST_EPT_9 (0x1u << 9) /**< \brief (UDPHS_EPTRST) Endpoint 9 Reset */
#define UDPHS_EPTRST_EPT_10 (0x1u << 10) /**< \brief (UDPHS_EPTRST) Endpoint 10 Reset */
#define UDPHS_EPTRST_EPT_11 (0x1u << 11) /**< \brief (UDPHS_EPTRST) Endpoint 11 Reset */
#define UDPHS_EPTRST_EPT_12 (0x1u << 12) /**< \brief (UDPHS_EPTRST) Endpoint 12 Reset */
#define UDPHS_EPTRST_EPT_13 (0x1u << 13) /**< \brief (UDPHS_EPTRST) Endpoint 13 Reset */
#define UDPHS_EPTRST_EPT_14 (0x1u << 14) /**< \brief (UDPHS_EPTRST) Endpoint 14 Reset */
#define UDPHS_EPTRST_EPT_15 (0x1u << 15) /**< \brief (UDPHS_EPTRST) Endpoint 15 Reset */
/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */
#define UDPHS_TST_SPEED_CFG_Pos 0
#define UDPHS_TST_SPEED_CFG_Msk (0x3u << UDPHS_TST_SPEED_CFG_Pos) /**< \brief (UDPHS_TST) Speed Configuration */
#define   UDPHS_TST_SPEED_CFG_NORMAL (0x0u << 0) /**< \brief (UDPHS_TST) Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode */
#define   UDPHS_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) /**< \brief (UDPHS_TST) Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. */
#define   UDPHS_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) /**< \brief (UDPHS_TST) Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. */
#define UDPHS_TST_TST_J (0x1u << 2) /**< \brief (UDPHS_TST) Test J Mode */
#define UDPHS_TST_TST_K (0x1u << 3) /**< \brief (UDPHS_TST) Test K Mode */
#define UDPHS_TST_TST_PKT (0x1u << 4) /**< \brief (UDPHS_TST) Test Packet Mode */
#define UDPHS_TST_OPMODE2 (0x1u << 5) /**< \brief (UDPHS_TST) OpMode2 */
/* -------- UDPHS_IPNAME1 : (UDPHS Offset: 0xF0) UDPHS Name1 Register -------- */
#define UDPHS_IPNAME1_IP_NAME1_Pos 0
#define UDPHS_IPNAME1_IP_NAME1_Msk (0xffffffffu << UDPHS_IPNAME1_IP_NAME1_Pos) /**< \brief (UDPHS_IPNAME1)  */
/* -------- UDPHS_IPNAME2 : (UDPHS Offset: 0xF4) UDPHS Name2 Register -------- */
#define UDPHS_IPNAME2_IP_NAME2_Pos 0
#define UDPHS_IPNAME2_IP_NAME2_Msk (0xffffffffu << UDPHS_IPNAME2_IP_NAME2_Pos) /**< \brief (UDPHS_IPNAME2)  */
/* -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xF8) UDPHS Features Register -------- */
#define UDPHS_IPFEATURES_EPT_NBR_MAX_Pos 0
#define UDPHS_IPFEATURES_EPT_NBR_MAX_Msk (0xfu << UDPHS_IPFEATURES_EPT_NBR_MAX_Pos) /**< \brief (UDPHS_IPFEATURES) Max Number of Endpoints */
#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos 4
#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk (0x7u << UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos) /**< \brief (UDPHS_IPFEATURES) Number of DMA Channels */
#define UDPHS_IPFEATURES_DMA_B_SIZ (0x1u << 7) /**< \brief (UDPHS_IPFEATURES) DMA Buffer Size */
#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos 8
#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Msk (0xfu << UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos) /**< \brief (UDPHS_IPFEATURES) DMA FIFO Depth in Words */
#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos 12
#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Msk (0x7u << UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos) /**< \brief (UDPHS_IPFEATURES) DPRAM Size */
#define UDPHS_IPFEATURES_BW_DPRAM (0x1u << 15) /**< \brief (UDPHS_IPFEATURES) DPRAM Byte Write Capability */
#define UDPHS_IPFEATURES_DATAB16_8 (0x1u << 16) /**< \brief (UDPHS_IPFEATURES) UTMI DataBus16_8 */
#define UDPHS_IPFEATURES_ISO_EPT_1 (0x1u << 17) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_2 (0x1u << 18) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_3 (0x1u << 19) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_4 (0x1u << 20) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_5 (0x1u << 21) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_6 (0x1u << 22) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_7 (0x1u << 23) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_8 (0x1u << 24) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_9 (0x1u << 25) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_10 (0x1u << 26) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_11 (0x1u << 27) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_12 (0x1u << 28) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_13 (0x1u << 29) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_14 (0x1u << 30) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
#define UDPHS_IPFEATURES_ISO_EPT_15 (0x1u << 31) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
/* -------- UDPHS_EPTCFG : (UDPHS Offset: N/A) UDPHS Endpoint Configuration Register -------- */
#define UDPHS_EPTCFG_EPT_SIZE_Pos 0
#define UDPHS_EPTCFG_EPT_SIZE_Msk (0x7u << UDPHS_EPTCFG_EPT_SIZE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Size */
#define   UDPHS_EPTCFG_EPT_SIZE_8 (0x0u << 0) /**< \brief (UDPHS_EPTCFG) 8 bytes */
#define   UDPHS_EPTCFG_EPT_SIZE_16 (0x1u << 0) /**< \brief (UDPHS_EPTCFG) 16 bytes */
#define   UDPHS_EPTCFG_EPT_SIZE_32 (0x2u << 0) /**< \brief (UDPHS_EPTCFG) 32 bytes */
#define   UDPHS_EPTCFG_EPT_SIZE_64 (0x3u << 0) /**< \brief (UDPHS_EPTCFG) 64 bytes */
#define   UDPHS_EPTCFG_EPT_SIZE_128 (0x4u << 0) /**< \brief (UDPHS_EPTCFG) 128 bytes */
#define   UDPHS_EPTCFG_EPT_SIZE_256 (0x5u << 0) /**< \brief (UDPHS_EPTCFG) 256 bytes */
#define   UDPHS_EPTCFG_EPT_SIZE_512 (0x6u << 0) /**< \brief (UDPHS_EPTCFG) 512 bytes */
#define   UDPHS_EPTCFG_EPT_SIZE_1024 (0x7u << 0) /**< \brief (UDPHS_EPTCFG) 1024 bytes */
#define UDPHS_EPTCFG_EPT_DIR (0x1u << 3) /**< \brief (UDPHS_EPTCFG) Endpoint Direction */
#define UDPHS_EPTCFG_EPT_TYPE_Pos 4
#define UDPHS_EPTCFG_EPT_TYPE_Msk (0x3u << UDPHS_EPTCFG_EPT_TYPE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Type */
#define   UDPHS_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) /**< \brief (UDPHS_EPTCFG) Control endpoint */
#define   UDPHS_EPTCFG_EPT_TYPE_ISO (0x1u << 4) /**< \brief (UDPHS_EPTCFG) Isochronous endpoint */
#define   UDPHS_EPTCFG_EPT_TYPE_BULK (0x2u << 4) /**< \brief (UDPHS_EPTCFG) Bulk endpoint */
#define   UDPHS_EPTCFG_EPT_TYPE_INT (0x3u << 4) /**< \brief (UDPHS_EPTCFG) Interrupt endpoint */
#define UDPHS_EPTCFG_BK_NUMBER_Pos 6
#define UDPHS_EPTCFG_BK_NUMBER_Msk (0x3u << UDPHS_EPTCFG_BK_NUMBER_Pos) /**< \brief (UDPHS_EPTCFG) Number of Banks */
#define   UDPHS_EPTCFG_BK_NUMBER_0 (0x0u << 6) /**< \brief (UDPHS_EPTCFG) Zero bank, the endpoint is not mapped in memory */
#define   UDPHS_EPTCFG_BK_NUMBER_1 (0x1u << 6) /**< \brief (UDPHS_EPTCFG) One bank (bank 0) */
#define   UDPHS_EPTCFG_BK_NUMBER_2 (0x2u << 6) /**< \brief (UDPHS_EPTCFG) Double bank (Ping-Pong: bank0/bank1) */
#define   UDPHS_EPTCFG_BK_NUMBER_3 (0x3u << 6) /**< \brief (UDPHS_EPTCFG) Triple bank (bank0/bank1/bank2) */
#define UDPHS_EPTCFG_NB_TRANS_Pos 8
#define UDPHS_EPTCFG_NB_TRANS_Msk (0x3u << UDPHS_EPTCFG_NB_TRANS_Pos) /**< \brief (UDPHS_EPTCFG) Number Of Transaction per Microframe */
#define UDPHS_EPTCFG_NB_TRANS(value) ((UDPHS_EPTCFG_NB_TRANS_Msk & ((value) << UDPHS_EPTCFG_NB_TRANS_Pos)))
#define UDPHS_EPTCFG_EPT_MAPD (0x1u << 31) /**< \brief (UDPHS_EPTCFG) Endpoint Mapped */
/* -------- UDPHS_EPTCTLENB : (UDPHS Offset: N/A) UDPHS Endpoint Control Enable Register -------- */
#define UDPHS_EPTCTLENB_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLENB) Endpoint Enable */
#define UDPHS_EPTCTLENB_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLENB) Packet Auto-Valid Enable */
#define UDPHS_EPTCTLENB_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLENB) Interrupts Disable DMA */
#define UDPHS_EPTCTLENB_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLENB) NYET Disable (Only for High Speed Bulk OUT endpoints) */
#define UDPHS_EPTCTLENB_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLENB) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
#define UDPHS_EPTCTLENB_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLENB) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
#define UDPHS_EPTCTLENB_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLENB) Overflow Error Interrupt Enable */
#define UDPHS_EPTCTLENB_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTLENB) Received OUT Data Interrupt Enable */
#define UDPHS_EPTCTLENB_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLENB) Transmitted IN Data Complete Interrupt Enable */
#define UDPHS_EPTCTLENB_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */
#define UDPHS_EPTCTLENB_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */
#define UDPHS_EPTCTLENB_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP/Error Flow Interrupt Enable */
#define UDPHS_EPTCTLENB_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP/Error Flow Interrupt Enable */
#define UDPHS_EPTCTLENB_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
#define UDPHS_EPTCTLENB_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
#define UDPHS_EPTCTLENB_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
#define UDPHS_EPTCTLENB_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN/Bank Flush Error Interrupt Enable */
#define UDPHS_EPTCTLENB_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN/Bank Flush Error Interrupt Enable */
#define UDPHS_EPTCTLENB_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLENB) NAKOUT Interrupt Enable */
#define UDPHS_EPTCTLENB_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLENB) Busy Bank Interrupt Enable */
#define UDPHS_EPTCTLENB_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLENB) Short Packet Send/Short Packet Interrupt Enable */
/* -------- UDPHS_EPTCTLDIS : (UDPHS Offset: N/A) UDPHS Endpoint Control Disable Register -------- */
#define UDPHS_EPTCTLDIS_EPT_DISABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLDIS) Endpoint Disable */
#define UDPHS_EPTCTLDIS_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLDIS) Packet Auto-Valid Disable */
#define UDPHS_EPTCTLDIS_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLDIS) Interrupts Disable DMA */
#define UDPHS_EPTCTLDIS_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLDIS) NYET Enable (Only for High Speed Bulk OUT endpoints) */
#define UDPHS_EPTCTLDIS_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLDIS) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
#define UDPHS_EPTCTLDIS_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLDIS) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
#define UDPHS_EPTCTLDIS_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLDIS) Overflow Error Interrupt Disable */
#define UDPHS_EPTCTLDIS_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTLDIS) Received OUT Data Interrupt Disable */
#define UDPHS_EPTCTLDIS_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLDIS) Transmitted IN Data Complete Interrupt Disable */
#define UDPHS_EPTCTLDIS_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */
#define UDPHS_EPTCTLDIS_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */
#define UDPHS_EPTCTLDIS_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP/Error Flow Interrupt Disable */
#define UDPHS_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP/Error Flow Interrupt Disable */
#define UDPHS_EPTCTLDIS_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
#define UDPHS_EPTCTLDIS_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
#define UDPHS_EPTCTLDIS_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
#define UDPHS_EPTCTLDIS_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN/bank flush error Interrupt Disable */
#define UDPHS_EPTCTLDIS_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN/bank flush error Interrupt Disable */
#define UDPHS_EPTCTLDIS_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLDIS) NAKOUT Interrupt Disable */
#define UDPHS_EPTCTLDIS_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLDIS) Busy Bank Interrupt Disable */
#define UDPHS_EPTCTLDIS_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLDIS) Short Packet Interrupt Disable */
/* -------- UDPHS_EPTCTL : (UDPHS Offset: N/A) UDPHS Endpoint Control Register -------- */
#define UDPHS_EPTCTL_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTL) Endpoint Enable */
#define UDPHS_EPTCTL_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTL) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
#define UDPHS_EPTCTL_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTL) Interrupt Disables DMA */
#define UDPHS_EPTCTL_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTL) NYET Disable (Only for High Speed Bulk OUT endpoints) */
#define UDPHS_EPTCTL_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTL) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
#define UDPHS_EPTCTL_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTL) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
#define UDPHS_EPTCTL_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTL) Overflow Error Interrupt Enabled */
#define UDPHS_EPTCTL_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTL) Received OUT Data Interrupt Enabled */
#define UDPHS_EPTCTL_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTL) Transmitted IN Data Complete Interrupt Enabled */
#define UDPHS_EPTCTL_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */
#define UDPHS_EPTCTL_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */
#define UDPHS_EPTCTL_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP/Error Flow Interrupt Enabled */
#define UDPHS_EPTCTL_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP/Error Flow Interrupt Enabled */
#define UDPHS_EPTCTL_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
#define UDPHS_EPTCTL_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
#define UDPHS_EPTCTL_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
#define UDPHS_EPTCTL_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN/Bank Flush Error Interrupt Enabled */
#define UDPHS_EPTCTL_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN/Bank Flush Error Interrupt Enabled */
#define UDPHS_EPTCTL_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTL) NAKOUT Interrupt Enabled */
#define UDPHS_EPTCTL_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTL) Busy Bank Interrupt Enabled */
#define UDPHS_EPTCTL_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTL) Short Packet Interrupt Enabled */
/* -------- UDPHS_EPTSETSTA : (UDPHS Offset: N/A) UDPHS Endpoint Set Status Register -------- */
#define UDPHS_EPTSETSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSETSTA) Stall Handshake Request Set */
#define UDPHS_EPTSETSTA_KILL_BANK (0x1u << 9) /**< \brief (UDPHS_EPTSETSTA) KILL Bank Set (for IN Endpoint) */
#define UDPHS_EPTSETSTA_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */
/* -------- UDPHS_EPTCLRSTA : (UDPHS Offset: N/A) UDPHS Endpoint Clear Status Register -------- */
#define UDPHS_EPTCLRSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTCLRSTA) Stall Handshake Request Clear */
#define UDPHS_EPTCLRSTA_TOGGLESQ (0x1u << 6) /**< \brief (UDPHS_EPTCLRSTA) Data Toggle Clear */
#define UDPHS_EPTCLRSTA_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCLRSTA) Received OUT Data Clear */
#define UDPHS_EPTCLRSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCLRSTA) Transmitted IN Data Complete Clear */
#define UDPHS_EPTCLRSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP/Error Flow Clear */
#define UDPHS_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP/Error Flow Clear */
#define UDPHS_EPTCLRSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent/Number of Transaction Error Clear */
#define UDPHS_EPTCLRSTA_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent/Number of Transaction Error Clear */
#define UDPHS_EPTCLRSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN/Bank Flush Error Clear */
#define UDPHS_EPTCLRSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN/Bank Flush Error Clear */
#define UDPHS_EPTCLRSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCLRSTA) NAKOUT Clear */
/* -------- UDPHS_EPTSTA : (UDPHS Offset: N/A) UDPHS Endpoint Status Register -------- */
#define UDPHS_EPTSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSTA) Stall Handshake Request */
#define UDPHS_EPTSTA_TOGGLESQ_STA_Pos 6
#define UDPHS_EPTSTA_TOGGLESQ_STA_Msk (0x3u << UDPHS_EPTSTA_TOGGLESQ_STA_Pos) /**< \brief (UDPHS_EPTSTA) Toggle Sequencing */
#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) /**< \brief (UDPHS_EPTSTA) DATA0 */
#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) /**< \brief (UDPHS_EPTSTA) DATA1 */
#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) /**< \brief (UDPHS_EPTSTA) Data2 (only for High Bandwidth Isochronous Endpoint) */
#define   UDPHS_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) /**< \brief (UDPHS_EPTSTA) MData (only for High Bandwidth Isochronous Endpoint) */
#define UDPHS_EPTSTA_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTSTA) Overflow Error */
#define UDPHS_EPTSTA_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */
#define UDPHS_EPTSTA_KILL_BANK (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */
#define UDPHS_EPTSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTSTA) Transmitted IN Data Complete */
#define UDPHS_EPTSTA_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */
#define UDPHS_EPTSTA_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */
#define UDPHS_EPTSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP/Error Flow */
#define UDPHS_EPTSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP/Error Flow */
#define UDPHS_EPTSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
#define UDPHS_EPTSTA_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
#define UDPHS_EPTSTA_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
#define UDPHS_EPTSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN/Bank Flush Error */
#define UDPHS_EPTSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN/Bank Flush Error */
#define UDPHS_EPTSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTSTA) NAK OUT */
#define UDPHS_EPTSTA_CURRENT_BANK_Pos 16
#define UDPHS_EPTSTA_CURRENT_BANK_Msk (0x3u << UDPHS_EPTSTA_CURRENT_BANK_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */
#define UDPHS_EPTSTA_CONTROL_DIR_Pos 16
#define UDPHS_EPTSTA_CONTROL_DIR_Msk (0x3u << UDPHS_EPTSTA_CONTROL_DIR_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */
#define UDPHS_EPTSTA_BUSY_BANK_STA_Pos 18
#define UDPHS_EPTSTA_BUSY_BANK_STA_Msk (0x3u << UDPHS_EPTSTA_BUSY_BANK_STA_Pos) /**< \brief (UDPHS_EPTSTA) Busy Bank Number */
#define   UDPHS_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x0u << 18) /**< \brief (UDPHS_EPTSTA) 1 busy bank */
#define   UDPHS_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x1u << 18) /**< \brief (UDPHS_EPTSTA) 2 busy banks */
#define   UDPHS_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x2u << 18) /**< \brief (UDPHS_EPTSTA) 3 busy banks */
#define UDPHS_EPTSTA_BYTE_COUNT_Pos 20
#define UDPHS_EPTSTA_BYTE_COUNT_Msk (0x7ffu << UDPHS_EPTSTA_BYTE_COUNT_Pos) /**< \brief (UDPHS_EPTSTA) UDPHS Byte Count */
#define UDPHS_EPTSTA_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTSTA) Short Packet */
/* -------- UDPHS_DMANXTDSC : (UDPHS Offset: N/A) UDPHS DMA Next Descriptor Address Register -------- */
#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos 0
#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UDPHS_DMANXTDSC)  */
#define UDPHS_DMANXTDSC_NXT_DSC_ADD(value) ((UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos)))
/* -------- UDPHS_DMAADDRESS : (UDPHS Offset: N/A) UDPHS DMA Channel Address Register -------- */
#define UDPHS_DMAADDRESS_BUFF_ADD_Pos 0
#define UDPHS_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UDPHS_DMAADDRESS_BUFF_ADD_Pos) /**< \brief (UDPHS_DMAADDRESS)  */
#define UDPHS_DMAADDRESS_BUFF_ADD(value) ((UDPHS_DMAADDRESS_BUFF_ADD_Msk & ((value) << UDPHS_DMAADDRESS_BUFF_ADD_Pos)))
/* -------- UDPHS_DMACONTROL : (UDPHS Offset: N/A) UDPHS DMA Channel Control Register -------- */
#define UDPHS_DMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMACONTROL)  */
#define UDPHS_DMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UDPHS_DMACONTROL) Load Next Channel Transfer Descriptor Enable (Command) */
#define UDPHS_DMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UDPHS_DMACONTROL) End of Transfer Enable (Control) */
#define UDPHS_DMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UDPHS_DMACONTROL) End of Buffer Enable (Control) */
#define UDPHS_DMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UDPHS_DMACONTROL) End of Transfer Interrupt Enable */
#define UDPHS_DMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UDPHS_DMACONTROL) End of Buffer Interrupt Enable */
#define UDPHS_DMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UDPHS_DMACONTROL) Descriptor Loaded Interrupt Enable */
#define UDPHS_DMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UDPHS_DMACONTROL) Burst Lock Enable */
#define UDPHS_DMACONTROL_BUFF_LENGTH_Pos 16
#define UDPHS_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << UDPHS_DMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UDPHS_DMACONTROL) Buffer Byte Length (Write-only) */
#define UDPHS_DMACONTROL_BUFF_LENGTH(value) ((UDPHS_DMACONTROL_BUFF_LENGTH_Msk & ((value) << UDPHS_DMACONTROL_BUFF_LENGTH_Pos)))
/* -------- UDPHS_DMASTATUS : (UDPHS Offset: N/A) UDPHS DMA Channel Status Register -------- */
#define UDPHS_DMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMASTATUS) Channel Enable Status */
#define UDPHS_DMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UDPHS_DMASTATUS) Channel Active Status */
#define UDPHS_DMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UDPHS_DMASTATUS) End of Channel Transfer Status */
#define UDPHS_DMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UDPHS_DMASTATUS) End of Channel Buffer Status */
#define UDPHS_DMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UDPHS_DMASTATUS) Descriptor Loaded Status */
#define UDPHS_DMASTATUS_BUFF_COUNT_Pos 16
#define UDPHS_DMASTATUS_BUFF_COUNT_Msk (0xffffu << UDPHS_DMASTATUS_BUFF_COUNT_Pos) /**< \brief (UDPHS_DMASTATUS) Buffer Byte Count */
#define UDPHS_DMASTATUS_BUFF_COUNT(value) ((UDPHS_DMASTATUS_BUFF_COUNT_Msk & ((value) << UDPHS_DMASTATUS_BUFF_COUNT_Pos)))

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_USART Universal Synchronous Asynchronous Receiver Transmitter */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Usart hardware registers */
typedef struct {
  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
  RoReg Reserved1[5];
  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
  RoReg Reserved2[1];
  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
  RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
  RoReg Reserved3[36];
  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
} Usart;
#endif /* __ASSEMBLY__ */
/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
#define US_MR_USART_MODE_Pos 0
#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
#define US_MR_USCLKS_Pos 4
#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=(DIV=8)) is selected */
#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
#define US_MR_CHRL_Pos 6
#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
#define US_MR_PAR_Pos 9
#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
#define US_MR_NBSTOP_Pos 12
#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
#define US_MR_CHMODE_Pos 14
#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
#define US_MR_MAX_ITERATION_Pos 24
#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
#define US_RHR_RXCHR_Pos 0
#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
#define US_THR_TXCHR_Pos 0
#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
#define US_BRGR_CD_Pos 0
#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
#define US_BRGR_FP_Pos 16
#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
#define US_RTOR_TO_Pos 0
#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
#define US_TTGR_TG_Pos 0
#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
#define US_FIDI_FI_DI_RATIO_Pos 0
#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
#define US_NER_NB_ERRORS_Pos 0
#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
#define US_IF_IRDA_FILTER_Pos 0
#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
#define US_MAN_TX_PL_Pos 0
#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
#define US_MAN_TX_PP_Pos 8
#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
#define US_MAN_RX_PL_Pos 16
#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
#define US_MAN_RX_PP_Pos 24
#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
#define US_WPMR_WPKEY_Pos 8
#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
#define US_WPSR_WPVSRC_Pos 8
#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */

/*@}*/

/* ============================================================================= */
/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
/* ============================================================================= */
/** \addtogroup AT91SAMA5_WDT Watchdog Timer */
/*@{*/

#ifndef __ASSEMBLY__
/** \brief Wdt hardware registers */
typedef struct {
  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
} Wdt;
#endif /* __ASSEMBLY__ */
/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
#define WDT_CR_KEY_Pos 24
#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
#define WDT_MR_WDV_Pos 0
#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
#define WDT_MR_WDD_Pos 16
#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */

/*@}*/

/*@}*/

/* ************************************************************************** */
/*   REGISTER ACCESS DEFINITIONS FOR AT91SAMA5 */
/* ************************************************************************** */
/** \addtogroup AT91SAMA5_reg Registers Access Definitions */
/*@{*/

/* ========== Register definition for AXIMX peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_AXIMX_REMAP                        (0x00800000U) /**< \brief (AXIMX) Remap Register */
#define REG_AXIMX_PERIPH_ID4                   (0x00801FD0U) /**< \brief (AXIMX) Peripheral ID Register 4 */
#define REG_AXIMX_PERIPH_ID5                   (0x00801FD4U) /**< \brief (AXIMX) Peripheral ID Register 5 */
#define REG_AXIMX_PERIPH_ID6                   (0x00801FD8U) /**< \brief (AXIMX) Peripheral ID Register 6 */
#define REG_AXIMX_PERIPH_ID7                   (0x00801FDCU) /**< \brief (AXIMX) Peripheral ID Register 7 */
#define REG_AXIMX_PERIPH_ID0                   (0x00801FE0U) /**< \brief (AXIMX) Peripheral ID Register 0 */
#define REG_AXIMX_PERIPH_ID1                   (0x00801FE4U) /**< \brief (AXIMX) Peripheral ID Register 1 */
#define REG_AXIMX_PERIPH_ID2                   (0x00801FE8U) /**< \brief (AXIMX) Peripheral ID Register 2 */
#define REG_AXIMX_PERIPH_ID3                   (0x00801FECU) /**< \brief (AXIMX) Peripheral ID Register 3 */
#define REG_AXIMX_COMP_ID                      (0x00801FF0U) /**< \brief (AXIMX) Component ID Register */
#define REG_AXIMX_AMIB3_FN_MOD_BM_ISS          (0x00805008U) /**< \brief (AXIMX) AMIB3 Bus Matrix Functionality Modification Register */
#define REG_AXIMX_AMIB3_FN_MOD2                (0x00805024U) /**< \brief (AXIMX) AMIB3 Bypass Merge */
#define REG_AXIMX_ASIB0_READ_QOS               (0x00842100U) /**< \brief (AXIMX) ASIB0 Read Channel QoS Register */
#define REG_AXIMX_ASIB0_WRITE_QOS              (0x00842104U) /**< \brief (AXIMX) ASIB0 Write Channel QoS Register */
#define REG_AXIMX_ASIB1_FN_MOD_AHB             (0x00843028U) /**< \brief (AXIMX) ASIB1 AHB Functionality Modification Register */
#define REG_AXIMX_ASIB1_READ_QOS               (0x00843100U) /**< \brief (AXIMX) ASIB1 Read Channel QoS Register */
#define REG_AXIMX_ASIB1_WRITE_QOS              (0x00843104U) /**< \brief (AXIMX) ASIB1 Write Channel QoS Register */
#define REG_AXIMX_ASIB1_FN_MOD                 (0x00843108U) /**< \brief (AXIMX) ASIB1 Issuing Functionality Modification Register */
#else
#define REG_AXIMX_REMAP               (*(WoReg*)0x00800000U) /**< \brief (AXIMX) Remap Register */
#define REG_AXIMX_PERIPH_ID4          (*(RoReg*)0x00801FD0U) /**< \brief (AXIMX) Peripheral ID Register 4 */
#define REG_AXIMX_PERIPH_ID5          (*(RoReg*)0x00801FD4U) /**< \brief (AXIMX) Peripheral ID Register 5 */
#define REG_AXIMX_PERIPH_ID6          (*(RoReg*)0x00801FD8U) /**< \brief (AXIMX) Peripheral ID Register 6 */
#define REG_AXIMX_PERIPH_ID7          (*(RoReg*)0x00801FDCU) /**< \brief (AXIMX) Peripheral ID Register 7 */
#define REG_AXIMX_PERIPH_ID0          (*(RoReg*)0x00801FE0U) /**< \brief (AXIMX) Peripheral ID Register 0 */
#define REG_AXIMX_PERIPH_ID1          (*(RoReg*)0x00801FE4U) /**< \brief (AXIMX) Peripheral ID Register 1 */
#define REG_AXIMX_PERIPH_ID2          (*(RoReg*)0x00801FE8U) /**< \brief (AXIMX) Peripheral ID Register 2 */
#define REG_AXIMX_PERIPH_ID3          (*(RoReg*)0x00801FECU) /**< \brief (AXIMX) Peripheral ID Register 3 */
#define REG_AXIMX_COMP_ID             (*(RoReg*)0x00801FF0U) /**< \brief (AXIMX) Component ID Register */
#define REG_AXIMX_AMIB3_FN_MOD_BM_ISS (*(RwReg*)0x00805008U) /**< \brief (AXIMX) AMIB3 Bus Matrix Functionality Modification Register */
#define REG_AXIMX_AMIB3_FN_MOD2       (*(RwReg*)0x00805024U) /**< \brief (AXIMX) AMIB3 Bypass Merge */
#define REG_AXIMX_ASIB0_READ_QOS      (*(RwReg*)0x00842100U) /**< \brief (AXIMX) ASIB0 Read Channel QoS Register */
#define REG_AXIMX_ASIB0_WRITE_QOS     (*(RwReg*)0x00842104U) /**< \brief (AXIMX) ASIB0 Write Channel QoS Register */
#define REG_AXIMX_ASIB1_FN_MOD_AHB    (*(RwReg*)0x00843028U) /**< \brief (AXIMX) ASIB1 AHB Functionality Modification Register */
#define REG_AXIMX_ASIB1_READ_QOS      (*(RwReg*)0x00843100U) /**< \brief (AXIMX) ASIB1 Read Channel QoS Register */
#define REG_AXIMX_ASIB1_WRITE_QOS     (*(RwReg*)0x00843104U) /**< \brief (AXIMX) ASIB1 Write Channel QoS Register */
#define REG_AXIMX_ASIB1_FN_MOD        (*(RwReg*)0x00843108U) /**< \brief (AXIMX) ASIB1 Issuing Functionality Modification Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for HSMCI0 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_HSMCI0_CR                          (0xF0000000U) /**< \brief (HSMCI0) Control Register */
#define REG_HSMCI0_MR                          (0xF0000004U) /**< \brief (HSMCI0) Mode Register */
#define REG_HSMCI0_DTOR                        (0xF0000008U) /**< \brief (HSMCI0) Data Timeout Register */
#define REG_HSMCI0_SDCR                        (0xF000000CU) /**< \brief (HSMCI0) SD/SDIO Card Register */
#define REG_HSMCI0_ARGR                        (0xF0000010U) /**< \brief (HSMCI0) Argument Register */
#define REG_HSMCI0_CMDR                        (0xF0000014U) /**< \brief (HSMCI0) Command Register */
#define REG_HSMCI0_BLKR                        (0xF0000018U) /**< \brief (HSMCI0) Block Register */
#define REG_HSMCI0_CSTOR                       (0xF000001CU) /**< \brief (HSMCI0) Completion Signal Timeout Register */
#define REG_HSMCI0_RSPR                        (0xF0000020U) /**< \brief (HSMCI0) Response Register */
#define REG_HSMCI0_RDR                         (0xF0000030U) /**< \brief (HSMCI0) Receive Data Register */
#define REG_HSMCI0_TDR                         (0xF0000034U) /**< \brief (HSMCI0) Transmit Data Register */
#define REG_HSMCI0_SR                          (0xF0000040U) /**< \brief (HSMCI0) Status Register */
#define REG_HSMCI0_IER                         (0xF0000044U) /**< \brief (HSMCI0) Interrupt Enable Register */
#define REG_HSMCI0_IDR                         (0xF0000048U) /**< \brief (HSMCI0) Interrupt Disable Register */
#define REG_HSMCI0_IMR                         (0xF000004CU) /**< \brief (HSMCI0) Interrupt Mask Register */
#define REG_HSMCI0_DMA                         (0xF0000050U) /**< \brief (HSMCI0) DMA Configuration Register */
#define REG_HSMCI0_CFG                         (0xF0000054U) /**< \brief (HSMCI0) Configuration Register */
#define REG_HSMCI0_WPMR                        (0xF00000E4U) /**< \brief (HSMCI0) Write Protection Mode Register */
#define REG_HSMCI0_WPSR                        (0xF00000E8U) /**< \brief (HSMCI0) Write Protection Status Register */
#define REG_HSMCI0_FIFO                        (0xF0000200U) /**< \brief (HSMCI0) FIFO Memory Aperture0 */
#else
#define REG_HSMCI0_CR                 (*(WoReg*)0xF0000000U) /**< \brief (HSMCI0) Control Register */
#define REG_HSMCI0_MR                 (*(RwReg*)0xF0000004U) /**< \brief (HSMCI0) Mode Register */
#define REG_HSMCI0_DTOR               (*(RwReg*)0xF0000008U) /**< \brief (HSMCI0) Data Timeout Register */
#define REG_HSMCI0_SDCR               (*(RwReg*)0xF000000CU) /**< \brief (HSMCI0) SD/SDIO Card Register */
#define REG_HSMCI0_ARGR               (*(RwReg*)0xF0000010U) /**< \brief (HSMCI0) Argument Register */
#define REG_HSMCI0_CMDR               (*(WoReg*)0xF0000014U) /**< \brief (HSMCI0) Command Register */
#define REG_HSMCI0_BLKR               (*(RwReg*)0xF0000018U) /**< \brief (HSMCI0) Block Register */
#define REG_HSMCI0_CSTOR              (*(RwReg*)0xF000001CU) /**< \brief (HSMCI0) Completion Signal Timeout Register */
#define REG_HSMCI0_RSPR               (*(RoReg*)0xF0000020U) /**< \brief (HSMCI0) Response Register */
#define REG_HSMCI0_RDR                (*(RoReg*)0xF0000030U) /**< \brief (HSMCI0) Receive Data Register */
#define REG_HSMCI0_TDR                (*(WoReg*)0xF0000034U) /**< \brief (HSMCI0) Transmit Data Register */
#define REG_HSMCI0_SR                 (*(RoReg*)0xF0000040U) /**< \brief (HSMCI0) Status Register */
#define REG_HSMCI0_IER                (*(WoReg*)0xF0000044U) /**< \brief (HSMCI0) Interrupt Enable Register */
#define REG_HSMCI0_IDR                (*(WoReg*)0xF0000048U) /**< \brief (HSMCI0) Interrupt Disable Register */
#define REG_HSMCI0_IMR                (*(RoReg*)0xF000004CU) /**< \brief (HSMCI0) Interrupt Mask Register */
#define REG_HSMCI0_DMA                (*(RwReg*)0xF0000050U) /**< \brief (HSMCI0) DMA Configuration Register */
#define REG_HSMCI0_CFG                (*(RwReg*)0xF0000054U) /**< \brief (HSMCI0) Configuration Register */
#define REG_HSMCI0_WPMR               (*(RwReg*)0xF00000E4U) /**< \brief (HSMCI0) Write Protection Mode Register */
#define REG_HSMCI0_WPSR               (*(RoReg*)0xF00000E8U) /**< \brief (HSMCI0) Write Protection Status Register */
#define REG_HSMCI0_FIFO               (*(RwReg*)0xF0000200U) /**< \brief (HSMCI0) FIFO Memory Aperture0 */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for SPI0 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_SPI0_CR                            (0xF0004000U) /**< \brief (SPI0) Control Register */
#define REG_SPI0_MR                            (0xF0004004U) /**< \brief (SPI0) Mode Register */
#define REG_SPI0_RDR                           (0xF0004008U) /**< \brief (SPI0) Receive Data Register */
#define REG_SPI0_TDR                           (0xF000400CU) /**< \brief (SPI0) Transmit Data Register */
#define REG_SPI0_SR                            (0xF0004010U) /**< \brief (SPI0) Status Register */
#define REG_SPI0_IER                           (0xF0004014U) /**< \brief (SPI0) Interrupt Enable Register */
#define REG_SPI0_IDR                           (0xF0004018U) /**< \brief (SPI0) Interrupt Disable Register */
#define REG_SPI0_IMR                           (0xF000401CU) /**< \brief (SPI0) Interrupt Mask Register */
#define REG_SPI0_CSR                           (0xF0004030U) /**< \brief (SPI0) Chip Select Register */
#define REG_SPI0_WPMR                          (0xF00040E4U) /**< \brief (SPI0) Write Protection Control Register */
#define REG_SPI0_WPSR                          (0xF00040E8U) /**< \brief (SPI0) Write Protection Status Register */
#else
#define REG_SPI0_CR                   (*(WoReg*)0xF0004000U) /**< \brief (SPI0) Control Register */
#define REG_SPI0_MR                   (*(RwReg*)0xF0004004U) /**< \brief (SPI0) Mode Register */
#define REG_SPI0_RDR                  (*(RoReg*)0xF0004008U) /**< \brief (SPI0) Receive Data Register */
#define REG_SPI0_TDR                  (*(WoReg*)0xF000400CU) /**< \brief (SPI0) Transmit Data Register */
#define REG_SPI0_SR                   (*(RoReg*)0xF0004010U) /**< \brief (SPI0) Status Register */
#define REG_SPI0_IER                  (*(WoReg*)0xF0004014U) /**< \brief (SPI0) Interrupt Enable Register */
#define REG_SPI0_IDR                  (*(WoReg*)0xF0004018U) /**< \brief (SPI0) Interrupt Disable Register */
#define REG_SPI0_IMR                  (*(RoReg*)0xF000401CU) /**< \brief (SPI0) Interrupt Mask Register */
#define REG_SPI0_CSR                  (*(RwReg*)0xF0004030U) /**< \brief (SPI0) Chip Select Register */
#define REG_SPI0_WPMR                 (*(RwReg*)0xF00040E4U) /**< \brief (SPI0) Write Protection Control Register */
#define REG_SPI0_WPSR                 (*(RoReg*)0xF00040E8U) /**< \brief (SPI0) Write Protection Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for SSC0 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_SSC0_CR                            (0xF0008000U) /**< \brief (SSC0) Control Register */
#define REG_SSC0_CMR                           (0xF0008004U) /**< \brief (SSC0) Clock Mode Register */
#define REG_SSC0_RCMR                          (0xF0008010U) /**< \brief (SSC0) Receive Clock Mode Register */
#define REG_SSC0_RFMR                          (0xF0008014U) /**< \brief (SSC0) Receive Frame Mode Register */
#define REG_SSC0_TCMR                          (0xF0008018U) /**< \brief (SSC0) Transmit Clock Mode Register */
#define REG_SSC0_TFMR                          (0xF000801CU) /**< \brief (SSC0) Transmit Frame Mode Register */
#define REG_SSC0_RHR                           (0xF0008020U) /**< \brief (SSC0) Receive Holding Register */
#define REG_SSC0_THR                           (0xF0008024U) /**< \brief (SSC0) Transmit Holding Register */
#define REG_SSC0_RSHR                          (0xF0008030U) /**< \brief (SSC0) Receive Sync. Holding Register */
#define REG_SSC0_TSHR                          (0xF0008034U) /**< \brief (SSC0) Transmit Sync. Holding Register */
#define REG_SSC0_RC0R                          (0xF0008038U) /**< \brief (SSC0) Receive Compare 0 Register */
#define REG_SSC0_RC1R                          (0xF000803CU) /**< \brief (SSC0) Receive Compare 1 Register */
#define REG_SSC0_SR                            (0xF0008040U) /**< \brief (SSC0) Status Register */
#define REG_SSC0_IER                           (0xF0008044U) /**< \brief (SSC0) Interrupt Enable Register */
#define REG_SSC0_IDR                           (0xF0008048U) /**< \brief (SSC0) Interrupt Disable Register */
#define REG_SSC0_IMR                           (0xF000804CU) /**< \brief (SSC0) Interrupt Mask Register */
#define REG_SSC0_WPMR                          (0xF00080E4U) /**< \brief (SSC0) Write Protect Mode Register */
#define REG_SSC0_WPSR                          (0xF00080E8U) /**< \brief (SSC0) Write Protect Status Register */
#else
#define REG_SSC0_CR                   (*(WoReg*)0xF0008000U) /**< \brief (SSC0) Control Register */
#define REG_SSC0_CMR                  (*(RwReg*)0xF0008004U) /**< \brief (SSC0) Clock Mode Register */
#define REG_SSC0_RCMR                 (*(RwReg*)0xF0008010U) /**< \brief (SSC0) Receive Clock Mode Register */
#define REG_SSC0_RFMR                 (*(RwReg*)0xF0008014U) /**< \brief (SSC0) Receive Frame Mode Register */
#define REG_SSC0_TCMR                 (*(RwReg*)0xF0008018U) /**< \brief (SSC0) Transmit Clock Mode Register */
#define REG_SSC0_TFMR                 (*(RwReg*)0xF000801CU) /**< \brief (SSC0) Transmit Frame Mode Register */
#define REG_SSC0_RHR                  (*(RoReg*)0xF0008020U) /**< \brief (SSC0) Receive Holding Register */
#define REG_SSC0_THR                  (*(WoReg*)0xF0008024U) /**< \brief (SSC0) Transmit Holding Register */
#define REG_SSC0_RSHR                 (*(RoReg*)0xF0008030U) /**< \brief (SSC0) Receive Sync. Holding Register */
#define REG_SSC0_TSHR                 (*(RwReg*)0xF0008034U) /**< \brief (SSC0) Transmit Sync. Holding Register */
#define REG_SSC0_RC0R                 (*(RwReg*)0xF0008038U) /**< \brief (SSC0) Receive Compare 0 Register */
#define REG_SSC0_RC1R                 (*(RwReg*)0xF000803CU) /**< \brief (SSC0) Receive Compare 1 Register */
#define REG_SSC0_SR                   (*(RoReg*)0xF0008040U) /**< \brief (SSC0) Status Register */
#define REG_SSC0_IER                  (*(WoReg*)0xF0008044U) /**< \brief (SSC0) Interrupt Enable Register */
#define REG_SSC0_IDR                  (*(WoReg*)0xF0008048U) /**< \brief (SSC0) Interrupt Disable Register */
#define REG_SSC0_IMR                  (*(RoReg*)0xF000804CU) /**< \brief (SSC0) Interrupt Mask Register */
#define REG_SSC0_WPMR                 (*(RwReg*)0xF00080E4U) /**< \brief (SSC0) Write Protect Mode Register */
#define REG_SSC0_WPSR                 (*(RoReg*)0xF00080E8U) /**< \brief (SSC0) Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for CAN0 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_CAN0_MR                            (0xF000C000U) /**< \brief (CAN0) Mode Register */
#define REG_CAN0_IER                           (0xF000C004U) /**< \brief (CAN0) Interrupt Enable Register */
#define REG_CAN0_IDR                           (0xF000C008U) /**< \brief (CAN0) Interrupt Disable Register */
#define REG_CAN0_IMR                           (0xF000C00CU) /**< \brief (CAN0) Interrupt Mask Register */
#define REG_CAN0_SR                            (0xF000C010U) /**< \brief (CAN0) Status Register */
#define REG_CAN0_BR                            (0xF000C014U) /**< \brief (CAN0) Baudrate Register */
#define REG_CAN0_TIM                           (0xF000C018U) /**< \brief (CAN0) Timer Register */
#define REG_CAN0_TIMESTP                       (0xF000C01CU) /**< \brief (CAN0) Timestamp Register */
#define REG_CAN0_ECR                           (0xF000C020U) /**< \brief (CAN0) Error Counter Register */
#define REG_CAN0_TCR                           (0xF000C024U) /**< \brief (CAN0) Transfer Command Register */
#define REG_CAN0_ACR                           (0xF000C028U) /**< \brief (CAN0) Abort Command Register */
#define REG_CAN0_MMR0                          (0xF000C200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */
#define REG_CAN0_MAM0                          (0xF000C204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */
#define REG_CAN0_MID0                          (0xF000C208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */
#define REG_CAN0_MFID0                         (0xF000C20CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */
#define REG_CAN0_MSR0                          (0xF000C210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */
#define REG_CAN0_MDL0                          (0xF000C214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */
#define REG_CAN0_MDH0                          (0xF000C218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */
#define REG_CAN0_MCR0                          (0xF000C21CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */
#define REG_CAN0_MMR1                          (0xF000C220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */
#define REG_CAN0_MAM1                          (0xF000C224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */
#define REG_CAN0_MID1                          (0xF000C228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */
#define REG_CAN0_MFID1                         (0xF000C22CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */
#define REG_CAN0_MSR1                          (0xF000C230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */
#define REG_CAN0_MDL1                          (0xF000C234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */
#define REG_CAN0_MDH1                          (0xF000C238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */
#define REG_CAN0_MCR1                          (0xF000C23CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */
#define REG_CAN0_MMR2                          (0xF000C240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */
#define REG_CAN0_MAM2                          (0xF000C244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */
#define REG_CAN0_MID2                          (0xF000C248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */
#define REG_CAN0_MFID2                         (0xF000C24CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */
#define REG_CAN0_MSR2                          (0xF000C250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */
#define REG_CAN0_MDL2                          (0xF000C254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */
#define REG_CAN0_MDH2                          (0xF000C258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */
#define REG_CAN0_MCR2                          (0xF000C25CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */
#define REG_CAN0_MMR3                          (0xF000C260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */
#define REG_CAN0_MAM3                          (0xF000C264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */
#define REG_CAN0_MID3                          (0xF000C268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */
#define REG_CAN0_MFID3                         (0xF000C26CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */
#define REG_CAN0_MSR3                          (0xF000C270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */
#define REG_CAN0_MDL3                          (0xF000C274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */
#define REG_CAN0_MDH3                          (0xF000C278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */
#define REG_CAN0_MCR3                          (0xF000C27CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */
#define REG_CAN0_MMR4                          (0xF000C280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */
#define REG_CAN0_MAM4                          (0xF000C284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */
#define REG_CAN0_MID4                          (0xF000C288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */
#define REG_CAN0_MFID4                         (0xF000C28CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */
#define REG_CAN0_MSR4                          (0xF000C290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */
#define REG_CAN0_MDL4                          (0xF000C294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */
#define REG_CAN0_MDH4                          (0xF000C298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */
#define REG_CAN0_MCR4                          (0xF000C29CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */
#define REG_CAN0_MMR5                          (0xF000C2A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */
#define REG_CAN0_MAM5                          (0xF000C2A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */
#define REG_CAN0_MID5                          (0xF000C2A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */
#define REG_CAN0_MFID5                         (0xF000C2ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */
#define REG_CAN0_MSR5                          (0xF000C2B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */
#define REG_CAN0_MDL5                          (0xF000C2B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */
#define REG_CAN0_MDH5                          (0xF000C2B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */
#define REG_CAN0_MCR5                          (0xF000C2BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */
#define REG_CAN0_MMR6                          (0xF000C2C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */
#define REG_CAN0_MAM6                          (0xF000C2C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */
#define REG_CAN0_MID6                          (0xF000C2C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */
#define REG_CAN0_MFID6                         (0xF000C2CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */
#define REG_CAN0_MSR6                          (0xF000C2D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */
#define REG_CAN0_MDL6                          (0xF000C2D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */
#define REG_CAN0_MDH6                          (0xF000C2D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */
#define REG_CAN0_MCR6                          (0xF000C2DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */
#define REG_CAN0_MMR7                          (0xF000C2E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */
#define REG_CAN0_MAM7                          (0xF000C2E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */
#define REG_CAN0_MID7                          (0xF000C2E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */
#define REG_CAN0_MFID7                         (0xF000C2ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */
#define REG_CAN0_MSR7                          (0xF000C2F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */
#define REG_CAN0_MDL7                          (0xF000C2F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */
#define REG_CAN0_MDH7                          (0xF000C2F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */
#define REG_CAN0_MCR7                          (0xF000C2FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */
#else
#define REG_CAN0_MR                   (*(RwReg*)0xF000C000U) /**< \brief (CAN0) Mode Register */
#define REG_CAN0_IER                  (*(WoReg*)0xF000C004U) /**< \brief (CAN0) Interrupt Enable Register */
#define REG_CAN0_IDR                  (*(WoReg*)0xF000C008U) /**< \brief (CAN0) Interrupt Disable Register */
#define REG_CAN0_IMR                  (*(RoReg*)0xF000C00CU) /**< \brief (CAN0) Interrupt Mask Register */
#define REG_CAN0_SR                   (*(RoReg*)0xF000C010U) /**< \brief (CAN0) Status Register */
#define REG_CAN0_BR                   (*(RwReg*)0xF000C014U) /**< \brief (CAN0) Baudrate Register */
#define REG_CAN0_TIM                  (*(RoReg*)0xF000C018U) /**< \brief (CAN0) Timer Register */
#define REG_CAN0_TIMESTP              (*(RoReg*)0xF000C01CU) /**< \brief (CAN0) Timestamp Register */
#define REG_CAN0_ECR                  (*(RoReg*)0xF000C020U) /**< \brief (CAN0) Error Counter Register */
#define REG_CAN0_TCR                  (*(WoReg*)0xF000C024U) /**< \brief (CAN0) Transfer Command Register */
#define REG_CAN0_ACR                  (*(WoReg*)0xF000C028U) /**< \brief (CAN0) Abort Command Register */
#define REG_CAN0_MMR0                 (*(RwReg*)0xF000C200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */
#define REG_CAN0_MAM0                 (*(RwReg*)0xF000C204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */
#define REG_CAN0_MID0                 (*(RwReg*)0xF000C208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */
#define REG_CAN0_MFID0                (*(RoReg*)0xF000C20CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */
#define REG_CAN0_MSR0                 (*(RoReg*)0xF000C210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */
#define REG_CAN0_MDL0                 (*(RwReg*)0xF000C214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */
#define REG_CAN0_MDH0                 (*(RwReg*)0xF000C218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */
#define REG_CAN0_MCR0                 (*(WoReg*)0xF000C21CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */
#define REG_CAN0_MMR1                 (*(RwReg*)0xF000C220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */
#define REG_CAN0_MAM1                 (*(RwReg*)0xF000C224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */
#define REG_CAN0_MID1                 (*(RwReg*)0xF000C228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */
#define REG_CAN0_MFID1                (*(RoReg*)0xF000C22CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */
#define REG_CAN0_MSR1                 (*(RoReg*)0xF000C230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */
#define REG_CAN0_MDL1                 (*(RwReg*)0xF000C234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */
#define REG_CAN0_MDH1                 (*(RwReg*)0xF000C238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */
#define REG_CAN0_MCR1                 (*(WoReg*)0xF000C23CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */
#define REG_CAN0_MMR2                 (*(RwReg*)0xF000C240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */
#define REG_CAN0_MAM2                 (*(RwReg*)0xF000C244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */
#define REG_CAN0_MID2                 (*(RwReg*)0xF000C248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */
#define REG_CAN0_MFID2                (*(RoReg*)0xF000C24CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */
#define REG_CAN0_MSR2                 (*(RoReg*)0xF000C250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */
#define REG_CAN0_MDL2                 (*(RwReg*)0xF000C254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */
#define REG_CAN0_MDH2                 (*(RwReg*)0xF000C258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */
#define REG_CAN0_MCR2                 (*(WoReg*)0xF000C25CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */
#define REG_CAN0_MMR3                 (*(RwReg*)0xF000C260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */
#define REG_CAN0_MAM3                 (*(RwReg*)0xF000C264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */
#define REG_CAN0_MID3                 (*(RwReg*)0xF000C268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */
#define REG_CAN0_MFID3                (*(RoReg*)0xF000C26CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */
#define REG_CAN0_MSR3                 (*(RoReg*)0xF000C270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */
#define REG_CAN0_MDL3                 (*(RwReg*)0xF000C274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */
#define REG_CAN0_MDH3                 (*(RwReg*)0xF000C278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */
#define REG_CAN0_MCR3                 (*(WoReg*)0xF000C27CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */
#define REG_CAN0_MMR4                 (*(RwReg*)0xF000C280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */
#define REG_CAN0_MAM4                 (*(RwReg*)0xF000C284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */
#define REG_CAN0_MID4                 (*(RwReg*)0xF000C288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */
#define REG_CAN0_MFID4                (*(RoReg*)0xF000C28CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */
#define REG_CAN0_MSR4                 (*(RoReg*)0xF000C290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */
#define REG_CAN0_MDL4                 (*(RwReg*)0xF000C294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */
#define REG_CAN0_MDH4                 (*(RwReg*)0xF000C298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */
#define REG_CAN0_MCR4                 (*(WoReg*)0xF000C29CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */
#define REG_CAN0_MMR5                 (*(RwReg*)0xF000C2A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */
#define REG_CAN0_MAM5                 (*(RwReg*)0xF000C2A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */
#define REG_CAN0_MID5                 (*(RwReg*)0xF000C2A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */
#define REG_CAN0_MFID5                (*(RoReg*)0xF000C2ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */
#define REG_CAN0_MSR5                 (*(RoReg*)0xF000C2B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */
#define REG_CAN0_MDL5                 (*(RwReg*)0xF000C2B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */
#define REG_CAN0_MDH5                 (*(RwReg*)0xF000C2B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */
#define REG_CAN0_MCR5                 (*(WoReg*)0xF000C2BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */
#define REG_CAN0_MMR6                 (*(RwReg*)0xF000C2C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */
#define REG_CAN0_MAM6                 (*(RwReg*)0xF000C2C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */
#define REG_CAN0_MID6                 (*(RwReg*)0xF000C2C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */
#define REG_CAN0_MFID6                (*(RoReg*)0xF000C2CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */
#define REG_CAN0_MSR6                 (*(RoReg*)0xF000C2D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */
#define REG_CAN0_MDL6                 (*(RwReg*)0xF000C2D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */
#define REG_CAN0_MDH6                 (*(RwReg*)0xF000C2D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */
#define REG_CAN0_MCR6                 (*(WoReg*)0xF000C2DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */
#define REG_CAN0_MMR7                 (*(RwReg*)0xF000C2E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */
#define REG_CAN0_MAM7                 (*(RwReg*)0xF000C2E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */
#define REG_CAN0_MID7                 (*(RwReg*)0xF000C2E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */
#define REG_CAN0_MFID7                (*(RoReg*)0xF000C2ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */
#define REG_CAN0_MSR7                 (*(RoReg*)0xF000C2F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */
#define REG_CAN0_MDL7                 (*(RwReg*)0xF000C2F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */
#define REG_CAN0_MDH7                 (*(RwReg*)0xF000C2F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */
#define REG_CAN0_MCR7                 (*(WoReg*)0xF000C2FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for TC0 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_TC0_CCR0                           (0xF0010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
#define REG_TC0_CMR0                           (0xF0010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
#define REG_TC0_SMMR0                          (0xF0010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
#define REG_TC0_RAB0                           (0xF001000CU) /**< \brief (TC0) Register AB (channel = 0) */
#define REG_TC0_CV0                            (0xF0010010U) /**< \brief (TC0) Counter Value (channel = 0) */
#define REG_TC0_RA0                            (0xF0010014U) /**< \brief (TC0) Register A (channel = 0) */
#define REG_TC0_RB0                            (0xF0010018U) /**< \brief (TC0) Register B (channel = 0) */
#define REG_TC0_RC0                            (0xF001001CU) /**< \brief (TC0) Register C (channel = 0) */
#define REG_TC0_SR0                            (0xF0010020U) /**< \brief (TC0) Status Register (channel = 0) */
#define REG_TC0_IER0                           (0xF0010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
#define REG_TC0_IDR0                           (0xF0010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
#define REG_TC0_IMR0                           (0xF001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
#define REG_TC0_CCR1                           (0xF0010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
#define REG_TC0_CMR1                           (0xF0010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
#define REG_TC0_SMMR1                          (0xF0010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
#define REG_TC0_RAB1                           (0xF001004CU) /**< \brief (TC0) Register AB (channel = 1) */
#define REG_TC0_CV1                            (0xF0010050U) /**< \brief (TC0) Counter Value (channel = 1) */
#define REG_TC0_RA1                            (0xF0010054U) /**< \brief (TC0) Register A (channel = 1) */
#define REG_TC0_RB1                            (0xF0010058U) /**< \brief (TC0) Register B (channel = 1) */
#define REG_TC0_RC1                            (0xF001005CU) /**< \brief (TC0) Register C (channel = 1) */
#define REG_TC0_SR1                            (0xF0010060U) /**< \brief (TC0) Status Register (channel = 1) */
#define REG_TC0_IER1                           (0xF0010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
#define REG_TC0_IDR1                           (0xF0010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
#define REG_TC0_IMR1                           (0xF001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
#define REG_TC0_CCR2                           (0xF0010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
#define REG_TC0_CMR2                           (0xF0010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
#define REG_TC0_SMMR2                          (0xF0010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
#define REG_TC0_RAB2                           (0xF001008CU) /**< \brief (TC0) Register AB (channel = 2) */
#define REG_TC0_CV2                            (0xF0010090U) /**< \brief (TC0) Counter Value (channel = 2) */
#define REG_TC0_RA2                            (0xF0010094U) /**< \brief (TC0) Register A (channel = 2) */
#define REG_TC0_RB2                            (0xF0010098U) /**< \brief (TC0) Register B (channel = 2) */
#define REG_TC0_RC2                            (0xF001009CU) /**< \brief (TC0) Register C (channel = 2) */
#define REG_TC0_SR2                            (0xF00100A0U) /**< \brief (TC0) Status Register (channel = 2) */
#define REG_TC0_IER2                           (0xF00100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
#define REG_TC0_IDR2                           (0xF00100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
#define REG_TC0_IMR2                           (0xF00100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
#define REG_TC0_BCR                            (0xF00100C0U) /**< \brief (TC0) Block Control Register */
#define REG_TC0_BMR                            (0xF00100C4U) /**< \brief (TC0) Block Mode Register */
#define REG_TC0_WPMR                           (0xF00100E4U) /**< \brief (TC0) Write Protect Mode Register */
#else
#define REG_TC0_CCR0                  (*(WoReg*)0xF0010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
#define REG_TC0_CMR0                  (*(RwReg*)0xF0010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
#define REG_TC0_SMMR0                 (*(RwReg*)0xF0010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
#define REG_TC0_RAB0                  (*(RoReg*)0xF001000CU) /**< \brief (TC0) Register AB (channel = 0) */
#define REG_TC0_CV0                   (*(RoReg*)0xF0010010U) /**< \brief (TC0) Counter Value (channel = 0) */
#define REG_TC0_RA0                   (*(RwReg*)0xF0010014U) /**< \brief (TC0) Register A (channel = 0) */
#define REG_TC0_RB0                   (*(RwReg*)0xF0010018U) /**< \brief (TC0) Register B (channel = 0) */
#define REG_TC0_RC0                   (*(RwReg*)0xF001001CU) /**< \brief (TC0) Register C (channel = 0) */
#define REG_TC0_SR0                   (*(RoReg*)0xF0010020U) /**< \brief (TC0) Status Register (channel = 0) */
#define REG_TC0_IER0                  (*(WoReg*)0xF0010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
#define REG_TC0_IDR0                  (*(WoReg*)0xF0010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
#define REG_TC0_IMR0                  (*(RoReg*)0xF001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
#define REG_TC0_CCR1                  (*(WoReg*)0xF0010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
#define REG_TC0_CMR1                  (*(RwReg*)0xF0010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
#define REG_TC0_SMMR1                 (*(RwReg*)0xF0010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
#define REG_TC0_RAB1                  (*(RoReg*)0xF001004CU) /**< \brief (TC0) Register AB (channel = 1) */
#define REG_TC0_CV1                   (*(RoReg*)0xF0010050U) /**< \brief (TC0) Counter Value (channel = 1) */
#define REG_TC0_RA1                   (*(RwReg*)0xF0010054U) /**< \brief (TC0) Register A (channel = 1) */
#define REG_TC0_RB1                   (*(RwReg*)0xF0010058U) /**< \brief (TC0) Register B (channel = 1) */
#define REG_TC0_RC1                   (*(RwReg*)0xF001005CU) /**< \brief (TC0) Register C (channel = 1) */
#define REG_TC0_SR1                   (*(RoReg*)0xF0010060U) /**< \brief (TC0) Status Register (channel = 1) */
#define REG_TC0_IER1                  (*(WoReg*)0xF0010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
#define REG_TC0_IDR1                  (*(WoReg*)0xF0010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
#define REG_TC0_IMR1                  (*(RoReg*)0xF001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
#define REG_TC0_CCR2                  (*(WoReg*)0xF0010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
#define REG_TC0_CMR2                  (*(RwReg*)0xF0010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
#define REG_TC0_SMMR2                 (*(RwReg*)0xF0010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
#define REG_TC0_RAB2                  (*(RoReg*)0xF001008CU) /**< \brief (TC0) Register AB (channel = 2) */
#define REG_TC0_CV2                   (*(RoReg*)0xF0010090U) /**< \brief (TC0) Counter Value (channel = 2) */
#define REG_TC0_RA2                   (*(RwReg*)0xF0010094U) /**< \brief (TC0) Register A (channel = 2) */
#define REG_TC0_RB2                   (*(RwReg*)0xF0010098U) /**< \brief (TC0) Register B (channel = 2) */
#define REG_TC0_RC2                   (*(RwReg*)0xF001009CU) /**< \brief (TC0) Register C (channel = 2) */
#define REG_TC0_SR2                   (*(RoReg*)0xF00100A0U) /**< \brief (TC0) Status Register (channel = 2) */
#define REG_TC0_IER2                  (*(WoReg*)0xF00100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
#define REG_TC0_IDR2                  (*(WoReg*)0xF00100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
#define REG_TC0_IMR2                  (*(RoReg*)0xF00100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
#define REG_TC0_BCR                   (*(WoReg*)0xF00100C0U) /**< \brief (TC0) Block Control Register */
#define REG_TC0_BMR                   (*(RwReg*)0xF00100C4U) /**< \brief (TC0) Block Mode Register */
#define REG_TC0_WPMR                  (*(RwReg*)0xF00100E4U) /**< \brief (TC0) Write Protect Mode Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for TWI0 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_TWI0_CR                            (0xF0014000U) /**< \brief (TWI0) Control Register */
#define REG_TWI0_MMR                           (0xF0014004U) /**< \brief (TWI0) Master Mode Register */
#define REG_TWI0_SMR                           (0xF0014008U) /**< \brief (TWI0) Slave Mode Register */
#define REG_TWI0_IADR                          (0xF001400CU) /**< \brief (TWI0) Internal Address Register */
#define REG_TWI0_CWGR                          (0xF0014010U) /**< \brief (TWI0) Clock Waveform Generator Register */
#define REG_TWI0_SR                            (0xF0014020U) /**< \brief (TWI0) Status Register */
#define REG_TWI0_IER                           (0xF0014024U) /**< \brief (TWI0) Interrupt Enable Register */
#define REG_TWI0_IDR                           (0xF0014028U) /**< \brief (TWI0) Interrupt Disable Register */
#define REG_TWI0_IMR                           (0xF001402CU) /**< \brief (TWI0) Interrupt Mask Register */
#define REG_TWI0_RHR                           (0xF0014030U) /**< \brief (TWI0) Receive Holding Register */
#define REG_TWI0_THR                           (0xF0014034U) /**< \brief (TWI0) Transmit Holding Register */
#define REG_TWI0_WPROT_MODE                    (0xF00140E4U) /**< \brief (TWI0) Protection Mode Register */
#define REG_TWI0_WPROT_STATUS                  (0xF00140E8U) /**< \brief (TWI0) Protection Status Register */
#else
#define REG_TWI0_CR                   (*(WoReg*)0xF0014000U) /**< \brief (TWI0) Control Register */
#define REG_TWI0_MMR                  (*(RwReg*)0xF0014004U) /**< \brief (TWI0) Master Mode Register */
#define REG_TWI0_SMR                  (*(RwReg*)0xF0014008U) /**< \brief (TWI0) Slave Mode Register */
#define REG_TWI0_IADR                 (*(RwReg*)0xF001400CU) /**< \brief (TWI0) Internal Address Register */
#define REG_TWI0_CWGR                 (*(RwReg*)0xF0014010U) /**< \brief (TWI0) Clock Waveform Generator Register */
#define REG_TWI0_SR                   (*(RoReg*)0xF0014020U) /**< \brief (TWI0) Status Register */
#define REG_TWI0_IER                  (*(WoReg*)0xF0014024U) /**< \brief (TWI0) Interrupt Enable Register */
#define REG_TWI0_IDR                  (*(WoReg*)0xF0014028U) /**< \brief (TWI0) Interrupt Disable Register */
#define REG_TWI0_IMR                  (*(RoReg*)0xF001402CU) /**< \brief (TWI0) Interrupt Mask Register */
#define REG_TWI0_RHR                  (*(RoReg*)0xF0014030U) /**< \brief (TWI0) Receive Holding Register */
#define REG_TWI0_THR                  (*(WoReg*)0xF0014034U) /**< \brief (TWI0) Transmit Holding Register */
#define REG_TWI0_WPROT_MODE           (*(RwReg*)0xF00140E4U) /**< \brief (TWI0) Protection Mode Register */
#define REG_TWI0_WPROT_STATUS         (*(RoReg*)0xF00140E8U) /**< \brief (TWI0) Protection Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for TWI1 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_TWI1_CR                            (0xF0018000U) /**< \brief (TWI1) Control Register */
#define REG_TWI1_MMR                           (0xF0018004U) /**< \brief (TWI1) Master Mode Register */
#define REG_TWI1_SMR                           (0xF0018008U) /**< \brief (TWI1) Slave Mode Register */
#define REG_TWI1_IADR                          (0xF001800CU) /**< \brief (TWI1) Internal Address Register */
#define REG_TWI1_CWGR                          (0xF0018010U) /**< \brief (TWI1) Clock Waveform Generator Register */
#define REG_TWI1_SR                            (0xF0018020U) /**< \brief (TWI1) Status Register */
#define REG_TWI1_IER                           (0xF0018024U) /**< \brief (TWI1) Interrupt Enable Register */
#define REG_TWI1_IDR                           (0xF0018028U) /**< \brief (TWI1) Interrupt Disable Register */
#define REG_TWI1_IMR                           (0xF001802CU) /**< \brief (TWI1) Interrupt Mask Register */
#define REG_TWI1_RHR                           (0xF0018030U) /**< \brief (TWI1) Receive Holding Register */
#define REG_TWI1_THR                           (0xF0018034U) /**< \brief (TWI1) Transmit Holding Register */
#define REG_TWI1_WPROT_MODE                    (0xF00180E4U) /**< \brief (TWI1) Protection Mode Register */
#define REG_TWI1_WPROT_STATUS                  (0xF00180E8U) /**< \brief (TWI1) Protection Status Register */
#else
#define REG_TWI1_CR                   (*(WoReg*)0xF0018000U) /**< \brief (TWI1) Control Register */
#define REG_TWI1_MMR                  (*(RwReg*)0xF0018004U) /**< \brief (TWI1) Master Mode Register */
#define REG_TWI1_SMR                  (*(RwReg*)0xF0018008U) /**< \brief (TWI1) Slave Mode Register */
#define REG_TWI1_IADR                 (*(RwReg*)0xF001800CU) /**< \brief (TWI1) Internal Address Register */
#define REG_TWI1_CWGR                 (*(RwReg*)0xF0018010U) /**< \brief (TWI1) Clock Waveform Generator Register */
#define REG_TWI1_SR                   (*(RoReg*)0xF0018020U) /**< \brief (TWI1) Status Register */
#define REG_TWI1_IER                  (*(WoReg*)0xF0018024U) /**< \brief (TWI1) Interrupt Enable Register */
#define REG_TWI1_IDR                  (*(WoReg*)0xF0018028U) /**< \brief (TWI1) Interrupt Disable Register */
#define REG_TWI1_IMR                  (*(RoReg*)0xF001802CU) /**< \brief (TWI1) Interrupt Mask Register */
#define REG_TWI1_RHR                  (*(RoReg*)0xF0018030U) /**< \brief (TWI1) Receive Holding Register */
#define REG_TWI1_THR                  (*(WoReg*)0xF0018034U) /**< \brief (TWI1) Transmit Holding Register */
#define REG_TWI1_WPROT_MODE           (*(RwReg*)0xF00180E4U) /**< \brief (TWI1) Protection Mode Register */
#define REG_TWI1_WPROT_STATUS         (*(RoReg*)0xF00180E8U) /**< \brief (TWI1) Protection Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for USART0 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_USART0_CR                          (0xF001C000U) /**< \brief (USART0) Control Register */
#define REG_USART0_MR                          (0xF001C004U) /**< \brief (USART0) Mode Register */
#define REG_USART0_IER                         (0xF001C008U) /**< \brief (USART0) Interrupt Enable Register */
#define REG_USART0_IDR                         (0xF001C00CU) /**< \brief (USART0) Interrupt Disable Register */
#define REG_USART0_IMR                         (0xF001C010U) /**< \brief (USART0) Interrupt Mask Register */
#define REG_USART0_CSR                         (0xF001C014U) /**< \brief (USART0) Channel Status Register */
#define REG_USART0_RHR                         (0xF001C018U) /**< \brief (USART0) Receiver Holding Register */
#define REG_USART0_THR                         (0xF001C01CU) /**< \brief (USART0) Transmitter Holding Register */
#define REG_USART0_BRGR                        (0xF001C020U) /**< \brief (USART0) Baud Rate Generator Register */
#define REG_USART0_RTOR                        (0xF001C024U) /**< \brief (USART0) Receiver Time-out Register */
#define REG_USART0_TTGR                        (0xF001C028U) /**< \brief (USART0) Transmitter Timeguard Register */
#define REG_USART0_FIDI                        (0xF001C040U) /**< \brief (USART0) FI DI Ratio Register */
#define REG_USART0_NER                         (0xF001C044U) /**< \brief (USART0) Number of Errors Register */
#define REG_USART0_IF                          (0xF001C04CU) /**< \brief (USART0) IrDA Filter Register */
#define REG_USART0_MAN                         (0xF001C050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
#define REG_USART0_WPMR                        (0xF001C0E4U) /**< \brief (USART0) Write Protect Mode Register */
#define REG_USART0_WPSR                        (0xF001C0E8U) /**< \brief (USART0) Write Protect Status Register */
#else
#define REG_USART0_CR                 (*(WoReg*)0xF001C000U) /**< \brief (USART0) Control Register */
#define REG_USART0_MR                 (*(RwReg*)0xF001C004U) /**< \brief (USART0) Mode Register */
#define REG_USART0_IER                (*(WoReg*)0xF001C008U) /**< \brief (USART0) Interrupt Enable Register */
#define REG_USART0_IDR                (*(WoReg*)0xF001C00CU) /**< \brief (USART0) Interrupt Disable Register */
#define REG_USART0_IMR                (*(RoReg*)0xF001C010U) /**< \brief (USART0) Interrupt Mask Register */
#define REG_USART0_CSR                (*(RoReg*)0xF001C014U) /**< \brief (USART0) Channel Status Register */
#define REG_USART0_RHR                (*(RoReg*)0xF001C018U) /**< \brief (USART0) Receiver Holding Register */
#define REG_USART0_THR                (*(WoReg*)0xF001C01CU) /**< \brief (USART0) Transmitter Holding Register */
#define REG_USART0_BRGR               (*(RwReg*)0xF001C020U) /**< \brief (USART0) Baud Rate Generator Register */
#define REG_USART0_RTOR               (*(RwReg*)0xF001C024U) /**< \brief (USART0) Receiver Time-out Register */
#define REG_USART0_TTGR               (*(RwReg*)0xF001C028U) /**< \brief (USART0) Transmitter Timeguard Register */
#define REG_USART0_FIDI               (*(RwReg*)0xF001C040U) /**< \brief (USART0) FI DI Ratio Register */
#define REG_USART0_NER                (*(RoReg*)0xF001C044U) /**< \brief (USART0) Number of Errors Register */
#define REG_USART0_IF                 (*(RwReg*)0xF001C04CU) /**< \brief (USART0) IrDA Filter Register */
#define REG_USART0_MAN                (*(RwReg*)0xF001C050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
#define REG_USART0_WPMR               (*(RwReg*)0xF001C0E4U) /**< \brief (USART0) Write Protect Mode Register */
#define REG_USART0_WPSR               (*(RoReg*)0xF001C0E8U) /**< \brief (USART0) Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for USART1 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_USART1_CR                          (0xF0020000U) /**< \brief (USART1) Control Register */
#define REG_USART1_MR                          (0xF0020004U) /**< \brief (USART1) Mode Register */
#define REG_USART1_IER                         (0xF0020008U) /**< \brief (USART1) Interrupt Enable Register */
#define REG_USART1_IDR                         (0xF002000CU) /**< \brief (USART1) Interrupt Disable Register */
#define REG_USART1_IMR                         (0xF0020010U) /**< \brief (USART1) Interrupt Mask Register */
#define REG_USART1_CSR                         (0xF0020014U) /**< \brief (USART1) Channel Status Register */
#define REG_USART1_RHR                         (0xF0020018U) /**< \brief (USART1) Receiver Holding Register */
#define REG_USART1_THR                         (0xF002001CU) /**< \brief (USART1) Transmitter Holding Register */
#define REG_USART1_BRGR                        (0xF0020020U) /**< \brief (USART1) Baud Rate Generator Register */
#define REG_USART1_RTOR                        (0xF0020024U) /**< \brief (USART1) Receiver Time-out Register */
#define REG_USART1_TTGR                        (0xF0020028U) /**< \brief (USART1) Transmitter Timeguard Register */
#define REG_USART1_FIDI                        (0xF0020040U) /**< \brief (USART1) FI DI Ratio Register */
#define REG_USART1_NER                         (0xF0020044U) /**< \brief (USART1) Number of Errors Register */
#define REG_USART1_IF                          (0xF002004CU) /**< \brief (USART1) IrDA Filter Register */
#define REG_USART1_MAN                         (0xF0020050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
#define REG_USART1_WPMR                        (0xF00200E4U) /**< \brief (USART1) Write Protect Mode Register */
#define REG_USART1_WPSR                        (0xF00200E8U) /**< \brief (USART1) Write Protect Status Register */
#else
#define REG_USART1_CR                 (*(WoReg*)0xF0020000U) /**< \brief (USART1) Control Register */
#define REG_USART1_MR                 (*(RwReg*)0xF0020004U) /**< \brief (USART1) Mode Register */
#define REG_USART1_IER                (*(WoReg*)0xF0020008U) /**< \brief (USART1) Interrupt Enable Register */
#define REG_USART1_IDR                (*(WoReg*)0xF002000CU) /**< \brief (USART1) Interrupt Disable Register */
#define REG_USART1_IMR                (*(RoReg*)0xF0020010U) /**< \brief (USART1) Interrupt Mask Register */
#define REG_USART1_CSR                (*(RoReg*)0xF0020014U) /**< \brief (USART1) Channel Status Register */
#define REG_USART1_RHR                (*(RoReg*)0xF0020018U) /**< \brief (USART1) Receiver Holding Register */
#define REG_USART1_THR                (*(WoReg*)0xF002001CU) /**< \brief (USART1) Transmitter Holding Register */
#define REG_USART1_BRGR               (*(RwReg*)0xF0020020U) /**< \brief (USART1) Baud Rate Generator Register */
#define REG_USART1_RTOR               (*(RwReg*)0xF0020024U) /**< \brief (USART1) Receiver Time-out Register */
#define REG_USART1_TTGR               (*(RwReg*)0xF0020028U) /**< \brief (USART1) Transmitter Timeguard Register */
#define REG_USART1_FIDI               (*(RwReg*)0xF0020040U) /**< \brief (USART1) FI DI Ratio Register */
#define REG_USART1_NER                (*(RoReg*)0xF0020044U) /**< \brief (USART1) Number of Errors Register */
#define REG_USART1_IF                 (*(RwReg*)0xF002004CU) /**< \brief (USART1) IrDA Filter Register */
#define REG_USART1_MAN                (*(RwReg*)0xF0020050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
#define REG_USART1_WPMR               (*(RwReg*)0xF00200E4U) /**< \brief (USART1) Write Protect Mode Register */
#define REG_USART1_WPSR               (*(RoReg*)0xF00200E8U) /**< \brief (USART1) Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for UART0 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_UART0_CR                           (0xF0024000U) /**< \brief (UART0) Control Register */
#define REG_UART0_MR                           (0xF0024004U) /**< \brief (UART0) Mode Register */
#define REG_UART0_IER                          (0xF0024008U) /**< \brief (UART0) Interrupt Enable Register */
#define REG_UART0_IDR                          (0xF002400CU) /**< \brief (UART0) Interrupt Disable Register */
#define REG_UART0_IMR                          (0xF0024010U) /**< \brief (UART0) Interrupt Mask Register */
#define REG_UART0_SR                           (0xF0024014U) /**< \brief (UART0) Status Register */
#define REG_UART0_RHR                          (0xF0024018U) /**< \brief (UART0) Receive Holding Register */
#define REG_UART0_THR                          (0xF002401CU) /**< \brief (UART0) Transmit Holding Register */
#define REG_UART0_BRGR                         (0xF0024020U) /**< \brief (UART0) Baud Rate Generator Register */
#else
#define REG_UART0_CR                  (*(WoReg*)0xF0024000U) /**< \brief (UART0) Control Register */
#define REG_UART0_MR                  (*(RwReg*)0xF0024004U) /**< \brief (UART0) Mode Register */
#define REG_UART0_IER                 (*(WoReg*)0xF0024008U) /**< \brief (UART0) Interrupt Enable Register */
#define REG_UART0_IDR                 (*(WoReg*)0xF002400CU) /**< \brief (UART0) Interrupt Disable Register */
#define REG_UART0_IMR                 (*(RoReg*)0xF0024010U) /**< \brief (UART0) Interrupt Mask Register */
#define REG_UART0_SR                  (*(RoReg*)0xF0024014U) /**< \brief (UART0) Status Register */
#define REG_UART0_RHR                 (*(RoReg*)0xF0024018U) /**< \brief (UART0) Receive Holding Register */
#define REG_UART0_THR                 (*(WoReg*)0xF002401CU) /**< \brief (UART0) Transmit Holding Register */
#define REG_UART0_BRGR                (*(RwReg*)0xF0024020U) /**< \brief (UART0) Baud Rate Generator Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for GMAC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_GMAC_NCR                           (0xF0028000U) /**< \brief (GMAC) Network Control Register */
#define REG_GMAC_NCFGR                         (0xF0028004U) /**< \brief (GMAC) Network Configuration Register */
#define REG_GMAC_NSR                           (0xF0028008U) /**< \brief (GMAC) Network Status Register */
#define REG_GMAC_UR                            (0xF002800CU) /**< \brief (GMAC) User Register */
#define REG_GMAC_DCFGR                         (0xF0028010U) /**< \brief (GMAC) DMA Configuration Register */
#define REG_GMAC_TSR                           (0xF0028014U) /**< \brief (GMAC) Transmit Status Register */
#define REG_GMAC_RBQB                          (0xF0028018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */
#define REG_GMAC_TBQB                          (0xF002801CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */
#define REG_GMAC_RSR                           (0xF0028020U) /**< \brief (GMAC) Receive Status Register */
#define REG_GMAC_ISR                           (0xF0028024U) /**< \brief (GMAC) Interrupt Status Register */
#define REG_GMAC_IER                           (0xF0028028U) /**< \brief (GMAC) Interrupt Enable Register */
#define REG_GMAC_IDR                           (0xF002802CU) /**< \brief (GMAC) Interrupt Disable Register */
#define REG_GMAC_IMR                           (0xF0028030U) /**< \brief (GMAC) Interrupt Mask Register */
#define REG_GMAC_MAN                           (0xF0028034U) /**< \brief (GMAC) PHY Maintenance Register */
#define REG_GMAC_RPQ                           (0xF0028038U) /**< \brief (GMAC) Received Pause Quantum Register */
#define REG_GMAC_TPQ                           (0xF002803CU) /**< \brief (GMAC) Transmit Pause Quantum Register */
#define REG_GMAC_TPSF                          (0xF0028040U) /**< \brief (GMAC) TX Partial Store and Forward Register */
#define REG_GMAC_RPSF                          (0xF0028044U) /**< \brief (GMAC) RX Partial Store and Forward Register */
#define REG_GMAC_HRB                           (0xF0028080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */
#define REG_GMAC_HRT                           (0xF0028084U) /**< \brief (GMAC) Hash Register Top [63:32] */
#define REG_GMAC_SAB1                          (0xF0028088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */
#define REG_GMAC_SAT1                          (0xF002808CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */
#define REG_GMAC_SAB2                          (0xF0028090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */
#define REG_GMAC_SAT2                          (0xF0028094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */
#define REG_GMAC_SAB3                          (0xF0028098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */
#define REG_GMAC_SAT3                          (0xF002809CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */
#define REG_GMAC_SAB4                          (0xF00280A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */
#define REG_GMAC_SAT4                          (0xF00280A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */
#define REG_GMAC_TIDM                          (0xF00280A8U) /**< \brief (GMAC) Type ID Match 1 Register */
#define REG_GMAC_WOL                           (0xF00280B8U) /**< \brief (GMAC) Wake on LAN Register */
#define REG_GMAC_IPGS                          (0xF00280BCU) /**< \brief (GMAC) IPG Stretch Register */
#define REG_GMAC_SVLAN                         (0xF00280C0U) /**< \brief (GMAC) Stacked VLAN Register */
#define REG_GMAC_TPFCP                         (0xF00280C4U) /**< \brief (GMAC) Transmit PFC Pause Register */
#define REG_GMAC_SAMB1                         (0xF00280C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */
#define REG_GMAC_SAMT1                         (0xF00280CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */
#define REG_GMAC_OTLO                          (0xF0028100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */
#define REG_GMAC_OTHI                          (0xF0028104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */
#define REG_GMAC_FT                            (0xF0028108U) /**< \brief (GMAC) Frames Transmitted Register */
#define REG_GMAC_BCFT                          (0xF002810CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
#define REG_GMAC_MFT                           (0xF0028110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */
#define REG_GMAC_PFT                           (0xF0028114U) /**< \brief (GMAC) Pause Frames Transmitted Register */
#define REG_GMAC_BFT64                         (0xF0028118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT127                       (0xF002811CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT255                       (0xF0028120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT511                       (0xF0028124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1023                      (0xF0028128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1518                      (0xF002812CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
#define REG_GMAC_GTBFT1518                     (0xF0028130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
#define REG_GMAC_TUR                           (0xF0028134U) /**< \brief (GMAC) Transmit Under Runs Register */
#define REG_GMAC_SCF                           (0xF0028138U) /**< \brief (GMAC) Single Collision Frames Register */
#define REG_GMAC_MCF                           (0xF002813CU) /**< \brief (GMAC) Multiple Collision Frames Register */
#define REG_GMAC_EC                            (0xF0028140U) /**< \brief (GMAC) Excessive Collisions Register */
#define REG_GMAC_LC                            (0xF0028144U) /**< \brief (GMAC) Late Collisions Register */
#define REG_GMAC_DTF                           (0xF0028148U) /**< \brief (GMAC) Deferred Transmission Frames Register */
#define REG_GMAC_CSE                           (0xF002814CU) /**< \brief (GMAC) Carrier Sense Errors Register */
#define REG_GMAC_ORLO                          (0xF0028150U) /**< \brief (GMAC) Octets Received [31:0] Received */
#define REG_GMAC_ORHI                          (0xF0028154U) /**< \brief (GMAC) Octets Received [47:32] Received */
#define REG_GMAC_FR                            (0xF0028158U) /**< \brief (GMAC) Frames Received Register */
#define REG_GMAC_BCFR                          (0xF002815CU) /**< \brief (GMAC) Broadcast Frames Received Register */
#define REG_GMAC_MFR                           (0xF0028160U) /**< \brief (GMAC) Multicast Frames Received Register */
#define REG_GMAC_PFR                           (0xF0028164U) /**< \brief (GMAC) Pause Frames Received Register */
#define REG_GMAC_BFR64                         (0xF0028168U) /**< \brief (GMAC) 64 Byte Frames Received Register */
#define REG_GMAC_TBFR127                       (0xF002816CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
#define REG_GMAC_TBFR255                       (0xF0028170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
#define REG_GMAC_TBFR511                       (0xF0028174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */
#define REG_GMAC_TBFR1023                      (0xF0028178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
#define REG_GMAC_TBFR1518                      (0xF002817CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
#define REG_GMAC_TMXBFR                        (0xF0028180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
#define REG_GMAC_UFR                           (0xF0028184U) /**< \brief (GMAC) Undersize Frames Received Register */
#define REG_GMAC_OFR                           (0xF0028188U) /**< \brief (GMAC) Oversize Frames Received Register */
#define REG_GMAC_JR                            (0xF002818CU) /**< \brief (GMAC) Jabbers Received Register */
#define REG_GMAC_FCSE                          (0xF0028190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */
#define REG_GMAC_LFFE                          (0xF0028194U) /**< \brief (GMAC) Length Field Frame Errors Register */
#define REG_GMAC_RSE                           (0xF0028198U) /**< \brief (GMAC) Receive Symbol Errors Register */
#define REG_GMAC_AE                            (0xF002819CU) /**< \brief (GMAC) Alignment Errors Register */
#define REG_GMAC_RRE                           (0xF00281A0U) /**< \brief (GMAC) Receive Resource Errors Register */
#define REG_GMAC_ROE                           (0xF00281A4U) /**< \brief (GMAC) Receive Overrun Register */
#define REG_GMAC_IHCE                          (0xF00281A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */
#define REG_GMAC_TCE                           (0xF00281ACU) /**< \brief (GMAC) TCP Checksum Errors Register */
#define REG_GMAC_UCE                           (0xF00281B0U) /**< \brief (GMAC) UDP Checksum Errors Register */
#define REG_GMAC_TSSS                          (0xF00281C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */
#define REG_GMAC_TSSN                          (0xF00281CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */
#define REG_GMAC_TS                            (0xF00281D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */
#define REG_GMAC_TN                            (0xF00281D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
#define REG_GMAC_TA                            (0xF00281D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */
#define REG_GMAC_TI                            (0xF00281DCU) /**< \brief (GMAC) 1588 Timer Increment Register */
#define REG_GMAC_EFTS                          (0xF00281E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */
#define REG_GMAC_EFTN                          (0xF00281E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */
#define REG_GMAC_EFRS                          (0xF00281E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */
#define REG_GMAC_EFRN                          (0xF00281ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */
#define REG_GMAC_PEFTS                         (0xF00281F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */
#define REG_GMAC_PEFTN                         (0xF00281F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */
#define REG_GMAC_PEFRS                         (0xF00281F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */
#define REG_GMAC_PEFRN                         (0xF00281FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */
#define REG_GMAC_ISRPQ                         (0xF0028400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue */
#define REG_GMAC_TBQBAPQ                       (0xF0028440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Priority Queue */
#define REG_GMAC_RBQBAPQ                       (0xF0028480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Priority Queue */
#define REG_GMAC_RBSRPQ                        (0xF00284A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue */
#define REG_GMAC_ST1RPQ                        (0xF0028500U) /**< \brief (GMAC) Screening Type1 Register Priority Queue */
#define REG_GMAC_ST2RPQ                        (0xF0028540U) /**< \brief (GMAC) Screening Type2 Register Priority Queue */
#define REG_GMAC_IERPQ                         (0xF0028600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue */
#define REG_GMAC_IDRPQ                         (0xF0028620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue */
#define REG_GMAC_IMRPQ                         (0xF0028640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue */
#else
#define REG_GMAC_NCR                  (*(RwReg*)0xF0028000U) /**< \brief (GMAC) Network Control Register */
#define REG_GMAC_NCFGR                (*(RwReg*)0xF0028004U) /**< \brief (GMAC) Network Configuration Register */
#define REG_GMAC_NSR                  (*(RoReg*)0xF0028008U) /**< \brief (GMAC) Network Status Register */
#define REG_GMAC_UR                   (*(RwReg*)0xF002800CU) /**< \brief (GMAC) User Register */
#define REG_GMAC_DCFGR                (*(RwReg*)0xF0028010U) /**< \brief (GMAC) DMA Configuration Register */
#define REG_GMAC_TSR                  (*(RwReg*)0xF0028014U) /**< \brief (GMAC) Transmit Status Register */
#define REG_GMAC_RBQB                 (*(RwReg*)0xF0028018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */
#define REG_GMAC_TBQB                 (*(RwReg*)0xF002801CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */
#define REG_GMAC_RSR                  (*(RwReg*)0xF0028020U) /**< \brief (GMAC) Receive Status Register */
#define REG_GMAC_ISR                  (*(RoReg*)0xF0028024U) /**< \brief (GMAC) Interrupt Status Register */
#define REG_GMAC_IER                  (*(WoReg*)0xF0028028U) /**< \brief (GMAC) Interrupt Enable Register */
#define REG_GMAC_IDR                  (*(WoReg*)0xF002802CU) /**< \brief (GMAC) Interrupt Disable Register */
#define REG_GMAC_IMR                  (*(RoReg*)0xF0028030U) /**< \brief (GMAC) Interrupt Mask Register */
#define REG_GMAC_MAN                  (*(RwReg*)0xF0028034U) /**< \brief (GMAC) PHY Maintenance Register */
#define REG_GMAC_RPQ                  (*(RoReg*)0xF0028038U) /**< \brief (GMAC) Received Pause Quantum Register */
#define REG_GMAC_TPQ                  (*(RwReg*)0xF002803CU) /**< \brief (GMAC) Transmit Pause Quantum Register */
#define REG_GMAC_TPSF                 (*(RwReg*)0xF0028040U) /**< \brief (GMAC) TX Partial Store and Forward Register */
#define REG_GMAC_RPSF                 (*(RwReg*)0xF0028044U) /**< \brief (GMAC) RX Partial Store and Forward Register */
#define REG_GMAC_HRB                  (*(RwReg*)0xF0028080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */
#define REG_GMAC_HRT                  (*(RwReg*)0xF0028084U) /**< \brief (GMAC) Hash Register Top [63:32] */
#define REG_GMAC_SAB1                 (*(RwReg*)0xF0028088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */
#define REG_GMAC_SAT1                 (*(RwReg*)0xF002808CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */
#define REG_GMAC_SAB2                 (*(RwReg*)0xF0028090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */
#define REG_GMAC_SAT2                 (*(RwReg*)0xF0028094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */
#define REG_GMAC_SAB3                 (*(RwReg*)0xF0028098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */
#define REG_GMAC_SAT3                 (*(RwReg*)0xF002809CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */
#define REG_GMAC_SAB4                 (*(RwReg*)0xF00280A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */
#define REG_GMAC_SAT4                 (*(RwReg*)0xF00280A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */
#define REG_GMAC_TIDM                 (*(RwReg*)0xF00280A8U) /**< \brief (GMAC) Type ID Match 1 Register */
#define REG_GMAC_WOL                  (*(RwReg*)0xF00280B8U) /**< \brief (GMAC) Wake on LAN Register */
#define REG_GMAC_IPGS                 (*(RwReg*)0xF00280BCU) /**< \brief (GMAC) IPG Stretch Register */
#define REG_GMAC_SVLAN                (*(RwReg*)0xF00280C0U) /**< \brief (GMAC) Stacked VLAN Register */
#define REG_GMAC_TPFCP                (*(RwReg*)0xF00280C4U) /**< \brief (GMAC) Transmit PFC Pause Register */
#define REG_GMAC_SAMB1                (*(RwReg*)0xF00280C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */
#define REG_GMAC_SAMT1                (*(RwReg*)0xF00280CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */
#define REG_GMAC_OTLO                 (*(RoReg*)0xF0028100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */
#define REG_GMAC_OTHI                 (*(RoReg*)0xF0028104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */
#define REG_GMAC_FT                   (*(RoReg*)0xF0028108U) /**< \brief (GMAC) Frames Transmitted Register */
#define REG_GMAC_BCFT                 (*(RoReg*)0xF002810CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
#define REG_GMAC_MFT                  (*(RoReg*)0xF0028110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */
#define REG_GMAC_PFT                  (*(RoReg*)0xF0028114U) /**< \brief (GMAC) Pause Frames Transmitted Register */
#define REG_GMAC_BFT64                (*(RoReg*)0xF0028118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT127              (*(RoReg*)0xF002811CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT255              (*(RoReg*)0xF0028120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT511              (*(RoReg*)0xF0028124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1023             (*(RoReg*)0xF0028128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1518             (*(RoReg*)0xF002812CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
#define REG_GMAC_GTBFT1518            (*(RoReg*)0xF0028130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
#define REG_GMAC_TUR                  (*(RoReg*)0xF0028134U) /**< \brief (GMAC) Transmit Under Runs Register */
#define REG_GMAC_SCF                  (*(RoReg*)0xF0028138U) /**< \brief (GMAC) Single Collision Frames Register */
#define REG_GMAC_MCF                  (*(RoReg*)0xF002813CU) /**< \brief (GMAC) Multiple Collision Frames Register */
#define REG_GMAC_EC                   (*(RoReg*)0xF0028140U) /**< \brief (GMAC) Excessive Collisions Register */
#define REG_GMAC_LC                   (*(RoReg*)0xF0028144U) /**< \brief (GMAC) Late Collisions Register */
#define REG_GMAC_DTF                  (*(RoReg*)0xF0028148U) /**< \brief (GMAC) Deferred Transmission Frames Register */
#define REG_GMAC_CSE                  (*(RoReg*)0xF002814CU) /**< \brief (GMAC) Carrier Sense Errors Register */
#define REG_GMAC_ORLO                 (*(RoReg*)0xF0028150U) /**< \brief (GMAC) Octets Received [31:0] Received */
#define REG_GMAC_ORHI                 (*(RoReg*)0xF0028154U) /**< \brief (GMAC) Octets Received [47:32] Received */
#define REG_GMAC_FR                   (*(RoReg*)0xF0028158U) /**< \brief (GMAC) Frames Received Register */
#define REG_GMAC_BCFR                 (*(RoReg*)0xF002815CU) /**< \brief (GMAC) Broadcast Frames Received Register */
#define REG_GMAC_MFR                  (*(RoReg*)0xF0028160U) /**< \brief (GMAC) Multicast Frames Received Register */
#define REG_GMAC_PFR                  (*(RoReg*)0xF0028164U) /**< \brief (GMAC) Pause Frames Received Register */
#define REG_GMAC_BFR64                (*(RoReg*)0xF0028168U) /**< \brief (GMAC) 64 Byte Frames Received Register */
#define REG_GMAC_TBFR127              (*(RoReg*)0xF002816CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
#define REG_GMAC_TBFR255              (*(RoReg*)0xF0028170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
#define REG_GMAC_TBFR511              (*(RoReg*)0xF0028174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */
#define REG_GMAC_TBFR1023             (*(RoReg*)0xF0028178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
#define REG_GMAC_TBFR1518             (*(RoReg*)0xF002817CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
#define REG_GMAC_TMXBFR               (*(RoReg*)0xF0028180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
#define REG_GMAC_UFR                  (*(RoReg*)0xF0028184U) /**< \brief (GMAC) Undersize Frames Received Register */
#define REG_GMAC_OFR                  (*(RoReg*)0xF0028188U) /**< \brief (GMAC) Oversize Frames Received Register */
#define REG_GMAC_JR                   (*(RoReg*)0xF002818CU) /**< \brief (GMAC) Jabbers Received Register */
#define REG_GMAC_FCSE                 (*(RoReg*)0xF0028190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */
#define REG_GMAC_LFFE                 (*(RoReg*)0xF0028194U) /**< \brief (GMAC) Length Field Frame Errors Register */
#define REG_GMAC_RSE                  (*(RoReg*)0xF0028198U) /**< \brief (GMAC) Receive Symbol Errors Register */
#define REG_GMAC_AE                   (*(RoReg*)0xF002819CU) /**< \brief (GMAC) Alignment Errors Register */
#define REG_GMAC_RRE                  (*(RoReg*)0xF00281A0U) /**< \brief (GMAC) Receive Resource Errors Register */
#define REG_GMAC_ROE                  (*(RoReg*)0xF00281A4U) /**< \brief (GMAC) Receive Overrun Register */
#define REG_GMAC_IHCE                 (*(RoReg*)0xF00281A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */
#define REG_GMAC_TCE                  (*(RoReg*)0xF00281ACU) /**< \brief (GMAC) TCP Checksum Errors Register */
#define REG_GMAC_UCE                  (*(RoReg*)0xF00281B0U) /**< \brief (GMAC) UDP Checksum Errors Register */
#define REG_GMAC_TSSS                 (*(RwReg*)0xF00281C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */
#define REG_GMAC_TSSN                 (*(RwReg*)0xF00281CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */
#define REG_GMAC_TS                   (*(RwReg*)0xF00281D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */
#define REG_GMAC_TN                   (*(RwReg*)0xF00281D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
#define REG_GMAC_TA                   (*(WoReg*)0xF00281D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */
#define REG_GMAC_TI                   (*(RwReg*)0xF00281DCU) /**< \brief (GMAC) 1588 Timer Increment Register */
#define REG_GMAC_EFTS                 (*(RoReg*)0xF00281E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */
#define REG_GMAC_EFTN                 (*(RoReg*)0xF00281E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */
#define REG_GMAC_EFRS                 (*(RoReg*)0xF00281E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */
#define REG_GMAC_EFRN                 (*(RoReg*)0xF00281ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */
#define REG_GMAC_PEFTS                (*(RoReg*)0xF00281F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */
#define REG_GMAC_PEFTN                (*(RoReg*)0xF00281F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */
#define REG_GMAC_PEFRS                (*(RoReg*)0xF00281F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */
#define REG_GMAC_PEFRN                (*(RoReg*)0xF00281FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */
#define REG_GMAC_ISRPQ                (*(RoReg*)0xF0028400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue */
#define REG_GMAC_TBQBAPQ              (*(RwReg*)0xF0028440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Priority Queue */
#define REG_GMAC_RBQBAPQ              (*(RwReg*)0xF0028480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Priority Queue */
#define REG_GMAC_RBSRPQ               (*(RwReg*)0xF00284A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue */
#define REG_GMAC_ST1RPQ               (*(RwReg*)0xF0028500U) /**< \brief (GMAC) Screening Type1 Register Priority Queue */
#define REG_GMAC_ST2RPQ               (*(RwReg*)0xF0028540U) /**< \brief (GMAC) Screening Type2 Register Priority Queue */
#define REG_GMAC_IERPQ                (*(WoReg*)0xF0028600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue */
#define REG_GMAC_IDRPQ                (*(WoReg*)0xF0028620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue */
#define REG_GMAC_IMRPQ                (*(RwReg*)0xF0028640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for PWM peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_PWM_CLK                            (0xF002C000U) /**< \brief (PWM) PWM Clock Register */
#define REG_PWM_ENA                            (0xF002C004U) /**< \brief (PWM) PWM Enable Register */
#define REG_PWM_DIS                            (0xF002C008U) /**< \brief (PWM) PWM Disable Register */
#define REG_PWM_SR                             (0xF002C00CU) /**< \brief (PWM) PWM Status Register */
#define REG_PWM_IER1                           (0xF002C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
#define REG_PWM_IDR1                           (0xF002C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
#define REG_PWM_IMR1                           (0xF002C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
#define REG_PWM_ISR1                           (0xF002C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
#define REG_PWM_SCM                            (0xF002C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
#define REG_PWM_SCUC                           (0xF002C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
#define REG_PWM_SCUP                           (0xF002C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
#define REG_PWM_SCUPUPD                        (0xF002C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
#define REG_PWM_IER2                           (0xF002C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
#define REG_PWM_IDR2                           (0xF002C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
#define REG_PWM_IMR2                           (0xF002C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
#define REG_PWM_ISR2                           (0xF002C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
#define REG_PWM_OOV                            (0xF002C044U) /**< \brief (PWM) PWM Output Override Value Register */
#define REG_PWM_OS                             (0xF002C048U) /**< \brief (PWM) PWM Output Selection Register */
#define REG_PWM_OSS                            (0xF002C04CU) /**< \brief (PWM) PWM Output Selection Set Register */
#define REG_PWM_OSC                            (0xF002C050U) /**< \brief (PWM) PWM Output Selection Clear Register */
#define REG_PWM_OSSUPD                         (0xF002C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
#define REG_PWM_OSCUPD                         (0xF002C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
#define REG_PWM_FMR                            (0xF002C05CU) /**< \brief (PWM) PWM Fault Mode Register */
#define REG_PWM_FSR                            (0xF002C060U) /**< \brief (PWM) PWM Fault Status Register */
#define REG_PWM_FCR                            (0xF002C064U) /**< \brief (PWM) PWM Fault Clear Register */
#define REG_PWM_FPV                            (0xF002C068U) /**< \brief (PWM) PWM Fault Protection Value Register */
#define REG_PWM_FPE                            (0xF002C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
#define REG_PWM_ELMR                           (0xF002C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
#define REG_PWM_SMMR                           (0xF002C0B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
#define REG_PWM_WPCR                           (0xF002C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */
#define REG_PWM_WPSR                           (0xF002C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */
#define REG_PWM_CMPV0                          (0xF002C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
#define REG_PWM_CMPVUPD0                       (0xF002C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
#define REG_PWM_CMPM0                          (0xF002C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
#define REG_PWM_CMPMUPD0                       (0xF002C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
#define REG_PWM_CMPV1                          (0xF002C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
#define REG_PWM_CMPVUPD1                       (0xF002C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
#define REG_PWM_CMPM1                          (0xF002C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
#define REG_PWM_CMPMUPD1                       (0xF002C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
#define REG_PWM_CMPV2                          (0xF002C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
#define REG_PWM_CMPVUPD2                       (0xF002C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
#define REG_PWM_CMPM2                          (0xF002C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
#define REG_PWM_CMPMUPD2                       (0xF002C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
#define REG_PWM_CMPV3                          (0xF002C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
#define REG_PWM_CMPVUPD3                       (0xF002C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
#define REG_PWM_CMPM3                          (0xF002C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
#define REG_PWM_CMPMUPD3                       (0xF002C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
#define REG_PWM_CMPV4                          (0xF002C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
#define REG_PWM_CMPVUPD4                       (0xF002C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
#define REG_PWM_CMPM4                          (0xF002C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
#define REG_PWM_CMPMUPD4                       (0xF002C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
#define REG_PWM_CMPV5                          (0xF002C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
#define REG_PWM_CMPVUPD5                       (0xF002C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
#define REG_PWM_CMPM5                          (0xF002C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
#define REG_PWM_CMPMUPD5                       (0xF002C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
#define REG_PWM_CMPV6                          (0xF002C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
#define REG_PWM_CMPVUPD6                       (0xF002C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
#define REG_PWM_CMPM6                          (0xF002C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
#define REG_PWM_CMPMUPD6                       (0xF002C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
#define REG_PWM_CMPV7                          (0xF002C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
#define REG_PWM_CMPVUPD7                       (0xF002C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
#define REG_PWM_CMPM7                          (0xF002C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
#define REG_PWM_CMPMUPD7                       (0xF002C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
#define REG_PWM_CMR0                           (0xF002C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
#define REG_PWM_CDTY0                          (0xF002C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
#define REG_PWM_CDTYUPD0                       (0xF002C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
#define REG_PWM_CPRD0                          (0xF002C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
#define REG_PWM_CPRDUPD0                       (0xF002C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
#define REG_PWM_CCNT0                          (0xF002C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
#define REG_PWM_DT0                            (0xF002C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
#define REG_PWM_DTUPD0                         (0xF002C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
#define REG_PWM_CMR1                           (0xF002C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
#define REG_PWM_CDTY1                          (0xF002C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
#define REG_PWM_CDTYUPD1                       (0xF002C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
#define REG_PWM_CPRD1                          (0xF002C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
#define REG_PWM_CPRDUPD1                       (0xF002C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
#define REG_PWM_CCNT1                          (0xF002C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
#define REG_PWM_DT1                            (0xF002C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
#define REG_PWM_DTUPD1                         (0xF002C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
#define REG_PWM_CMR2                           (0xF002C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
#define REG_PWM_CDTY2                          (0xF002C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
#define REG_PWM_CDTYUPD2                       (0xF002C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
#define REG_PWM_CPRD2                          (0xF002C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
#define REG_PWM_CPRDUPD2                       (0xF002C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
#define REG_PWM_CCNT2                          (0xF002C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
#define REG_PWM_DT2                            (0xF002C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
#define REG_PWM_DTUPD2                         (0xF002C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
#define REG_PWM_CMR3                           (0xF002C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
#define REG_PWM_CDTY3                          (0xF002C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
#define REG_PWM_CDTYUPD3                       (0xF002C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
#define REG_PWM_CPRD3                          (0xF002C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
#define REG_PWM_CPRDUPD3                       (0xF002C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
#define REG_PWM_CCNT3                          (0xF002C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
#define REG_PWM_DT3                            (0xF002C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
#define REG_PWM_DTUPD3                         (0xF002C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
#else
#define REG_PWM_CLK                   (*(RwReg*)0xF002C000U) /**< \brief (PWM) PWM Clock Register */
#define REG_PWM_ENA                   (*(WoReg*)0xF002C004U) /**< \brief (PWM) PWM Enable Register */
#define REG_PWM_DIS                   (*(WoReg*)0xF002C008U) /**< \brief (PWM) PWM Disable Register */
#define REG_PWM_SR                    (*(RoReg*)0xF002C00CU) /**< \brief (PWM) PWM Status Register */
#define REG_PWM_IER1                  (*(WoReg*)0xF002C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
#define REG_PWM_IDR1                  (*(WoReg*)0xF002C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
#define REG_PWM_IMR1                  (*(RoReg*)0xF002C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
#define REG_PWM_ISR1                  (*(RoReg*)0xF002C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
#define REG_PWM_SCM                   (*(RwReg*)0xF002C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
#define REG_PWM_SCUC                  (*(RwReg*)0xF002C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
#define REG_PWM_SCUP                  (*(RwReg*)0xF002C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
#define REG_PWM_SCUPUPD               (*(WoReg*)0xF002C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
#define REG_PWM_IER2                  (*(WoReg*)0xF002C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
#define REG_PWM_IDR2                  (*(WoReg*)0xF002C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
#define REG_PWM_IMR2                  (*(RoReg*)0xF002C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
#define REG_PWM_ISR2                  (*(RoReg*)0xF002C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
#define REG_PWM_OOV                   (*(RwReg*)0xF002C044U) /**< \brief (PWM) PWM Output Override Value Register */
#define REG_PWM_OS                    (*(RwReg*)0xF002C048U) /**< \brief (PWM) PWM Output Selection Register */
#define REG_PWM_OSS                   (*(WoReg*)0xF002C04CU) /**< \brief (PWM) PWM Output Selection Set Register */
#define REG_PWM_OSC                   (*(WoReg*)0xF002C050U) /**< \brief (PWM) PWM Output Selection Clear Register */
#define REG_PWM_OSSUPD                (*(WoReg*)0xF002C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
#define REG_PWM_OSCUPD                (*(WoReg*)0xF002C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
#define REG_PWM_FMR                   (*(RwReg*)0xF002C05CU) /**< \brief (PWM) PWM Fault Mode Register */
#define REG_PWM_FSR                   (*(RoReg*)0xF002C060U) /**< \brief (PWM) PWM Fault Status Register */
#define REG_PWM_FCR                   (*(WoReg*)0xF002C064U) /**< \brief (PWM) PWM Fault Clear Register */
#define REG_PWM_FPV                   (*(RwReg*)0xF002C068U) /**< \brief (PWM) PWM Fault Protection Value Register */
#define REG_PWM_FPE                   (*(RwReg*)0xF002C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
#define REG_PWM_ELMR                  (*(RwReg*)0xF002C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
#define REG_PWM_SMMR                  (*(RwReg*)0xF002C0B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
#define REG_PWM_WPCR                  (*(WoReg*)0xF002C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */
#define REG_PWM_WPSR                  (*(RoReg*)0xF002C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */
#define REG_PWM_CMPV0                 (*(RwReg*)0xF002C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
#define REG_PWM_CMPVUPD0              (*(WoReg*)0xF002C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
#define REG_PWM_CMPM0                 (*(RwReg*)0xF002C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
#define REG_PWM_CMPMUPD0              (*(WoReg*)0xF002C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
#define REG_PWM_CMPV1                 (*(RwReg*)0xF002C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
#define REG_PWM_CMPVUPD1              (*(WoReg*)0xF002C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
#define REG_PWM_CMPM1                 (*(RwReg*)0xF002C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
#define REG_PWM_CMPMUPD1              (*(WoReg*)0xF002C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
#define REG_PWM_CMPV2                 (*(RwReg*)0xF002C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
#define REG_PWM_CMPVUPD2              (*(WoReg*)0xF002C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
#define REG_PWM_CMPM2                 (*(RwReg*)0xF002C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
#define REG_PWM_CMPMUPD2              (*(WoReg*)0xF002C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
#define REG_PWM_CMPV3                 (*(RwReg*)0xF002C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
#define REG_PWM_CMPVUPD3              (*(WoReg*)0xF002C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
#define REG_PWM_CMPM3                 (*(RwReg*)0xF002C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
#define REG_PWM_CMPMUPD3              (*(WoReg*)0xF002C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
#define REG_PWM_CMPV4                 (*(RwReg*)0xF002C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
#define REG_PWM_CMPVUPD4              (*(WoReg*)0xF002C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
#define REG_PWM_CMPM4                 (*(RwReg*)0xF002C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
#define REG_PWM_CMPMUPD4              (*(WoReg*)0xF002C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
#define REG_PWM_CMPV5                 (*(RwReg*)0xF002C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
#define REG_PWM_CMPVUPD5              (*(WoReg*)0xF002C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
#define REG_PWM_CMPM5                 (*(RwReg*)0xF002C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
#define REG_PWM_CMPMUPD5              (*(WoReg*)0xF002C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
#define REG_PWM_CMPV6                 (*(RwReg*)0xF002C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
#define REG_PWM_CMPVUPD6              (*(WoReg*)0xF002C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
#define REG_PWM_CMPM6                 (*(RwReg*)0xF002C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
#define REG_PWM_CMPMUPD6              (*(WoReg*)0xF002C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
#define REG_PWM_CMPV7                 (*(RwReg*)0xF002C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
#define REG_PWM_CMPVUPD7              (*(WoReg*)0xF002C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
#define REG_PWM_CMPM7                 (*(RwReg*)0xF002C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
#define REG_PWM_CMPMUPD7              (*(WoReg*)0xF002C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
#define REG_PWM_CMR0                  (*(RwReg*)0xF002C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
#define REG_PWM_CDTY0                 (*(RwReg*)0xF002C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
#define REG_PWM_CDTYUPD0              (*(WoReg*)0xF002C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
#define REG_PWM_CPRD0                 (*(RwReg*)0xF002C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
#define REG_PWM_CPRDUPD0              (*(WoReg*)0xF002C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
#define REG_PWM_CCNT0                 (*(RoReg*)0xF002C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
#define REG_PWM_DT0                   (*(RwReg*)0xF002C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
#define REG_PWM_DTUPD0                (*(WoReg*)0xF002C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
#define REG_PWM_CMR1                  (*(RwReg*)0xF002C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
#define REG_PWM_CDTY1                 (*(RwReg*)0xF002C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
#define REG_PWM_CDTYUPD1              (*(WoReg*)0xF002C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
#define REG_PWM_CPRD1                 (*(RwReg*)0xF002C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
#define REG_PWM_CPRDUPD1              (*(WoReg*)0xF002C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
#define REG_PWM_CCNT1                 (*(RoReg*)0xF002C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
#define REG_PWM_DT1                   (*(RwReg*)0xF002C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
#define REG_PWM_DTUPD1                (*(WoReg*)0xF002C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
#define REG_PWM_CMR2                  (*(RwReg*)0xF002C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
#define REG_PWM_CDTY2                 (*(RwReg*)0xF002C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
#define REG_PWM_CDTYUPD2              (*(WoReg*)0xF002C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
#define REG_PWM_CPRD2                 (*(RwReg*)0xF002C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
#define REG_PWM_CPRDUPD2              (*(WoReg*)0xF002C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
#define REG_PWM_CCNT2                 (*(RoReg*)0xF002C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
#define REG_PWM_DT2                   (*(RwReg*)0xF002C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
#define REG_PWM_DTUPD2                (*(WoReg*)0xF002C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
#define REG_PWM_CMR3                  (*(RwReg*)0xF002C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
#define REG_PWM_CDTY3                 (*(RwReg*)0xF002C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
#define REG_PWM_CDTYUPD3              (*(WoReg*)0xF002C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
#define REG_PWM_CPRD3                 (*(RwReg*)0xF002C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
#define REG_PWM_CPRDUPD3              (*(WoReg*)0xF002C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
#define REG_PWM_CCNT3                 (*(RoReg*)0xF002C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
#define REG_PWM_DT3                   (*(RwReg*)0xF002C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
#define REG_PWM_DTUPD3                (*(WoReg*)0xF002C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for LCDC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_LCDC_LCDCFG0                       (0xF0030000U) /**< \brief (LCDC) LCD Controller Configuration Register 0 */
#define REG_LCDC_LCDCFG1                       (0xF0030004U) /**< \brief (LCDC) LCD Controller Configuration Register 1 */
#define REG_LCDC_LCDCFG2                       (0xF0030008U) /**< \brief (LCDC) LCD Controller Configuration Register 2 */
#define REG_LCDC_LCDCFG3                       (0xF003000CU) /**< \brief (LCDC) LCD Controller Configuration Register 3 */
#define REG_LCDC_LCDCFG4                       (0xF0030010U) /**< \brief (LCDC) LCD Controller Configuration Register 4 */
#define REG_LCDC_LCDCFG5                       (0xF0030014U) /**< \brief (LCDC) LCD Controller Configuration Register 5 */
#define REG_LCDC_LCDCFG6                       (0xF0030018U) /**< \brief (LCDC) LCD Controller Configuration Register 6 */
#define REG_LCDC_LCDEN                         (0xF0030020U) /**< \brief (LCDC) LCD Controller Enable Register */
#define REG_LCDC_LCDDIS                        (0xF0030024U) /**< \brief (LCDC) LCD Controller Disable Register */
#define REG_LCDC_LCDSR                         (0xF0030028U) /**< \brief (LCDC) LCD Controller Status Register */
#define REG_LCDC_LCDIER                        (0xF003002CU) /**< \brief (LCDC) LCD Controller Interrupt Enable Register */
#define REG_LCDC_LCDIDR                        (0xF0030030U) /**< \brief (LCDC) LCD Controller Interrupt Disable Register */
#define REG_LCDC_LCDIMR                        (0xF0030034U) /**< \brief (LCDC) LCD Controller Interrupt Mask Register */
#define REG_LCDC_LCDISR                        (0xF0030038U) /**< \brief (LCDC) LCD Controller Interrupt Status Register */
#define REG_LCDC_BASECHER                      (0xF0030040U) /**< \brief (LCDC) Base Layer Channel Enable Register */
#define REG_LCDC_BASECHDR                      (0xF0030044U) /**< \brief (LCDC) Base Layer Channel Disable Register */
#define REG_LCDC_BASECHSR                      (0xF0030048U) /**< \brief (LCDC) Base Layer Channel Status Register */
#define REG_LCDC_BASEIER                       (0xF003004CU) /**< \brief (LCDC) Base Layer Interrupt Enable Register */
#define REG_LCDC_BASEIDR                       (0xF0030050U) /**< \brief (LCDC) Base Layer Interrupt Disabled Register */
#define REG_LCDC_BASEIMR                       (0xF0030054U) /**< \brief (LCDC) Base Layer Interrupt Mask Register */
#define REG_LCDC_BASEISR                       (0xF0030058U) /**< \brief (LCDC) Base Layer Interrupt status Register */
#define REG_LCDC_BASEHEAD                      (0xF003005CU) /**< \brief (LCDC) Base DMA Head Register */
#define REG_LCDC_BASEADDR                      (0xF0030060U) /**< \brief (LCDC) Base DMA Address Register */
#define REG_LCDC_BASECTRL                      (0xF0030064U) /**< \brief (LCDC) Base DMA Control Register */
#define REG_LCDC_BASENEXT                      (0xF0030068U) /**< \brief (LCDC) Base DMA Next Register */
#define REG_LCDC_BASECFG0                      (0xF003006CU) /**< \brief (LCDC) Base Configuration register 0 */
#define REG_LCDC_BASECFG1                      (0xF0030070U) /**< \brief (LCDC) Base Configuration register 1 */
#define REG_LCDC_BASECFG2                      (0xF0030074U) /**< \brief (LCDC) Base Configuration register 2 */
#define REG_LCDC_BASECFG3                      (0xF0030078U) /**< \brief (LCDC) Base Configuration register 3 */
#define REG_LCDC_BASECFG4                      (0xF003007CU) /**< \brief (LCDC) Base Configuration register 4 */
#define REG_LCDC_BASECFG5                      (0xF0030080U) /**< \brief (LCDC) Base Configuration register 5 */
#define REG_LCDC_BASECFG6                      (0xF0030084U) /**< \brief (LCDC) Base Configuration register 6 */
#define REG_LCDC_OVR1CHER                      (0xF0030140U) /**< \brief (LCDC) Overlay 1 Channel Enable Register */
#define REG_LCDC_OVR1CHDR                      (0xF0030144U) /**< \brief (LCDC) Overlay 1 Channel Disable Register */
#define REG_LCDC_OVR1CHSR                      (0xF0030148U) /**< \brief (LCDC) Overlay 1 Channel Status Register */
#define REG_LCDC_OVR1IER                       (0xF003014CU) /**< \brief (LCDC) Overlay 1 Interrupt Enable Register */
#define REG_LCDC_OVR1IDR                       (0xF0030150U) /**< \brief (LCDC) Overlay 1 Interrupt Disable Register */
#define REG_LCDC_OVR1IMR                       (0xF0030154U) /**< \brief (LCDC) Overlay 1 Interrupt Mask Register */
#define REG_LCDC_OVR1ISR                       (0xF0030158U) /**< \brief (LCDC) Overlay 1 Interrupt Status Register */
#define REG_LCDC_OVR1HEAD                      (0xF003015CU) /**< \brief (LCDC) Overlay 1 DMA Head Register */
#define REG_LCDC_OVR1ADDR                      (0xF0030160U) /**< \brief (LCDC) Overlay 1 DMA Address Register */
#define REG_LCDC_OVR1CTRL                      (0xF0030164U) /**< \brief (LCDC) Overlay1 DMA Control Register */
#define REG_LCDC_OVR1NEXT                      (0xF0030168U) /**< \brief (LCDC) Overlay1 DMA Next Register */
#define REG_LCDC_OVR1CFG0                      (0xF003016CU) /**< \brief (LCDC) Overlay 1 Configuration 0 Register */
#define REG_LCDC_OVR1CFG1                      (0xF0030170U) /**< \brief (LCDC) Overlay 1 Configuration 1 Register */
#define REG_LCDC_OVR1CFG2                      (0xF0030174U) /**< \brief (LCDC) Overlay 1 Configuration 2 Register */
#define REG_LCDC_OVR1CFG3                      (0xF0030178U) /**< \brief (LCDC) Overlay 1 Configuration 3 Register */
#define REG_LCDC_OVR1CFG4                      (0xF003017CU) /**< \brief (LCDC) Overlay 1 Configuration 4 Register */
#define REG_LCDC_OVR1CFG5                      (0xF0030180U) /**< \brief (LCDC) Overlay 1 Configuration 5 Register */
#define REG_LCDC_OVR1CFG6                      (0xF0030184U) /**< \brief (LCDC) Overlay 1 Configuration 6 Register */
#define REG_LCDC_OVR1CFG7                      (0xF0030188U) /**< \brief (LCDC) Overlay 1 Configuration 7 Register */
#define REG_LCDC_OVR1CFG8                      (0xF003018CU) /**< \brief (LCDC) Overlay 1 Configuration 8Register */
#define REG_LCDC_OVR1CFG9                      (0xF0030190U) /**< \brief (LCDC) Overlay 1 Configuration 9 Register */
#define REG_LCDC_OVR2CHER                      (0xF0030240U) /**< \brief (LCDC) Overlay 2 Channel Enable Register */
#define REG_LCDC_OVR2CHDR                      (0xF0030244U) /**< \brief (LCDC) Overlay 2 Channel Disable Register */
#define REG_LCDC_OVR2CHSR                      (0xF0030248U) /**< \brief (LCDC) Overlay 2 Channel Status Register */
#define REG_LCDC_OVR2IER                       (0xF003024CU) /**< \brief (LCDC) Overlay 2 Interrupt Enable Register */
#define REG_LCDC_OVR2IDR                       (0xF0030250U) /**< \brief (LCDC) Overlay 2 Interrupt Disable Register */
#define REG_LCDC_OVR2IMR                       (0xF0030254U) /**< \brief (LCDC) Overlay 2 Interrupt Mask Register */
#define REG_LCDC_OVR2ISR                       (0xF0030258U) /**< \brief (LCDC) Overlay 2 Interrupt status Register */
#define REG_LCDC_OVR2HEAD                      (0xF003025CU) /**< \brief (LCDC) Overlay 2 DMA Head Register */
#define REG_LCDC_OVR2ADDR                      (0xF0030260U) /**< \brief (LCDC) Overlay 2 DMA Address Register */
#define REG_LCDC_OVR2CTRL                      (0xF0030264U) /**< \brief (LCDC) Overlay 2 DMA Control Register */
#define REG_LCDC_OVR2NEXT                      (0xF0030268U) /**< \brief (LCDC) Overlay 2 DMA Next Register */
#define REG_LCDC_OVR2CFG0                      (0xF003026CU) /**< \brief (LCDC) Overlay 2 Configuration 0 Register */
#define REG_LCDC_OVR2CFG1                      (0xF0030270U) /**< \brief (LCDC) Overlay 2 Configuration 1 Register */
#define REG_LCDC_OVR2CFG2                      (0xF0030274U) /**< \brief (LCDC) Overlay 2 Configuration 2 Register */
#define REG_LCDC_OVR2CFG3                      (0xF0030278U) /**< \brief (LCDC) Overlay 2 Configuration 3 Register */
#define REG_LCDC_OVR2CFG4                      (0xF003027CU) /**< \brief (LCDC) Overlay 2 Configuration 4 Register */
#define REG_LCDC_OVR2CFG5                      (0xF0030280U) /**< \brief (LCDC) Overlay 2 Configuration 5 Register */
#define REG_LCDC_OVR2CFG6                      (0xF0030284U) /**< \brief (LCDC) Overlay 2 Configuration 6 Register */
#define REG_LCDC_OVR2CFG7                      (0xF0030288U) /**< \brief (LCDC) Overlay 2 Configuration 7 Register */
#define REG_LCDC_OVR2CFG8                      (0xF003028CU) /**< \brief (LCDC) Overlay 2 Configuration 8 Register */
#define REG_LCDC_OVR2CFG9                      (0xF0030290U) /**< \brief (LCDC) Overlay 2 Configuration 9 Register */
#define REG_LCDC_HEOCHER                       (0xF0030340U) /**< \brief (LCDC) High-End Overlay Channel Enable Register */
#define REG_LCDC_HEOCHDR                       (0xF0030344U) /**< \brief (LCDC) High-End Overlay Channel Disable Register */
#define REG_LCDC_HEOCHSR                       (0xF0030348U) /**< \brief (LCDC) High-End Overlay Channel Status Register */
#define REG_LCDC_HEOIER                        (0xF003034CU) /**< \brief (LCDC) High-End Overlay Interrupt Enable Register */
#define REG_LCDC_HEOIDR                        (0xF0030350U) /**< \brief (LCDC) High-End Overlay Interrupt Disable Register */
#define REG_LCDC_HEOIMR                        (0xF0030354U) /**< \brief (LCDC) High-End Overlay Interrupt Mask Register */
#define REG_LCDC_HEOISR                        (0xF0030358U) /**< \brief (LCDC) High-End Overlay Interrupt Status Register */
#define REG_LCDC_HEOHEAD                       (0xF003035CU) /**< \brief (LCDC) High-End Overlay DMA Head Register */
#define REG_LCDC_HEOADDR                       (0xF0030360U) /**< \brief (LCDC) High-End Overlay DMA Address Register */
#define REG_LCDC_HEOCTRL                       (0xF0030364U) /**< \brief (LCDC) High-End Overlay DMA Control Register */
#define REG_LCDC_HEONEXT                       (0xF0030368U) /**< \brief (LCDC) High-End Overlay DMA Next Register */
#define REG_LCDC_HEOUHEAD                      (0xF003036CU) /**< \brief (LCDC) High-End Overlay U DMA Head Register */
#define REG_LCDC_HEOUADDR                      (0xF0030370U) /**< \brief (LCDC) High-End Overlay U DMA Address Register */
#define REG_LCDC_HEOUCTRL                      (0xF0030374U) /**< \brief (LCDC) High-End Overlay U DMA control Register */
#define REG_LCDC_HEOUNEXT                      (0xF0030378U) /**< \brief (LCDC) High-End Overlay U DMA Next Register */
#define REG_LCDC_HEOVHEAD                      (0xF003037CU) /**< \brief (LCDC) High-End Overlay V DMA Head Register */
#define REG_LCDC_HEOVADDR                      (0xF0030380U) /**< \brief (LCDC) High-End Overlay V DMA Address Register */
#define REG_LCDC_HEOVCTRL                      (0xF0030384U) /**< \brief (LCDC) High-End Overlay V DMA control Register */
#define REG_LCDC_HEOVNEXT                      (0xF0030388U) /**< \brief (LCDC) High-End Overlay VDMA Next Register */
#define REG_LCDC_HEOCFG0                       (0xF003038CU) /**< \brief (LCDC) High-End Overlay Configuration Register 0 */
#define REG_LCDC_HEOCFG1                       (0xF0030390U) /**< \brief (LCDC) High-End Overlay Configuration Register 1 */
#define REG_LCDC_HEOCFG2                       (0xF0030394U) /**< \brief (LCDC) High-End Overlay Configuration Register 2 */
#define REG_LCDC_HEOCFG3                       (0xF0030398U) /**< \brief (LCDC) High-End Overlay Configuration Register 3 */
#define REG_LCDC_HEOCFG4                       (0xF003039CU) /**< \brief (LCDC) High-End Overlay Configuration Register 4 */
#define REG_LCDC_HEOCFG5                       (0xF00303A0U) /**< \brief (LCDC) High-End Overlay Configuration Register 5 */
#define REG_LCDC_HEOCFG6                       (0xF00303A4U) /**< \brief (LCDC) High-End Overlay Configuration Register 6 */
#define REG_LCDC_HEOCFG7                       (0xF00303A8U) /**< \brief (LCDC) High-End Overlay Configuration Register 7 */
#define REG_LCDC_HEOCFG8                       (0xF00303ACU) /**< \brief (LCDC) High-End Overlay Configuration Register 8 */
#define REG_LCDC_HEOCFG9                       (0xF00303B0U) /**< \brief (LCDC) High-End Overlay Configuration Register 9 */
#define REG_LCDC_HEOCFG10                      (0xF00303B4U) /**< \brief (LCDC) High-End Overlay Configuration Register 10 */
#define REG_LCDC_HEOCFG11                      (0xF00303B8U) /**< \brief (LCDC) High-End Overlay Configuration Register 11 */
#define REG_LCDC_HEOCFG12                      (0xF00303BCU) /**< \brief (LCDC) High-End Overlay Configuration Register 12 */
#define REG_LCDC_HEOCFG13                      (0xF00303C0U) /**< \brief (LCDC) High-End Overlay Configuration Register 13 */
#define REG_LCDC_HEOCFG14                      (0xF00303C4U) /**< \brief (LCDC) High-End Overlay Configuration Register 14 */
#define REG_LCDC_HEOCFG15                      (0xF00303C8U) /**< \brief (LCDC) High-End Overlay Configuration Register 15 */
#define REG_LCDC_HEOCFG16                      (0xF00303CCU) /**< \brief (LCDC) High-End Overlay Configuration Register 16 */
#define REG_LCDC_HEOCFG17                      (0xF00303D0U) /**< \brief (LCDC) High-End Overlay Configuration Register 17 */
#define REG_LCDC_HEOCFG18                      (0xF00303D4U) /**< \brief (LCDC) High-End Overlay Configuration Register 18 */
#define REG_LCDC_HEOCFG19                      (0xF00303D8U) /**< \brief (LCDC) High-End Overlay Configuration Register 19 */
#define REG_LCDC_HEOCFG20                      (0xF00303DCU) /**< \brief (LCDC) High-End Overlay Configuration Register 20 */
#define REG_LCDC_HEOCFG21                      (0xF00303E0U) /**< \brief (LCDC) High-End Overlay Configuration Register 21 */
#define REG_LCDC_HEOCFG22                      (0xF00303E4U) /**< \brief (LCDC) High-End Overlay Configuration Register 22 */
#define REG_LCDC_HEOCFG23                      (0xF00303E8U) /**< \brief (LCDC) High-End Overlay Configuration Register 23 */
#define REG_LCDC_HEOCFG24                      (0xF00303ECU) /**< \brief (LCDC) High-End Overlay Configuration Register 24 */
#define REG_LCDC_HEOCFG25                      (0xF00303F0U) /**< \brief (LCDC) High-End Overlay Configuration Register 25 */
#define REG_LCDC_HEOCFG26                      (0xF00303F4U) /**< \brief (LCDC) High-End Overlay Configuration Register 26 */
#define REG_LCDC_HEOCFG27                      (0xF00303F8U) /**< \brief (LCDC) High-End Overlay Configuration Register 27 */
#define REG_LCDC_HEOCFG28                      (0xF00303FCU) /**< \brief (LCDC) High-End Overlay Configuration Register 28 */
#define REG_LCDC_HEOCFG29                      (0xF0030400U) /**< \brief (LCDC) High-End Overlay Configuration Register 29 */
#define REG_LCDC_HEOCFG30                      (0xF0030404U) /**< \brief (LCDC) High-End Overlay Configuration Register 30 */
#define REG_LCDC_HEOCFG31                      (0xF0030408U) /**< \brief (LCDC) High-End Overlay Configuration Register 31 */
#define REG_LCDC_HEOCFG32                      (0xF003040CU) /**< \brief (LCDC) High-End Overlay Configuration Register 32 */
#define REG_LCDC_HEOCFG33                      (0xF0030410U) /**< \brief (LCDC) High-End Overlay Configuration Register 33 */
#define REG_LCDC_HEOCFG34                      (0xF0030414U) /**< \brief (LCDC) High-End Overlay Configuration Register 34 */
#define REG_LCDC_HEOCFG35                      (0xF0030418U) /**< \brief (LCDC) High-End Overlay Configuration Register 35 */
#define REG_LCDC_HEOCFG36                      (0xF003041CU) /**< \brief (LCDC) High-End Overlay Configuration Register 36 */
#define REG_LCDC_HEOCFG37                      (0xF0030420U) /**< \brief (LCDC) High-End Overlay Configuration Register 37 */
#define REG_LCDC_HEOCFG38                      (0xF0030424U) /**< \brief (LCDC) High-End Overlay Configuration Register 38 */
#define REG_LCDC_HEOCFG39                      (0xF0030428U) /**< \brief (LCDC) High-End Overlay Configuration Register 39 */
#define REG_LCDC_HEOCFG40                      (0xF003042CU) /**< \brief (LCDC) High-End Overlay Configuration Register 40 */
#define REG_LCDC_HEOCFG41                      (0xF0030430U) /**< \brief (LCDC) High-End Overlay Configuration Register 41 */
#define REG_LCDC_HCRCHER                       (0xF0030440U) /**< \brief (LCDC) Hardware Cursor Channel Enable Register */
#define REG_LCDC_HCRCHDR                       (0xF0030444U) /**< \brief (LCDC) Hardware Cursor Channel disable Register */
#define REG_LCDC_HCRCHSR                       (0xF0030448U) /**< \brief (LCDC) Hardware Cursor Channel Status Register */
#define REG_LCDC_HCRIER                        (0xF003044CU) /**< \brief (LCDC) Hardware Cursor Interrupt Enable Register */
#define REG_LCDC_HCRIDR                        (0xF0030450U) /**< \brief (LCDC) Hardware Cursor Interrupt Disable Register */
#define REG_LCDC_HCRIMR                        (0xF0030454U) /**< \brief (LCDC) Hardware Cursor Interrupt Mask Register */
#define REG_LCDC_HCRISR                        (0xF0030458U) /**< \brief (LCDC) Hardware Cursor Interrupt Status Register */
#define REG_LCDC_HCRHEAD                       (0xF003045CU) /**< \brief (LCDC) Hardware Cursor DMA Head Register */
#define REG_LCDC_HCRADDR                       (0xF0030460U) /**< \brief (LCDC) Hardware cursor DMA Address Register */
#define REG_LCDC_HCRCTRL                       (0xF0030464U) /**< \brief (LCDC) Hardware Cursor DMA Control Register */
#define REG_LCDC_HCRNEXT                       (0xF0030468U) /**< \brief (LCDC) Hardware Cursor DMA NExt Register */
#define REG_LCDC_HCRCFG0                       (0xF003046CU) /**< \brief (LCDC) Hardware Cursor Configuration 0 Register */
#define REG_LCDC_HCRCFG1                       (0xF0030470U) /**< \brief (LCDC) Hardware Cursor Configuration 1 Register */
#define REG_LCDC_HCRCFG2                       (0xF0030474U) /**< \brief (LCDC) Hardware Cursor Configuration 2 Register */
#define REG_LCDC_HCRCFG3                       (0xF0030478U) /**< \brief (LCDC) Hardware Cursor Configuration 3 Register */
#define REG_LCDC_HCRCFG4                       (0xF003047CU) /**< \brief (LCDC) Hardware Cursor Configuration 4 Register */
#define REG_LCDC_HCRCFG6                       (0xF0030484U) /**< \brief (LCDC) Hardware Cursor Configuration 6 Register */
#define REG_LCDC_HCRCFG7                       (0xF0030488U) /**< \brief (LCDC) Hardware Cursor Configuration 7 Register */
#define REG_LCDC_HCRCFG8                       (0xF003048CU) /**< \brief (LCDC) Hardware Cursor Configuration 8 Register */
#define REG_LCDC_HCRCFG9                       (0xF0030490U) /**< \brief (LCDC) Hardware Cursor Configuration 9 Register */
#define REG_LCDC_PPCHER                        (0xF0030540U) /**< \brief (LCDC) Post Processing Channel Enable Register */
#define REG_LCDC_PPCHDR                        (0xF0030544U) /**< \brief (LCDC) Post Processing Channel Disable Register */
#define REG_LCDC_PPCHSR                        (0xF0030548U) /**< \brief (LCDC) Post Processing Channel Status Register */
#define REG_LCDC_PPIER                         (0xF003054CU) /**< \brief (LCDC) Post Processing Interrupt Enable Register */
#define REG_LCDC_PPIDR                         (0xF0030550U) /**< \brief (LCDC) Post Processing Interrupt Disable Register */
#define REG_LCDC_PPIMR                         (0xF0030554U) /**< \brief (LCDC) Post Processing Interrupt Mask Register */
#define REG_LCDC_PPISR                         (0xF0030558U) /**< \brief (LCDC) Post Processing Interrupt Status Register */
#define REG_LCDC_PPHEAD                        (0xF003055CU) /**< \brief (LCDC) Post Processing Head Register */
#define REG_LCDC_PPADDR                        (0xF0030560U) /**< \brief (LCDC) Post Processing Address Register */
#define REG_LCDC_PPCTRL                        (0xF0030564U) /**< \brief (LCDC) Post Processing Control Register */
#define REG_LCDC_PPNEXT                        (0xF0030568U) /**< \brief (LCDC) Post Processing Next Register */
#define REG_LCDC_PPCFG0                        (0xF003056CU) /**< \brief (LCDC) Post Processing Configuration Register 0 */
#define REG_LCDC_PPCFG1                        (0xF0030570U) /**< \brief (LCDC) Post Processing Configuration Register 1 */
#define REG_LCDC_PPCFG2                        (0xF0030574U) /**< \brief (LCDC) Post Processing Configuration Register 2 */
#define REG_LCDC_PPCFG3                        (0xF0030578U) /**< \brief (LCDC) Post Processing Configuration Register 3 */
#define REG_LCDC_PPCFG4                        (0xF003057CU) /**< \brief (LCDC) Post Processing Configuration Register 4 */
#define REG_LCDC_PPCFG5                        (0xF0030580U) /**< \brief (LCDC) Post Processing Configuration Register 5 */
#define REG_LCDC_BASECLUT                      (0xF0030600U) /**< \brief (LCDC) Base CLUT Register */
#define REG_LCDC_OVR1CLUT                      (0xF0030A00U) /**< \brief (LCDC) Overlay 1 CLUT Register */
#define REG_LCDC_OVR2CLUT                      (0xF0030E00U) /**< \brief (LCDC) Overlay 2 CLUT Register */
#define REG_LCDC_HEOCLUT                       (0xF0031200U) /**< \brief (LCDC) High End Overlay CLUT Register */
#define REG_LCDC_HCRCLUT                       (0xF0031600U) /**< \brief (LCDC) Hardware Cursor CLUT Register */
#else
#define REG_LCDC_LCDCFG0              (*(RwReg*)0xF0030000U) /**< \brief (LCDC) LCD Controller Configuration Register 0 */
#define REG_LCDC_LCDCFG1              (*(RwReg*)0xF0030004U) /**< \brief (LCDC) LCD Controller Configuration Register 1 */
#define REG_LCDC_LCDCFG2              (*(RwReg*)0xF0030008U) /**< \brief (LCDC) LCD Controller Configuration Register 2 */
#define REG_LCDC_LCDCFG3              (*(RwReg*)0xF003000CU) /**< \brief (LCDC) LCD Controller Configuration Register 3 */
#define REG_LCDC_LCDCFG4              (*(RwReg*)0xF0030010U) /**< \brief (LCDC) LCD Controller Configuration Register 4 */
#define REG_LCDC_LCDCFG5              (*(RwReg*)0xF0030014U) /**< \brief (LCDC) LCD Controller Configuration Register 5 */
#define REG_LCDC_LCDCFG6              (*(RwReg*)0xF0030018U) /**< \brief (LCDC) LCD Controller Configuration Register 6 */
#define REG_LCDC_LCDEN                (*(WoReg*)0xF0030020U) /**< \brief (LCDC) LCD Controller Enable Register */
#define REG_LCDC_LCDDIS               (*(WoReg*)0xF0030024U) /**< \brief (LCDC) LCD Controller Disable Register */
#define REG_LCDC_LCDSR                (*(RoReg*)0xF0030028U) /**< \brief (LCDC) LCD Controller Status Register */
#define REG_LCDC_LCDIER               (*(WoReg*)0xF003002CU) /**< \brief (LCDC) LCD Controller Interrupt Enable Register */
#define REG_LCDC_LCDIDR               (*(WoReg*)0xF0030030U) /**< \brief (LCDC) LCD Controller Interrupt Disable Register */
#define REG_LCDC_LCDIMR               (*(RoReg*)0xF0030034U) /**< \brief (LCDC) LCD Controller Interrupt Mask Register */
#define REG_LCDC_LCDISR               (*(RoReg*)0xF0030038U) /**< \brief (LCDC) LCD Controller Interrupt Status Register */
#define REG_LCDC_BASECHER             (*(WoReg*)0xF0030040U) /**< \brief (LCDC) Base Layer Channel Enable Register */
#define REG_LCDC_BASECHDR             (*(WoReg*)0xF0030044U) /**< \brief (LCDC) Base Layer Channel Disable Register */
#define REG_LCDC_BASECHSR             (*(RoReg*)0xF0030048U) /**< \brief (LCDC) Base Layer Channel Status Register */
#define REG_LCDC_BASEIER              (*(WoReg*)0xF003004CU) /**< \brief (LCDC) Base Layer Interrupt Enable Register */
#define REG_LCDC_BASEIDR              (*(WoReg*)0xF0030050U) /**< \brief (LCDC) Base Layer Interrupt Disabled Register */
#define REG_LCDC_BASEIMR              (*(RoReg*)0xF0030054U) /**< \brief (LCDC) Base Layer Interrupt Mask Register */
#define REG_LCDC_BASEISR              (*(RoReg*)0xF0030058U) /**< \brief (LCDC) Base Layer Interrupt status Register */
#define REG_LCDC_BASEHEAD             (*(RwReg*)0xF003005CU) /**< \brief (LCDC) Base DMA Head Register */
#define REG_LCDC_BASEADDR             (*(RwReg*)0xF0030060U) /**< \brief (LCDC) Base DMA Address Register */
#define REG_LCDC_BASECTRL             (*(RwReg*)0xF0030064U) /**< \brief (LCDC) Base DMA Control Register */
#define REG_LCDC_BASENEXT             (*(RwReg*)0xF0030068U) /**< \brief (LCDC) Base DMA Next Register */
#define REG_LCDC_BASECFG0             (*(RwReg*)0xF003006CU) /**< \brief (LCDC) Base Configuration register 0 */
#define REG_LCDC_BASECFG1             (*(RwReg*)0xF0030070U) /**< \brief (LCDC) Base Configuration register 1 */
#define REG_LCDC_BASECFG2             (*(RwReg*)0xF0030074U) /**< \brief (LCDC) Base Configuration register 2 */
#define REG_LCDC_BASECFG3             (*(RwReg*)0xF0030078U) /**< \brief (LCDC) Base Configuration register 3 */
#define REG_LCDC_BASECFG4             (*(RwReg*)0xF003007CU) /**< \brief (LCDC) Base Configuration register 4 */
#define REG_LCDC_BASECFG5             (*(RwReg*)0xF0030080U) /**< \brief (LCDC) Base Configuration register 5 */
#define REG_LCDC_BASECFG6             (*(RwReg*)0xF0030084U) /**< \brief (LCDC) Base Configuration register 6 */
#define REG_LCDC_OVR1CHER             (*(WoReg*)0xF0030140U) /**< \brief (LCDC) Overlay 1 Channel Enable Register */
#define REG_LCDC_OVR1CHDR             (*(WoReg*)0xF0030144U) /**< \brief (LCDC) Overlay 1 Channel Disable Register */
#define REG_LCDC_OVR1CHSR             (*(RoReg*)0xF0030148U) /**< \brief (LCDC) Overlay 1 Channel Status Register */
#define REG_LCDC_OVR1IER              (*(WoReg*)0xF003014CU) /**< \brief (LCDC) Overlay 1 Interrupt Enable Register */
#define REG_LCDC_OVR1IDR              (*(WoReg*)0xF0030150U) /**< \brief (LCDC) Overlay 1 Interrupt Disable Register */
#define REG_LCDC_OVR1IMR              (*(RoReg*)0xF0030154U) /**< \brief (LCDC) Overlay 1 Interrupt Mask Register */
#define REG_LCDC_OVR1ISR              (*(RoReg*)0xF0030158U) /**< \brief (LCDC) Overlay 1 Interrupt Status Register */
#define REG_LCDC_OVR1HEAD             (*(RwReg*)0xF003015CU) /**< \brief (LCDC) Overlay 1 DMA Head Register */
#define REG_LCDC_OVR1ADDR             (*(RwReg*)0xF0030160U) /**< \brief (LCDC) Overlay 1 DMA Address Register */
#define REG_LCDC_OVR1CTRL             (*(RwReg*)0xF0030164U) /**< \brief (LCDC) Overlay1 DMA Control Register */
#define REG_LCDC_OVR1NEXT             (*(RwReg*)0xF0030168U) /**< \brief (LCDC) Overlay1 DMA Next Register */
#define REG_LCDC_OVR1CFG0             (*(RwReg*)0xF003016CU) /**< \brief (LCDC) Overlay 1 Configuration 0 Register */
#define REG_LCDC_OVR1CFG1             (*(RwReg*)0xF0030170U) /**< \brief (LCDC) Overlay 1 Configuration 1 Register */
#define REG_LCDC_OVR1CFG2             (*(RwReg*)0xF0030174U) /**< \brief (LCDC) Overlay 1 Configuration 2 Register */
#define REG_LCDC_OVR1CFG3             (*(RwReg*)0xF0030178U) /**< \brief (LCDC) Overlay 1 Configuration 3 Register */
#define REG_LCDC_OVR1CFG4             (*(RwReg*)0xF003017CU) /**< \brief (LCDC) Overlay 1 Configuration 4 Register */
#define REG_LCDC_OVR1CFG5             (*(RwReg*)0xF0030180U) /**< \brief (LCDC) Overlay 1 Configuration 5 Register */
#define REG_LCDC_OVR1CFG6             (*(RwReg*)0xF0030184U) /**< \brief (LCDC) Overlay 1 Configuration 6 Register */
#define REG_LCDC_OVR1CFG7             (*(RwReg*)0xF0030188U) /**< \brief (LCDC) Overlay 1 Configuration 7 Register */
#define REG_LCDC_OVR1CFG8             (*(RwReg*)0xF003018CU) /**< \brief (LCDC) Overlay 1 Configuration 8Register */
#define REG_LCDC_OVR1CFG9             (*(RwReg*)0xF0030190U) /**< \brief (LCDC) Overlay 1 Configuration 9 Register */
#define REG_LCDC_OVR2CHER             (*(WoReg*)0xF0030240U) /**< \brief (LCDC) Overlay 2 Channel Enable Register */
#define REG_LCDC_OVR2CHDR             (*(WoReg*)0xF0030244U) /**< \brief (LCDC) Overlay 2 Channel Disable Register */
#define REG_LCDC_OVR2CHSR             (*(RoReg*)0xF0030248U) /**< \brief (LCDC) Overlay 2 Channel Status Register */
#define REG_LCDC_OVR2IER              (*(WoReg*)0xF003024CU) /**< \brief (LCDC) Overlay 2 Interrupt Enable Register */
#define REG_LCDC_OVR2IDR              (*(WoReg*)0xF0030250U) /**< \brief (LCDC) Overlay 2 Interrupt Disable Register */
#define REG_LCDC_OVR2IMR              (*(RoReg*)0xF0030254U) /**< \brief (LCDC) Overlay 2 Interrupt Mask Register */
#define REG_LCDC_OVR2ISR              (*(RoReg*)0xF0030258U) /**< \brief (LCDC) Overlay 2 Interrupt status Register */
#define REG_LCDC_OVR2HEAD             (*(RwReg*)0xF003025CU) /**< \brief (LCDC) Overlay 2 DMA Head Register */
#define REG_LCDC_OVR2ADDR             (*(RwReg*)0xF0030260U) /**< \brief (LCDC) Overlay 2 DMA Address Register */
#define REG_LCDC_OVR2CTRL             (*(RwReg*)0xF0030264U) /**< \brief (LCDC) Overlay 2 DMA Control Register */
#define REG_LCDC_OVR2NEXT             (*(RwReg*)0xF0030268U) /**< \brief (LCDC) Overlay 2 DMA Next Register */
#define REG_LCDC_OVR2CFG0             (*(RwReg*)0xF003026CU) /**< \brief (LCDC) Overlay 2 Configuration 0 Register */
#define REG_LCDC_OVR2CFG1             (*(RwReg*)0xF0030270U) /**< \brief (LCDC) Overlay 2 Configuration 1 Register */
#define REG_LCDC_OVR2CFG2             (*(RwReg*)0xF0030274U) /**< \brief (LCDC) Overlay 2 Configuration 2 Register */
#define REG_LCDC_OVR2CFG3             (*(RwReg*)0xF0030278U) /**< \brief (LCDC) Overlay 2 Configuration 3 Register */
#define REG_LCDC_OVR2CFG4             (*(RwReg*)0xF003027CU) /**< \brief (LCDC) Overlay 2 Configuration 4 Register */
#define REG_LCDC_OVR2CFG5             (*(RwReg*)0xF0030280U) /**< \brief (LCDC) Overlay 2 Configuration 5 Register */
#define REG_LCDC_OVR2CFG6             (*(RwReg*)0xF0030284U) /**< \brief (LCDC) Overlay 2 Configuration 6 Register */
#define REG_LCDC_OVR2CFG7             (*(RwReg*)0xF0030288U) /**< \brief (LCDC) Overlay 2 Configuration 7 Register */
#define REG_LCDC_OVR2CFG8             (*(RwReg*)0xF003028CU) /**< \brief (LCDC) Overlay 2 Configuration 8 Register */
#define REG_LCDC_OVR2CFG9             (*(RwReg*)0xF0030290U) /**< \brief (LCDC) Overlay 2 Configuration 9 Register */
#define REG_LCDC_HEOCHER              (*(WoReg*)0xF0030340U) /**< \brief (LCDC) High-End Overlay Channel Enable Register */
#define REG_LCDC_HEOCHDR              (*(WoReg*)0xF0030344U) /**< \brief (LCDC) High-End Overlay Channel Disable Register */
#define REG_LCDC_HEOCHSR              (*(RoReg*)0xF0030348U) /**< \brief (LCDC) High-End Overlay Channel Status Register */
#define REG_LCDC_HEOIER               (*(WoReg*)0xF003034CU) /**< \brief (LCDC) High-End Overlay Interrupt Enable Register */
#define REG_LCDC_HEOIDR               (*(WoReg*)0xF0030350U) /**< \brief (LCDC) High-End Overlay Interrupt Disable Register */
#define REG_LCDC_HEOIMR               (*(RoReg*)0xF0030354U) /**< \brief (LCDC) High-End Overlay Interrupt Mask Register */
#define REG_LCDC_HEOISR               (*(RoReg*)0xF0030358U) /**< \brief (LCDC) High-End Overlay Interrupt Status Register */
#define REG_LCDC_HEOHEAD              (*(RwReg*)0xF003035CU) /**< \brief (LCDC) High-End Overlay DMA Head Register */
#define REG_LCDC_HEOADDR              (*(RwReg*)0xF0030360U) /**< \brief (LCDC) High-End Overlay DMA Address Register */
#define REG_LCDC_HEOCTRL              (*(RwReg*)0xF0030364U) /**< \brief (LCDC) High-End Overlay DMA Control Register */
#define REG_LCDC_HEONEXT              (*(RwReg*)0xF0030368U) /**< \brief (LCDC) High-End Overlay DMA Next Register */
#define REG_LCDC_HEOUHEAD             (*(RwReg*)0xF003036CU) /**< \brief (LCDC) High-End Overlay U DMA Head Register */
#define REG_LCDC_HEOUADDR             (*(RwReg*)0xF0030370U) /**< \brief (LCDC) High-End Overlay U DMA Address Register */
#define REG_LCDC_HEOUCTRL             (*(RwReg*)0xF0030374U) /**< \brief (LCDC) High-End Overlay U DMA control Register */
#define REG_LCDC_HEOUNEXT             (*(RwReg*)0xF0030378U) /**< \brief (LCDC) High-End Overlay U DMA Next Register */
#define REG_LCDC_HEOVHEAD             (*(RwReg*)0xF003037CU) /**< \brief (LCDC) High-End Overlay V DMA Head Register */
#define REG_LCDC_HEOVADDR             (*(RwReg*)0xF0030380U) /**< \brief (LCDC) High-End Overlay V DMA Address Register */
#define REG_LCDC_HEOVCTRL             (*(RwReg*)0xF0030384U) /**< \brief (LCDC) High-End Overlay V DMA control Register */
#define REG_LCDC_HEOVNEXT             (*(RwReg*)0xF0030388U) /**< \brief (LCDC) High-End Overlay VDMA Next Register */
#define REG_LCDC_HEOCFG0              (*(RwReg*)0xF003038CU) /**< \brief (LCDC) High-End Overlay Configuration Register 0 */
#define REG_LCDC_HEOCFG1              (*(RwReg*)0xF0030390U) /**< \brief (LCDC) High-End Overlay Configuration Register 1 */
#define REG_LCDC_HEOCFG2              (*(RwReg*)0xF0030394U) /**< \brief (LCDC) High-End Overlay Configuration Register 2 */
#define REG_LCDC_HEOCFG3              (*(RwReg*)0xF0030398U) /**< \brief (LCDC) High-End Overlay Configuration Register 3 */
#define REG_LCDC_HEOCFG4              (*(RwReg*)0xF003039CU) /**< \brief (LCDC) High-End Overlay Configuration Register 4 */
#define REG_LCDC_HEOCFG5              (*(RwReg*)0xF00303A0U) /**< \brief (LCDC) High-End Overlay Configuration Register 5 */
#define REG_LCDC_HEOCFG6              (*(RwReg*)0xF00303A4U) /**< \brief (LCDC) High-End Overlay Configuration Register 6 */
#define REG_LCDC_HEOCFG7              (*(RwReg*)0xF00303A8U) /**< \brief (LCDC) High-End Overlay Configuration Register 7 */
#define REG_LCDC_HEOCFG8              (*(RwReg*)0xF00303ACU) /**< \brief (LCDC) High-End Overlay Configuration Register 8 */
#define REG_LCDC_HEOCFG9              (*(RwReg*)0xF00303B0U) /**< \brief (LCDC) High-End Overlay Configuration Register 9 */
#define REG_LCDC_HEOCFG10             (*(RwReg*)0xF00303B4U) /**< \brief (LCDC) High-End Overlay Configuration Register 10 */
#define REG_LCDC_HEOCFG11             (*(RwReg*)0xF00303B8U) /**< \brief (LCDC) High-End Overlay Configuration Register 11 */
#define REG_LCDC_HEOCFG12             (*(RwReg*)0xF00303BCU) /**< \brief (LCDC) High-End Overlay Configuration Register 12 */
#define REG_LCDC_HEOCFG13             (*(RwReg*)0xF00303C0U) /**< \brief (LCDC) High-End Overlay Configuration Register 13 */
#define REG_LCDC_HEOCFG14             (*(RwReg*)0xF00303C4U) /**< \brief (LCDC) High-End Overlay Configuration Register 14 */
#define REG_LCDC_HEOCFG15             (*(RwReg*)0xF00303C8U) /**< \brief (LCDC) High-End Overlay Configuration Register 15 */
#define REG_LCDC_HEOCFG16             (*(RwReg*)0xF00303CCU) /**< \brief (LCDC) High-End Overlay Configuration Register 16 */
#define REG_LCDC_HEOCFG17             (*(RwReg*)0xF00303D0U) /**< \brief (LCDC) High-End Overlay Configuration Register 17 */
#define REG_LCDC_HEOCFG18             (*(RwReg*)0xF00303D4U) /**< \brief (LCDC) High-End Overlay Configuration Register 18 */
#define REG_LCDC_HEOCFG19             (*(RwReg*)0xF00303D8U) /**< \brief (LCDC) High-End Overlay Configuration Register 19 */
#define REG_LCDC_HEOCFG20             (*(RwReg*)0xF00303DCU) /**< \brief (LCDC) High-End Overlay Configuration Register 20 */
#define REG_LCDC_HEOCFG21             (*(RwReg*)0xF00303E0U) /**< \brief (LCDC) High-End Overlay Configuration Register 21 */
#define REG_LCDC_HEOCFG22             (*(RwReg*)0xF00303E4U) /**< \brief (LCDC) High-End Overlay Configuration Register 22 */
#define REG_LCDC_HEOCFG23             (*(RwReg*)0xF00303E8U) /**< \brief (LCDC) High-End Overlay Configuration Register 23 */
#define REG_LCDC_HEOCFG24             (*(RwReg*)0xF00303ECU) /**< \brief (LCDC) High-End Overlay Configuration Register 24 */
#define REG_LCDC_HEOCFG25             (*(RwReg*)0xF00303F0U) /**< \brief (LCDC) High-End Overlay Configuration Register 25 */
#define REG_LCDC_HEOCFG26             (*(RwReg*)0xF00303F4U) /**< \brief (LCDC) High-End Overlay Configuration Register 26 */
#define REG_LCDC_HEOCFG27             (*(RwReg*)0xF00303F8U) /**< \brief (LCDC) High-End Overlay Configuration Register 27 */
#define REG_LCDC_HEOCFG28             (*(RwReg*)0xF00303FCU) /**< \brief (LCDC) High-End Overlay Configuration Register 28 */
#define REG_LCDC_HEOCFG29             (*(RwReg*)0xF0030400U) /**< \brief (LCDC) High-End Overlay Configuration Register 29 */
#define REG_LCDC_HEOCFG30             (*(RwReg*)0xF0030404U) /**< \brief (LCDC) High-End Overlay Configuration Register 30 */
#define REG_LCDC_HEOCFG31             (*(RwReg*)0xF0030408U) /**< \brief (LCDC) High-End Overlay Configuration Register 31 */
#define REG_LCDC_HEOCFG32             (*(RwReg*)0xF003040CU) /**< \brief (LCDC) High-End Overlay Configuration Register 32 */
#define REG_LCDC_HEOCFG33             (*(RwReg*)0xF0030410U) /**< \brief (LCDC) High-End Overlay Configuration Register 33 */
#define REG_LCDC_HEOCFG34             (*(RwReg*)0xF0030414U) /**< \brief (LCDC) High-End Overlay Configuration Register 34 */
#define REG_LCDC_HEOCFG35             (*(RwReg*)0xF0030418U) /**< \brief (LCDC) High-End Overlay Configuration Register 35 */
#define REG_LCDC_HEOCFG36             (*(RwReg*)0xF003041CU) /**< \brief (LCDC) High-End Overlay Configuration Register 36 */
#define REG_LCDC_HEOCFG37             (*(RwReg*)0xF0030420U) /**< \brief (LCDC) High-End Overlay Configuration Register 37 */
#define REG_LCDC_HEOCFG38             (*(RwReg*)0xF0030424U) /**< \brief (LCDC) High-End Overlay Configuration Register 38 */
#define REG_LCDC_HEOCFG39             (*(RwReg*)0xF0030428U) /**< \brief (LCDC) High-End Overlay Configuration Register 39 */
#define REG_LCDC_HEOCFG40             (*(RwReg*)0xF003042CU) /**< \brief (LCDC) High-End Overlay Configuration Register 40 */
#define REG_LCDC_HEOCFG41             (*(RwReg*)0xF0030430U) /**< \brief (LCDC) High-End Overlay Configuration Register 41 */
#define REG_LCDC_HCRCHER              (*(WoReg*)0xF0030440U) /**< \brief (LCDC) Hardware Cursor Channel Enable Register */
#define REG_LCDC_HCRCHDR              (*(WoReg*)0xF0030444U) /**< \brief (LCDC) Hardware Cursor Channel disable Register */
#define REG_LCDC_HCRCHSR              (*(RoReg*)0xF0030448U) /**< \brief (LCDC) Hardware Cursor Channel Status Register */
#define REG_LCDC_HCRIER               (*(WoReg*)0xF003044CU) /**< \brief (LCDC) Hardware Cursor Interrupt Enable Register */
#define REG_LCDC_HCRIDR               (*(WoReg*)0xF0030450U) /**< \brief (LCDC) Hardware Cursor Interrupt Disable Register */
#define REG_LCDC_HCRIMR               (*(RoReg*)0xF0030454U) /**< \brief (LCDC) Hardware Cursor Interrupt Mask Register */
#define REG_LCDC_HCRISR               (*(RoReg*)0xF0030458U) /**< \brief (LCDC) Hardware Cursor Interrupt Status Register */
#define REG_LCDC_HCRHEAD              (*(RwReg*)0xF003045CU) /**< \brief (LCDC) Hardware Cursor DMA Head Register */
#define REG_LCDC_HCRADDR              (*(RwReg*)0xF0030460U) /**< \brief (LCDC) Hardware cursor DMA Address Register */
#define REG_LCDC_HCRCTRL              (*(RwReg*)0xF0030464U) /**< \brief (LCDC) Hardware Cursor DMA Control Register */
#define REG_LCDC_HCRNEXT              (*(RwReg*)0xF0030468U) /**< \brief (LCDC) Hardware Cursor DMA NExt Register */
#define REG_LCDC_HCRCFG0              (*(RwReg*)0xF003046CU) /**< \brief (LCDC) Hardware Cursor Configuration 0 Register */
#define REG_LCDC_HCRCFG1              (*(RwReg*)0xF0030470U) /**< \brief (LCDC) Hardware Cursor Configuration 1 Register */
#define REG_LCDC_HCRCFG2              (*(RwReg*)0xF0030474U) /**< \brief (LCDC) Hardware Cursor Configuration 2 Register */
#define REG_LCDC_HCRCFG3              (*(RwReg*)0xF0030478U) /**< \brief (LCDC) Hardware Cursor Configuration 3 Register */
#define REG_LCDC_HCRCFG4              (*(RwReg*)0xF003047CU) /**< \brief (LCDC) Hardware Cursor Configuration 4 Register */
#define REG_LCDC_HCRCFG6              (*(RwReg*)0xF0030484U) /**< \brief (LCDC) Hardware Cursor Configuration 6 Register */
#define REG_LCDC_HCRCFG7              (*(RwReg*)0xF0030488U) /**< \brief (LCDC) Hardware Cursor Configuration 7 Register */
#define REG_LCDC_HCRCFG8              (*(RwReg*)0xF003048CU) /**< \brief (LCDC) Hardware Cursor Configuration 8 Register */
#define REG_LCDC_HCRCFG9              (*(RwReg*)0xF0030490U) /**< \brief (LCDC) Hardware Cursor Configuration 9 Register */
#define REG_LCDC_PPCHER               (*(WoReg*)0xF0030540U) /**< \brief (LCDC) Post Processing Channel Enable Register */
#define REG_LCDC_PPCHDR               (*(WoReg*)0xF0030544U) /**< \brief (LCDC) Post Processing Channel Disable Register */
#define REG_LCDC_PPCHSR               (*(RoReg*)0xF0030548U) /**< \brief (LCDC) Post Processing Channel Status Register */
#define REG_LCDC_PPIER                (*(WoReg*)0xF003054CU) /**< \brief (LCDC) Post Processing Interrupt Enable Register */
#define REG_LCDC_PPIDR                (*(WoReg*)0xF0030550U) /**< \brief (LCDC) Post Processing Interrupt Disable Register */
#define REG_LCDC_PPIMR                (*(RoReg*)0xF0030554U) /**< \brief (LCDC) Post Processing Interrupt Mask Register */
#define REG_LCDC_PPISR                (*(RoReg*)0xF0030558U) /**< \brief (LCDC) Post Processing Interrupt Status Register */
#define REG_LCDC_PPHEAD               (*(RwReg*)0xF003055CU) /**< \brief (LCDC) Post Processing Head Register */
#define REG_LCDC_PPADDR               (*(RwReg*)0xF0030560U) /**< \brief (LCDC) Post Processing Address Register */
#define REG_LCDC_PPCTRL               (*(RwReg*)0xF0030564U) /**< \brief (LCDC) Post Processing Control Register */
#define REG_LCDC_PPNEXT               (*(RwReg*)0xF0030568U) /**< \brief (LCDC) Post Processing Next Register */
#define REG_LCDC_PPCFG0               (*(RwReg*)0xF003056CU) /**< \brief (LCDC) Post Processing Configuration Register 0 */
#define REG_LCDC_PPCFG1               (*(RwReg*)0xF0030570U) /**< \brief (LCDC) Post Processing Configuration Register 1 */
#define REG_LCDC_PPCFG2               (*(RwReg*)0xF0030574U) /**< \brief (LCDC) Post Processing Configuration Register 2 */
#define REG_LCDC_PPCFG3               (*(RwReg*)0xF0030578U) /**< \brief (LCDC) Post Processing Configuration Register 3 */
#define REG_LCDC_PPCFG4               (*(RwReg*)0xF003057CU) /**< \brief (LCDC) Post Processing Configuration Register 4 */
#define REG_LCDC_PPCFG5               (*(RwReg*)0xF0030580U) /**< \brief (LCDC) Post Processing Configuration Register 5 */
#define REG_LCDC_BASECLUT             (*(RwReg*)0xF0030600U) /**< \brief (LCDC) Base CLUT Register */
#define REG_LCDC_OVR1CLUT             (*(RwReg*)0xF0030A00U) /**< \brief (LCDC) Overlay 1 CLUT Register */
#define REG_LCDC_OVR2CLUT             (*(RwReg*)0xF0030E00U) /**< \brief (LCDC) Overlay 2 CLUT Register */
#define REG_LCDC_HEOCLUT              (*(RwReg*)0xF0031200U) /**< \brief (LCDC) High End Overlay CLUT Register */
#define REG_LCDC_HCRCLUT              (*(RwReg*)0xF0031600U) /**< \brief (LCDC) Hardware Cursor CLUT Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for ISI peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_ISI_CFG1                           (0xF0034000U) /**< \brief (ISI) ISI Configuration 1 Register */
#define REG_ISI_CFG2                           (0xF0034004U) /**< \brief (ISI) ISI Configuration 2 Register */
#define REG_ISI_PSIZE                          (0xF0034008U) /**< \brief (ISI) ISI Preview Size Register */
#define REG_ISI_PDECF                          (0xF003400CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */
#define REG_ISI_Y2R_SET0                       (0xF0034010U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 0 Register */
#define REG_ISI_Y2R_SET1                       (0xF0034014U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 1 Register */
#define REG_ISI_R2Y_SET0                       (0xF0034018U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 0 Register */
#define REG_ISI_R2Y_SET1                       (0xF003401CU) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 1 Register */
#define REG_ISI_R2Y_SET2                       (0xF0034020U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 2 Register */
#define REG_ISI_CR                             (0xF0034024U) /**< \brief (ISI) ISI Control Register */
#define REG_ISI_SR                             (0xF0034028U) /**< \brief (ISI) ISI Status Register */
#define REG_ISI_IER                            (0xF003402CU) /**< \brief (ISI) ISI Interrupt Enable Register */
#define REG_ISI_IDR                            (0xF0034030U) /**< \brief (ISI) ISI Interrupt Disable Register */
#define REG_ISI_IMR                            (0xF0034034U) /**< \brief (ISI) ISI Interrupt Mask Register */
#define REG_ISI_DMA_CHER                       (0xF0034038U) /**< \brief (ISI) DMA Channel Enable Register */
#define REG_ISI_DMA_CHDR                       (0xF003403CU) /**< \brief (ISI) DMA Channel Disable Register */
#define REG_ISI_DMA_CHSR                       (0xF0034040U) /**< \brief (ISI) DMA Channel Status Register */
#define REG_ISI_DMA_P_ADDR                     (0xF0034044U) /**< \brief (ISI) DMA Preview Base Address Register */
#define REG_ISI_DMA_P_CTRL                     (0xF0034048U) /**< \brief (ISI) DMA Preview Control Register */
#define REG_ISI_DMA_P_DSCR                     (0xF003404CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */
#define REG_ISI_DMA_C_ADDR                     (0xF0034050U) /**< \brief (ISI) DMA Codec Base Address Register */
#define REG_ISI_DMA_C_CTRL                     (0xF0034054U) /**< \brief (ISI) DMA Codec Control Register */
#define REG_ISI_DMA_C_DSCR                     (0xF0034058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */
#define REG_ISI_WPCR                           (0xF00340E4U) /**< \brief (ISI) Write Protection Control Register */
#define REG_ISI_WPSR                           (0xF00340E8U) /**< \brief (ISI) Write Protection Status Register */
#else
#define REG_ISI_CFG1                  (*(RwReg*)0xF0034000U) /**< \brief (ISI) ISI Configuration 1 Register */
#define REG_ISI_CFG2                  (*(RwReg*)0xF0034004U) /**< \brief (ISI) ISI Configuration 2 Register */
#define REG_ISI_PSIZE                 (*(RwReg*)0xF0034008U) /**< \brief (ISI) ISI Preview Size Register */
#define REG_ISI_PDECF                 (*(RwReg*)0xF003400CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */
#define REG_ISI_Y2R_SET0              (*(RwReg*)0xF0034010U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 0 Register */
#define REG_ISI_Y2R_SET1              (*(RwReg*)0xF0034014U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 1 Register */
#define REG_ISI_R2Y_SET0              (*(RwReg*)0xF0034018U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 0 Register */
#define REG_ISI_R2Y_SET1              (*(RwReg*)0xF003401CU) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 1 Register */
#define REG_ISI_R2Y_SET2              (*(RwReg*)0xF0034020U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 2 Register */
#define REG_ISI_CR                    (*(WoReg*)0xF0034024U) /**< \brief (ISI) ISI Control Register */
#define REG_ISI_SR                    (*(RoReg*)0xF0034028U) /**< \brief (ISI) ISI Status Register */
#define REG_ISI_IER                   (*(WoReg*)0xF003402CU) /**< \brief (ISI) ISI Interrupt Enable Register */
#define REG_ISI_IDR                   (*(WoReg*)0xF0034030U) /**< \brief (ISI) ISI Interrupt Disable Register */
#define REG_ISI_IMR                   (*(RoReg*)0xF0034034U) /**< \brief (ISI) ISI Interrupt Mask Register */
#define REG_ISI_DMA_CHER              (*(WoReg*)0xF0034038U) /**< \brief (ISI) DMA Channel Enable Register */
#define REG_ISI_DMA_CHDR              (*(WoReg*)0xF003403CU) /**< \brief (ISI) DMA Channel Disable Register */
#define REG_ISI_DMA_CHSR              (*(RoReg*)0xF0034040U) /**< \brief (ISI) DMA Channel Status Register */
#define REG_ISI_DMA_P_ADDR            (*(RwReg*)0xF0034044U) /**< \brief (ISI) DMA Preview Base Address Register */
#define REG_ISI_DMA_P_CTRL            (*(RwReg*)0xF0034048U) /**< \brief (ISI) DMA Preview Control Register */
#define REG_ISI_DMA_P_DSCR            (*(RwReg*)0xF003404CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */
#define REG_ISI_DMA_C_ADDR            (*(RwReg*)0xF0034050U) /**< \brief (ISI) DMA Codec Base Address Register */
#define REG_ISI_DMA_C_CTRL            (*(RwReg*)0xF0034054U) /**< \brief (ISI) DMA Codec Control Register */
#define REG_ISI_DMA_C_DSCR            (*(RwReg*)0xF0034058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */
#define REG_ISI_WPCR                  (*(RwReg*)0xF00340E4U) /**< \brief (ISI) Write Protection Control Register */
#define REG_ISI_WPSR                  (*(RoReg*)0xF00340E8U) /**< \brief (ISI) Write Protection Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for SFR peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_SFR_OHCIICR                        (0xF0038010U) /**< \brief (SFR) OHCI Interrupt Configuration Register */
#define REG_SFR_OHCIISR                        (0xF0038014U) /**< \brief (SFR) OHCI Interrupt Status Register */
#define REG_SFR_AHB                            (0xF0038020U) /**< \brief (SFR) AHB Configuration Register */
#define REG_SFR_BRIDGE                         (0xF0038024U) /**< \brief (SFR) Bridge Configuration Register */
#define REG_SFR_SECURE                         (0xF0038028U) /**< \brief (SFR) Security Configuration Register */
#define REG_SFR_UTMICKTRIM                     (0xF0038030U) /**< \brief (SFR) UTMI Clock Trimming Register */
#define REG_SFR_UTMIHSTRIM                     (0xF0038034U) /**< \brief (SFR) UTMI High Speed Trimming Register */
#define REG_SFR_UTMIFSTRIM                     (0xF0038038U) /**< \brief (SFR) UTMI Full Speed Trimming Register */
#define REG_SFR_UTMISWAP                       (0xF003803CU) /**< \brief (SFR) UTMI DP/DM Pin Swapping Register */
#define REG_SFR_EBICFG                         (0xF0038040U) /**< \brief (SFR) EBI Configuration Register */
#else
#define REG_SFR_OHCIICR               (*(RwReg*)0xF0038010U) /**< \brief (SFR) OHCI Interrupt Configuration Register */
#define REG_SFR_OHCIISR               (*(RoReg*)0xF0038014U) /**< \brief (SFR) OHCI Interrupt Status Register */
#define REG_SFR_AHB                   (*(RwReg*)0xF0038020U) /**< \brief (SFR) AHB Configuration Register */
#define REG_SFR_BRIDGE                (*(RwReg*)0xF0038024U) /**< \brief (SFR) Bridge Configuration Register */
#define REG_SFR_SECURE                (*(RwReg*)0xF0038028U) /**< \brief (SFR) Security Configuration Register */
#define REG_SFR_UTMICKTRIM            (*(RwReg*)0xF0038030U) /**< \brief (SFR) UTMI Clock Trimming Register */
#define REG_SFR_UTMIHSTRIM            (*(RwReg*)0xF0038034U) /**< \brief (SFR) UTMI High Speed Trimming Register */
#define REG_SFR_UTMIFSTRIM            (*(RwReg*)0xF0038038U) /**< \brief (SFR) UTMI Full Speed Trimming Register */
#define REG_SFR_UTMISWAP              (*(RwReg*)0xF003803CU) /**< \brief (SFR) UTMI DP/DM Pin Swapping Register */
#define REG_SFR_EBICFG                (*(RwReg*)0xF0038040U) /**< \brief (SFR) EBI Configuration Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for HSMCI1 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_HSMCI1_CR                          (0xF8000000U) /**< \brief (HSMCI1) Control Register */
#define REG_HSMCI1_MR                          (0xF8000004U) /**< \brief (HSMCI1) Mode Register */
#define REG_HSMCI1_DTOR                        (0xF8000008U) /**< \brief (HSMCI1) Data Timeout Register */
#define REG_HSMCI1_SDCR                        (0xF800000CU) /**< \brief (HSMCI1) SD/SDIO Card Register */
#define REG_HSMCI1_ARGR                        (0xF8000010U) /**< \brief (HSMCI1) Argument Register */
#define REG_HSMCI1_CMDR                        (0xF8000014U) /**< \brief (HSMCI1) Command Register */
#define REG_HSMCI1_BLKR                        (0xF8000018U) /**< \brief (HSMCI1) Block Register */
#define REG_HSMCI1_CSTOR                       (0xF800001CU) /**< \brief (HSMCI1) Completion Signal Timeout Register */
#define REG_HSMCI1_RSPR                        (0xF8000020U) /**< \brief (HSMCI1) Response Register */
#define REG_HSMCI1_RDR                         (0xF8000030U) /**< \brief (HSMCI1) Receive Data Register */
#define REG_HSMCI1_TDR                         (0xF8000034U) /**< \brief (HSMCI1) Transmit Data Register */
#define REG_HSMCI1_SR                          (0xF8000040U) /**< \brief (HSMCI1) Status Register */
#define REG_HSMCI1_IER                         (0xF8000044U) /**< \brief (HSMCI1) Interrupt Enable Register */
#define REG_HSMCI1_IDR                         (0xF8000048U) /**< \brief (HSMCI1) Interrupt Disable Register */
#define REG_HSMCI1_IMR                         (0xF800004CU) /**< \brief (HSMCI1) Interrupt Mask Register */
#define REG_HSMCI1_DMA                         (0xF8000050U) /**< \brief (HSMCI1) DMA Configuration Register */
#define REG_HSMCI1_CFG                         (0xF8000054U) /**< \brief (HSMCI1) Configuration Register */
#define REG_HSMCI1_WPMR                        (0xF80000E4U) /**< \brief (HSMCI1) Write Protection Mode Register */
#define REG_HSMCI1_WPSR                        (0xF80000E8U) /**< \brief (HSMCI1) Write Protection Status Register */
#define REG_HSMCI1_FIFO                        (0xF8000200U) /**< \brief (HSMCI1) FIFO Memory Aperture0 */
#else
#define REG_HSMCI1_CR                 (*(WoReg*)0xF8000000U) /**< \brief (HSMCI1) Control Register */
#define REG_HSMCI1_MR                 (*(RwReg*)0xF8000004U) /**< \brief (HSMCI1) Mode Register */
#define REG_HSMCI1_DTOR               (*(RwReg*)0xF8000008U) /**< \brief (HSMCI1) Data Timeout Register */
#define REG_HSMCI1_SDCR               (*(RwReg*)0xF800000CU) /**< \brief (HSMCI1) SD/SDIO Card Register */
#define REG_HSMCI1_ARGR               (*(RwReg*)0xF8000010U) /**< \brief (HSMCI1) Argument Register */
#define REG_HSMCI1_CMDR               (*(WoReg*)0xF8000014U) /**< \brief (HSMCI1) Command Register */
#define REG_HSMCI1_BLKR               (*(RwReg*)0xF8000018U) /**< \brief (HSMCI1) Block Register */
#define REG_HSMCI1_CSTOR              (*(RwReg*)0xF800001CU) /**< \brief (HSMCI1) Completion Signal Timeout Register */
#define REG_HSMCI1_RSPR               (*(RoReg*)0xF8000020U) /**< \brief (HSMCI1) Response Register */
#define REG_HSMCI1_RDR                (*(RoReg*)0xF8000030U) /**< \brief (HSMCI1) Receive Data Register */
#define REG_HSMCI1_TDR                (*(WoReg*)0xF8000034U) /**< \brief (HSMCI1) Transmit Data Register */
#define REG_HSMCI1_SR                 (*(RoReg*)0xF8000040U) /**< \brief (HSMCI1) Status Register */
#define REG_HSMCI1_IER                (*(WoReg*)0xF8000044U) /**< \brief (HSMCI1) Interrupt Enable Register */
#define REG_HSMCI1_IDR                (*(WoReg*)0xF8000048U) /**< \brief (HSMCI1) Interrupt Disable Register */
#define REG_HSMCI1_IMR                (*(RoReg*)0xF800004CU) /**< \brief (HSMCI1) Interrupt Mask Register */
#define REG_HSMCI1_DMA                (*(RwReg*)0xF8000050U) /**< \brief (HSMCI1) DMA Configuration Register */
#define REG_HSMCI1_CFG                (*(RwReg*)0xF8000054U) /**< \brief (HSMCI1) Configuration Register */
#define REG_HSMCI1_WPMR               (*(RwReg*)0xF80000E4U) /**< \brief (HSMCI1) Write Protection Mode Register */
#define REG_HSMCI1_WPSR               (*(RoReg*)0xF80000E8U) /**< \brief (HSMCI1) Write Protection Status Register */
#define REG_HSMCI1_FIFO               (*(RwReg*)0xF8000200U) /**< \brief (HSMCI1) FIFO Memory Aperture0 */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for HSMCI2 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_HSMCI2_CR                          (0xF8004000U) /**< \brief (HSMCI2) Control Register */
#define REG_HSMCI2_MR                          (0xF8004004U) /**< \brief (HSMCI2) Mode Register */
#define REG_HSMCI2_DTOR                        (0xF8004008U) /**< \brief (HSMCI2) Data Timeout Register */
#define REG_HSMCI2_SDCR                        (0xF800400CU) /**< \brief (HSMCI2) SD/SDIO Card Register */
#define REG_HSMCI2_ARGR                        (0xF8004010U) /**< \brief (HSMCI2) Argument Register */
#define REG_HSMCI2_CMDR                        (0xF8004014U) /**< \brief (HSMCI2) Command Register */
#define REG_HSMCI2_BLKR                        (0xF8004018U) /**< \brief (HSMCI2) Block Register */
#define REG_HSMCI2_CSTOR                       (0xF800401CU) /**< \brief (HSMCI2) Completion Signal Timeout Register */
#define REG_HSMCI2_RSPR                        (0xF8004020U) /**< \brief (HSMCI2) Response Register */
#define REG_HSMCI2_RDR                         (0xF8004030U) /**< \brief (HSMCI2) Receive Data Register */
#define REG_HSMCI2_TDR                         (0xF8004034U) /**< \brief (HSMCI2) Transmit Data Register */
#define REG_HSMCI2_SR                          (0xF8004040U) /**< \brief (HSMCI2) Status Register */
#define REG_HSMCI2_IER                         (0xF8004044U) /**< \brief (HSMCI2) Interrupt Enable Register */
#define REG_HSMCI2_IDR                         (0xF8004048U) /**< \brief (HSMCI2) Interrupt Disable Register */
#define REG_HSMCI2_IMR                         (0xF800404CU) /**< \brief (HSMCI2) Interrupt Mask Register */
#define REG_HSMCI2_DMA                         (0xF8004050U) /**< \brief (HSMCI2) DMA Configuration Register */
#define REG_HSMCI2_CFG                         (0xF8004054U) /**< \brief (HSMCI2) Configuration Register */
#define REG_HSMCI2_WPMR                        (0xF80040E4U) /**< \brief (HSMCI2) Write Protection Mode Register */
#define REG_HSMCI2_WPSR                        (0xF80040E8U) /**< \brief (HSMCI2) Write Protection Status Register */
#define REG_HSMCI2_FIFO                        (0xF8004200U) /**< \brief (HSMCI2) FIFO Memory Aperture0 */
#else
#define REG_HSMCI2_CR                 (*(WoReg*)0xF8004000U) /**< \brief (HSMCI2) Control Register */
#define REG_HSMCI2_MR                 (*(RwReg*)0xF8004004U) /**< \brief (HSMCI2) Mode Register */
#define REG_HSMCI2_DTOR               (*(RwReg*)0xF8004008U) /**< \brief (HSMCI2) Data Timeout Register */
#define REG_HSMCI2_SDCR               (*(RwReg*)0xF800400CU) /**< \brief (HSMCI2) SD/SDIO Card Register */
#define REG_HSMCI2_ARGR               (*(RwReg*)0xF8004010U) /**< \brief (HSMCI2) Argument Register */
#define REG_HSMCI2_CMDR               (*(WoReg*)0xF8004014U) /**< \brief (HSMCI2) Command Register */
#define REG_HSMCI2_BLKR               (*(RwReg*)0xF8004018U) /**< \brief (HSMCI2) Block Register */
#define REG_HSMCI2_CSTOR              (*(RwReg*)0xF800401CU) /**< \brief (HSMCI2) Completion Signal Timeout Register */
#define REG_HSMCI2_RSPR               (*(RoReg*)0xF8004020U) /**< \brief (HSMCI2) Response Register */
#define REG_HSMCI2_RDR                (*(RoReg*)0xF8004030U) /**< \brief (HSMCI2) Receive Data Register */
#define REG_HSMCI2_TDR                (*(WoReg*)0xF8004034U) /**< \brief (HSMCI2) Transmit Data Register */
#define REG_HSMCI2_SR                 (*(RoReg*)0xF8004040U) /**< \brief (HSMCI2) Status Register */
#define REG_HSMCI2_IER                (*(WoReg*)0xF8004044U) /**< \brief (HSMCI2) Interrupt Enable Register */
#define REG_HSMCI2_IDR                (*(WoReg*)0xF8004048U) /**< \brief (HSMCI2) Interrupt Disable Register */
#define REG_HSMCI2_IMR                (*(RoReg*)0xF800404CU) /**< \brief (HSMCI2) Interrupt Mask Register */
#define REG_HSMCI2_DMA                (*(RwReg*)0xF8004050U) /**< \brief (HSMCI2) DMA Configuration Register */
#define REG_HSMCI2_CFG                (*(RwReg*)0xF8004054U) /**< \brief (HSMCI2) Configuration Register */
#define REG_HSMCI2_WPMR               (*(RwReg*)0xF80040E4U) /**< \brief (HSMCI2) Write Protection Mode Register */
#define REG_HSMCI2_WPSR               (*(RoReg*)0xF80040E8U) /**< \brief (HSMCI2) Write Protection Status Register */
#define REG_HSMCI2_FIFO               (*(RwReg*)0xF8004200U) /**< \brief (HSMCI2) FIFO Memory Aperture0 */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for SPI1 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_SPI1_CR                            (0xF8008000U) /**< \brief (SPI1) Control Register */
#define REG_SPI1_MR                            (0xF8008004U) /**< \brief (SPI1) Mode Register */
#define REG_SPI1_RDR                           (0xF8008008U) /**< \brief (SPI1) Receive Data Register */
#define REG_SPI1_TDR                           (0xF800800CU) /**< \brief (SPI1) Transmit Data Register */
#define REG_SPI1_SR                            (0xF8008010U) /**< \brief (SPI1) Status Register */
#define REG_SPI1_IER                           (0xF8008014U) /**< \brief (SPI1) Interrupt Enable Register */
#define REG_SPI1_IDR                           (0xF8008018U) /**< \brief (SPI1) Interrupt Disable Register */
#define REG_SPI1_IMR                           (0xF800801CU) /**< \brief (SPI1) Interrupt Mask Register */
#define REG_SPI1_CSR                           (0xF8008030U) /**< \brief (SPI1) Chip Select Register */
#define REG_SPI1_WPMR                          (0xF80080E4U) /**< \brief (SPI1) Write Protection Control Register */
#define REG_SPI1_WPSR                          (0xF80080E8U) /**< \brief (SPI1) Write Protection Status Register */
#else
#define REG_SPI1_CR                   (*(WoReg*)0xF8008000U) /**< \brief (SPI1) Control Register */
#define REG_SPI1_MR                   (*(RwReg*)0xF8008004U) /**< \brief (SPI1) Mode Register */
#define REG_SPI1_RDR                  (*(RoReg*)0xF8008008U) /**< \brief (SPI1) Receive Data Register */
#define REG_SPI1_TDR                  (*(WoReg*)0xF800800CU) /**< \brief (SPI1) Transmit Data Register */
#define REG_SPI1_SR                   (*(RoReg*)0xF8008010U) /**< \brief (SPI1) Status Register */
#define REG_SPI1_IER                  (*(WoReg*)0xF8008014U) /**< \brief (SPI1) Interrupt Enable Register */
#define REG_SPI1_IDR                  (*(WoReg*)0xF8008018U) /**< \brief (SPI1) Interrupt Disable Register */
#define REG_SPI1_IMR                  (*(RoReg*)0xF800801CU) /**< \brief (SPI1) Interrupt Mask Register */
#define REG_SPI1_CSR                  (*(RwReg*)0xF8008030U) /**< \brief (SPI1) Chip Select Register */
#define REG_SPI1_WPMR                 (*(RwReg*)0xF80080E4U) /**< \brief (SPI1) Write Protection Control Register */
#define REG_SPI1_WPSR                 (*(RoReg*)0xF80080E8U) /**< \brief (SPI1) Write Protection Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for SSC1 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_SSC1_CR                            (0xF800C000U) /**< \brief (SSC1) Control Register */
#define REG_SSC1_CMR                           (0xF800C004U) /**< \brief (SSC1) Clock Mode Register */
#define REG_SSC1_RCMR                          (0xF800C010U) /**< \brief (SSC1) Receive Clock Mode Register */
#define REG_SSC1_RFMR                          (0xF800C014U) /**< \brief (SSC1) Receive Frame Mode Register */
#define REG_SSC1_TCMR                          (0xF800C018U) /**< \brief (SSC1) Transmit Clock Mode Register */
#define REG_SSC1_TFMR                          (0xF800C01CU) /**< \brief (SSC1) Transmit Frame Mode Register */
#define REG_SSC1_RHR                           (0xF800C020U) /**< \brief (SSC1) Receive Holding Register */
#define REG_SSC1_THR                           (0xF800C024U) /**< \brief (SSC1) Transmit Holding Register */
#define REG_SSC1_RSHR                          (0xF800C030U) /**< \brief (SSC1) Receive Sync. Holding Register */
#define REG_SSC1_TSHR                          (0xF800C034U) /**< \brief (SSC1) Transmit Sync. Holding Register */
#define REG_SSC1_RC0R                          (0xF800C038U) /**< \brief (SSC1) Receive Compare 0 Register */
#define REG_SSC1_RC1R                          (0xF800C03CU) /**< \brief (SSC1) Receive Compare 1 Register */
#define REG_SSC1_SR                            (0xF800C040U) /**< \brief (SSC1) Status Register */
#define REG_SSC1_IER                           (0xF800C044U) /**< \brief (SSC1) Interrupt Enable Register */
#define REG_SSC1_IDR                           (0xF800C048U) /**< \brief (SSC1) Interrupt Disable Register */
#define REG_SSC1_IMR                           (0xF800C04CU) /**< \brief (SSC1) Interrupt Mask Register */
#define REG_SSC1_WPMR                          (0xF800C0E4U) /**< \brief (SSC1) Write Protect Mode Register */
#define REG_SSC1_WPSR                          (0xF800C0E8U) /**< \brief (SSC1) Write Protect Status Register */
#else
#define REG_SSC1_CR                   (*(WoReg*)0xF800C000U) /**< \brief (SSC1) Control Register */
#define REG_SSC1_CMR                  (*(RwReg*)0xF800C004U) /**< \brief (SSC1) Clock Mode Register */
#define REG_SSC1_RCMR                 (*(RwReg*)0xF800C010U) /**< \brief (SSC1) Receive Clock Mode Register */
#define REG_SSC1_RFMR                 (*(RwReg*)0xF800C014U) /**< \brief (SSC1) Receive Frame Mode Register */
#define REG_SSC1_TCMR                 (*(RwReg*)0xF800C018U) /**< \brief (SSC1) Transmit Clock Mode Register */
#define REG_SSC1_TFMR                 (*(RwReg*)0xF800C01CU) /**< \brief (SSC1) Transmit Frame Mode Register */
#define REG_SSC1_RHR                  (*(RoReg*)0xF800C020U) /**< \brief (SSC1) Receive Holding Register */
#define REG_SSC1_THR                  (*(WoReg*)0xF800C024U) /**< \brief (SSC1) Transmit Holding Register */
#define REG_SSC1_RSHR                 (*(RoReg*)0xF800C030U) /**< \brief (SSC1) Receive Sync. Holding Register */
#define REG_SSC1_TSHR                 (*(RwReg*)0xF800C034U) /**< \brief (SSC1) Transmit Sync. Holding Register */
#define REG_SSC1_RC0R                 (*(RwReg*)0xF800C038U) /**< \brief (SSC1) Receive Compare 0 Register */
#define REG_SSC1_RC1R                 (*(RwReg*)0xF800C03CU) /**< \brief (SSC1) Receive Compare 1 Register */
#define REG_SSC1_SR                   (*(RoReg*)0xF800C040U) /**< \brief (SSC1) Status Register */
#define REG_SSC1_IER                  (*(WoReg*)0xF800C044U) /**< \brief (SSC1) Interrupt Enable Register */
#define REG_SSC1_IDR                  (*(WoReg*)0xF800C048U) /**< \brief (SSC1) Interrupt Disable Register */
#define REG_SSC1_IMR                  (*(RoReg*)0xF800C04CU) /**< \brief (SSC1) Interrupt Mask Register */
#define REG_SSC1_WPMR                 (*(RwReg*)0xF800C0E4U) /**< \brief (SSC1) Write Protect Mode Register */
#define REG_SSC1_WPSR                 (*(RoReg*)0xF800C0E8U) /**< \brief (SSC1) Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for CAN1 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_CAN1_MR                            (0xF8010000U) /**< \brief (CAN1) Mode Register */
#define REG_CAN1_IER                           (0xF8010004U) /**< \brief (CAN1) Interrupt Enable Register */
#define REG_CAN1_IDR                           (0xF8010008U) /**< \brief (CAN1) Interrupt Disable Register */
#define REG_CAN1_IMR                           (0xF801000CU) /**< \brief (CAN1) Interrupt Mask Register */
#define REG_CAN1_SR                            (0xF8010010U) /**< \brief (CAN1) Status Register */
#define REG_CAN1_BR                            (0xF8010014U) /**< \brief (CAN1) Baudrate Register */
#define REG_CAN1_TIM                           (0xF8010018U) /**< \brief (CAN1) Timer Register */
#define REG_CAN1_TIMESTP                       (0xF801001CU) /**< \brief (CAN1) Timestamp Register */
#define REG_CAN1_ECR                           (0xF8010020U) /**< \brief (CAN1) Error Counter Register */
#define REG_CAN1_TCR                           (0xF8010024U) /**< \brief (CAN1) Transfer Command Register */
#define REG_CAN1_ACR                           (0xF8010028U) /**< \brief (CAN1) Abort Command Register */
#define REG_CAN1_MMR0                          (0xF8010200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */
#define REG_CAN1_MAM0                          (0xF8010204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */
#define REG_CAN1_MID0                          (0xF8010208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */
#define REG_CAN1_MFID0                         (0xF801020CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */
#define REG_CAN1_MSR0                          (0xF8010210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */
#define REG_CAN1_MDL0                          (0xF8010214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */
#define REG_CAN1_MDH0                          (0xF8010218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */
#define REG_CAN1_MCR0                          (0xF801021CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */
#define REG_CAN1_MMR1                          (0xF8010220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */
#define REG_CAN1_MAM1                          (0xF8010224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */
#define REG_CAN1_MID1                          (0xF8010228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */
#define REG_CAN1_MFID1                         (0xF801022CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */
#define REG_CAN1_MSR1                          (0xF8010230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */
#define REG_CAN1_MDL1                          (0xF8010234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */
#define REG_CAN1_MDH1                          (0xF8010238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */
#define REG_CAN1_MCR1                          (0xF801023CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */
#define REG_CAN1_MMR2                          (0xF8010240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */
#define REG_CAN1_MAM2                          (0xF8010244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */
#define REG_CAN1_MID2                          (0xF8010248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */
#define REG_CAN1_MFID2                         (0xF801024CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */
#define REG_CAN1_MSR2                          (0xF8010250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */
#define REG_CAN1_MDL2                          (0xF8010254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */
#define REG_CAN1_MDH2                          (0xF8010258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */
#define REG_CAN1_MCR2                          (0xF801025CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */
#define REG_CAN1_MMR3                          (0xF8010260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */
#define REG_CAN1_MAM3                          (0xF8010264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */
#define REG_CAN1_MID3                          (0xF8010268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */
#define REG_CAN1_MFID3                         (0xF801026CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */
#define REG_CAN1_MSR3                          (0xF8010270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */
#define REG_CAN1_MDL3                          (0xF8010274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */
#define REG_CAN1_MDH3                          (0xF8010278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */
#define REG_CAN1_MCR3                          (0xF801027CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */
#define REG_CAN1_MMR4                          (0xF8010280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */
#define REG_CAN1_MAM4                          (0xF8010284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */
#define REG_CAN1_MID4                          (0xF8010288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */
#define REG_CAN1_MFID4                         (0xF801028CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */
#define REG_CAN1_MSR4                          (0xF8010290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */
#define REG_CAN1_MDL4                          (0xF8010294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */
#define REG_CAN1_MDH4                          (0xF8010298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */
#define REG_CAN1_MCR4                          (0xF801029CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */
#define REG_CAN1_MMR5                          (0xF80102A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */
#define REG_CAN1_MAM5                          (0xF80102A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */
#define REG_CAN1_MID5                          (0xF80102A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */
#define REG_CAN1_MFID5                         (0xF80102ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */
#define REG_CAN1_MSR5                          (0xF80102B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */
#define REG_CAN1_MDL5                          (0xF80102B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */
#define REG_CAN1_MDH5                          (0xF80102B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */
#define REG_CAN1_MCR5                          (0xF80102BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */
#define REG_CAN1_MMR6                          (0xF80102C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */
#define REG_CAN1_MAM6                          (0xF80102C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */
#define REG_CAN1_MID6                          (0xF80102C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */
#define REG_CAN1_MFID6                         (0xF80102CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */
#define REG_CAN1_MSR6                          (0xF80102D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */
#define REG_CAN1_MDL6                          (0xF80102D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */
#define REG_CAN1_MDH6                          (0xF80102D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */
#define REG_CAN1_MCR6                          (0xF80102DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */
#define REG_CAN1_MMR7                          (0xF80102E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */
#define REG_CAN1_MAM7                          (0xF80102E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */
#define REG_CAN1_MID7                          (0xF80102E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */
#define REG_CAN1_MFID7                         (0xF80102ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */
#define REG_CAN1_MSR7                          (0xF80102F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */
#define REG_CAN1_MDL7                          (0xF80102F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */
#define REG_CAN1_MDH7                          (0xF80102F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */
#define REG_CAN1_MCR7                          (0xF80102FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */
#else
#define REG_CAN1_MR                   (*(RwReg*)0xF8010000U) /**< \brief (CAN1) Mode Register */
#define REG_CAN1_IER                  (*(WoReg*)0xF8010004U) /**< \brief (CAN1) Interrupt Enable Register */
#define REG_CAN1_IDR                  (*(WoReg*)0xF8010008U) /**< \brief (CAN1) Interrupt Disable Register */
#define REG_CAN1_IMR                  (*(RoReg*)0xF801000CU) /**< \brief (CAN1) Interrupt Mask Register */
#define REG_CAN1_SR                   (*(RoReg*)0xF8010010U) /**< \brief (CAN1) Status Register */
#define REG_CAN1_BR                   (*(RwReg*)0xF8010014U) /**< \brief (CAN1) Baudrate Register */
#define REG_CAN1_TIM                  (*(RoReg*)0xF8010018U) /**< \brief (CAN1) Timer Register */
#define REG_CAN1_TIMESTP              (*(RoReg*)0xF801001CU) /**< \brief (CAN1) Timestamp Register */
#define REG_CAN1_ECR                  (*(RoReg*)0xF8010020U) /**< \brief (CAN1) Error Counter Register */
#define REG_CAN1_TCR                  (*(WoReg*)0xF8010024U) /**< \brief (CAN1) Transfer Command Register */
#define REG_CAN1_ACR                  (*(WoReg*)0xF8010028U) /**< \brief (CAN1) Abort Command Register */
#define REG_CAN1_MMR0                 (*(RwReg*)0xF8010200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */
#define REG_CAN1_MAM0                 (*(RwReg*)0xF8010204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */
#define REG_CAN1_MID0                 (*(RwReg*)0xF8010208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */
#define REG_CAN1_MFID0                (*(RoReg*)0xF801020CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */
#define REG_CAN1_MSR0                 (*(RoReg*)0xF8010210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */
#define REG_CAN1_MDL0                 (*(RwReg*)0xF8010214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */
#define REG_CAN1_MDH0                 (*(RwReg*)0xF8010218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */
#define REG_CAN1_MCR0                 (*(WoReg*)0xF801021CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */
#define REG_CAN1_MMR1                 (*(RwReg*)0xF8010220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */
#define REG_CAN1_MAM1                 (*(RwReg*)0xF8010224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */
#define REG_CAN1_MID1                 (*(RwReg*)0xF8010228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */
#define REG_CAN1_MFID1                (*(RoReg*)0xF801022CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */
#define REG_CAN1_MSR1                 (*(RoReg*)0xF8010230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */
#define REG_CAN1_MDL1                 (*(RwReg*)0xF8010234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */
#define REG_CAN1_MDH1                 (*(RwReg*)0xF8010238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */
#define REG_CAN1_MCR1                 (*(WoReg*)0xF801023CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */
#define REG_CAN1_MMR2                 (*(RwReg*)0xF8010240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */
#define REG_CAN1_MAM2                 (*(RwReg*)0xF8010244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */
#define REG_CAN1_MID2                 (*(RwReg*)0xF8010248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */
#define REG_CAN1_MFID2                (*(RoReg*)0xF801024CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */
#define REG_CAN1_MSR2                 (*(RoReg*)0xF8010250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */
#define REG_CAN1_MDL2                 (*(RwReg*)0xF8010254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */
#define REG_CAN1_MDH2                 (*(RwReg*)0xF8010258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */
#define REG_CAN1_MCR2                 (*(WoReg*)0xF801025CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */
#define REG_CAN1_MMR3                 (*(RwReg*)0xF8010260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */
#define REG_CAN1_MAM3                 (*(RwReg*)0xF8010264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */
#define REG_CAN1_MID3                 (*(RwReg*)0xF8010268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */
#define REG_CAN1_MFID3                (*(RoReg*)0xF801026CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */
#define REG_CAN1_MSR3                 (*(RoReg*)0xF8010270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */
#define REG_CAN1_MDL3                 (*(RwReg*)0xF8010274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */
#define REG_CAN1_MDH3                 (*(RwReg*)0xF8010278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */
#define REG_CAN1_MCR3                 (*(WoReg*)0xF801027CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */
#define REG_CAN1_MMR4                 (*(RwReg*)0xF8010280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */
#define REG_CAN1_MAM4                 (*(RwReg*)0xF8010284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */
#define REG_CAN1_MID4                 (*(RwReg*)0xF8010288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */
#define REG_CAN1_MFID4                (*(RoReg*)0xF801028CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */
#define REG_CAN1_MSR4                 (*(RoReg*)0xF8010290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */
#define REG_CAN1_MDL4                 (*(RwReg*)0xF8010294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */
#define REG_CAN1_MDH4                 (*(RwReg*)0xF8010298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */
#define REG_CAN1_MCR4                 (*(WoReg*)0xF801029CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */
#define REG_CAN1_MMR5                 (*(RwReg*)0xF80102A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */
#define REG_CAN1_MAM5                 (*(RwReg*)0xF80102A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */
#define REG_CAN1_MID5                 (*(RwReg*)0xF80102A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */
#define REG_CAN1_MFID5                (*(RoReg*)0xF80102ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */
#define REG_CAN1_MSR5                 (*(RoReg*)0xF80102B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */
#define REG_CAN1_MDL5                 (*(RwReg*)0xF80102B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */
#define REG_CAN1_MDH5                 (*(RwReg*)0xF80102B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */
#define REG_CAN1_MCR5                 (*(WoReg*)0xF80102BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */
#define REG_CAN1_MMR6                 (*(RwReg*)0xF80102C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */
#define REG_CAN1_MAM6                 (*(RwReg*)0xF80102C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */
#define REG_CAN1_MID6                 (*(RwReg*)0xF80102C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */
#define REG_CAN1_MFID6                (*(RoReg*)0xF80102CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */
#define REG_CAN1_MSR6                 (*(RoReg*)0xF80102D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */
#define REG_CAN1_MDL6                 (*(RwReg*)0xF80102D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */
#define REG_CAN1_MDH6                 (*(RwReg*)0xF80102D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */
#define REG_CAN1_MCR6                 (*(WoReg*)0xF80102DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */
#define REG_CAN1_MMR7                 (*(RwReg*)0xF80102E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */
#define REG_CAN1_MAM7                 (*(RwReg*)0xF80102E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */
#define REG_CAN1_MID7                 (*(RwReg*)0xF80102E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */
#define REG_CAN1_MFID7                (*(RoReg*)0xF80102ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */
#define REG_CAN1_MSR7                 (*(RoReg*)0xF80102F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */
#define REG_CAN1_MDL7                 (*(RwReg*)0xF80102F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */
#define REG_CAN1_MDH7                 (*(RwReg*)0xF80102F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */
#define REG_CAN1_MCR7                 (*(WoReg*)0xF80102FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for TC1 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_TC1_CCR0                           (0xF8014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
#define REG_TC1_CMR0                           (0xF8014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
#define REG_TC1_SMMR0                          (0xF8014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
#define REG_TC1_RAB0                           (0xF801400CU) /**< \brief (TC1) Register AB (channel = 0) */
#define REG_TC1_CV0                            (0xF8014010U) /**< \brief (TC1) Counter Value (channel = 0) */
#define REG_TC1_RA0                            (0xF8014014U) /**< \brief (TC1) Register A (channel = 0) */
#define REG_TC1_RB0                            (0xF8014018U) /**< \brief (TC1) Register B (channel = 0) */
#define REG_TC1_RC0                            (0xF801401CU) /**< \brief (TC1) Register C (channel = 0) */
#define REG_TC1_SR0                            (0xF8014020U) /**< \brief (TC1) Status Register (channel = 0) */
#define REG_TC1_IER0                           (0xF8014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
#define REG_TC1_IDR0                           (0xF8014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
#define REG_TC1_IMR0                           (0xF801402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
#define REG_TC1_CCR1                           (0xF8014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
#define REG_TC1_CMR1                           (0xF8014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
#define REG_TC1_SMMR1                          (0xF8014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
#define REG_TC1_RAB1                           (0xF801404CU) /**< \brief (TC1) Register AB (channel = 1) */
#define REG_TC1_CV1                            (0xF8014050U) /**< \brief (TC1) Counter Value (channel = 1) */
#define REG_TC1_RA1                            (0xF8014054U) /**< \brief (TC1) Register A (channel = 1) */
#define REG_TC1_RB1                            (0xF8014058U) /**< \brief (TC1) Register B (channel = 1) */
#define REG_TC1_RC1                            (0xF801405CU) /**< \brief (TC1) Register C (channel = 1) */
#define REG_TC1_SR1                            (0xF8014060U) /**< \brief (TC1) Status Register (channel = 1) */
#define REG_TC1_IER1                           (0xF8014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
#define REG_TC1_IDR1                           (0xF8014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
#define REG_TC1_IMR1                           (0xF801406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
#define REG_TC1_CCR2                           (0xF8014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
#define REG_TC1_CMR2                           (0xF8014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
#define REG_TC1_SMMR2                          (0xF8014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
#define REG_TC1_RAB2                           (0xF801408CU) /**< \brief (TC1) Register AB (channel = 2) */
#define REG_TC1_CV2                            (0xF8014090U) /**< \brief (TC1) Counter Value (channel = 2) */
#define REG_TC1_RA2                            (0xF8014094U) /**< \brief (TC1) Register A (channel = 2) */
#define REG_TC1_RB2                            (0xF8014098U) /**< \brief (TC1) Register B (channel = 2) */
#define REG_TC1_RC2                            (0xF801409CU) /**< \brief (TC1) Register C (channel = 2) */
#define REG_TC1_SR2                            (0xF80140A0U) /**< \brief (TC1) Status Register (channel = 2) */
#define REG_TC1_IER2                           (0xF80140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
#define REG_TC1_IDR2                           (0xF80140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
#define REG_TC1_IMR2                           (0xF80140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
#define REG_TC1_BCR                            (0xF80140C0U) /**< \brief (TC1) Block Control Register */
#define REG_TC1_BMR                            (0xF80140C4U) /**< \brief (TC1) Block Mode Register */
#define REG_TC1_WPMR                           (0xF80140E4U) /**< \brief (TC1) Write Protect Mode Register */
#else
#define REG_TC1_CCR0                  (*(WoReg*)0xF8014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
#define REG_TC1_CMR0                  (*(RwReg*)0xF8014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
#define REG_TC1_SMMR0                 (*(RwReg*)0xF8014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
#define REG_TC1_RAB0                  (*(RoReg*)0xF801400CU) /**< \brief (TC1) Register AB (channel = 0) */
#define REG_TC1_CV0                   (*(RoReg*)0xF8014010U) /**< \brief (TC1) Counter Value (channel = 0) */
#define REG_TC1_RA0                   (*(RwReg*)0xF8014014U) /**< \brief (TC1) Register A (channel = 0) */
#define REG_TC1_RB0                   (*(RwReg*)0xF8014018U) /**< \brief (TC1) Register B (channel = 0) */
#define REG_TC1_RC0                   (*(RwReg*)0xF801401CU) /**< \brief (TC1) Register C (channel = 0) */
#define REG_TC1_SR0                   (*(RoReg*)0xF8014020U) /**< \brief (TC1) Status Register (channel = 0) */
#define REG_TC1_IER0                  (*(WoReg*)0xF8014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
#define REG_TC1_IDR0                  (*(WoReg*)0xF8014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
#define REG_TC1_IMR0                  (*(RoReg*)0xF801402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
#define REG_TC1_CCR1                  (*(WoReg*)0xF8014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
#define REG_TC1_CMR1                  (*(RwReg*)0xF8014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
#define REG_TC1_SMMR1                 (*(RwReg*)0xF8014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
#define REG_TC1_RAB1                  (*(RoReg*)0xF801404CU) /**< \brief (TC1) Register AB (channel = 1) */
#define REG_TC1_CV1                   (*(RoReg*)0xF8014050U) /**< \brief (TC1) Counter Value (channel = 1) */
#define REG_TC1_RA1                   (*(RwReg*)0xF8014054U) /**< \brief (TC1) Register A (channel = 1) */
#define REG_TC1_RB1                   (*(RwReg*)0xF8014058U) /**< \brief (TC1) Register B (channel = 1) */
#define REG_TC1_RC1                   (*(RwReg*)0xF801405CU) /**< \brief (TC1) Register C (channel = 1) */
#define REG_TC1_SR1                   (*(RoReg*)0xF8014060U) /**< \brief (TC1) Status Register (channel = 1) */
#define REG_TC1_IER1                  (*(WoReg*)0xF8014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
#define REG_TC1_IDR1                  (*(WoReg*)0xF8014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
#define REG_TC1_IMR1                  (*(RoReg*)0xF801406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
#define REG_TC1_CCR2                  (*(WoReg*)0xF8014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
#define REG_TC1_CMR2                  (*(RwReg*)0xF8014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
#define REG_TC1_SMMR2                 (*(RwReg*)0xF8014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
#define REG_TC1_RAB2                  (*(RoReg*)0xF801408CU) /**< \brief (TC1) Register AB (channel = 2) */
#define REG_TC1_CV2                   (*(RoReg*)0xF8014090U) /**< \brief (TC1) Counter Value (channel = 2) */
#define REG_TC1_RA2                   (*(RwReg*)0xF8014094U) /**< \brief (TC1) Register A (channel = 2) */
#define REG_TC1_RB2                   (*(RwReg*)0xF8014098U) /**< \brief (TC1) Register B (channel = 2) */
#define REG_TC1_RC2                   (*(RwReg*)0xF801409CU) /**< \brief (TC1) Register C (channel = 2) */
#define REG_TC1_SR2                   (*(RoReg*)0xF80140A0U) /**< \brief (TC1) Status Register (channel = 2) */
#define REG_TC1_IER2                  (*(WoReg*)0xF80140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
#define REG_TC1_IDR2                  (*(WoReg*)0xF80140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
#define REG_TC1_IMR2                  (*(RoReg*)0xF80140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
#define REG_TC1_BCR                   (*(WoReg*)0xF80140C0U) /**< \brief (TC1) Block Control Register */
#define REG_TC1_BMR                   (*(RwReg*)0xF80140C4U) /**< \brief (TC1) Block Mode Register */
#define REG_TC1_WPMR                  (*(RwReg*)0xF80140E4U) /**< \brief (TC1) Write Protect Mode Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for ADC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_ADC_CR                             (0xF8018000U) /**< \brief (ADC) Control Register */
#define REG_ADC_MR                             (0xF8018004U) /**< \brief (ADC) Mode Register */
#define REG_ADC_SEQR1                          (0xF8018008U) /**< \brief (ADC) Channel Sequence Register 1 */
#define REG_ADC_SEQR2                          (0xF801800CU) /**< \brief (ADC) Channel Sequence Register 2 */
#define REG_ADC_CHER                           (0xF8018010U) /**< \brief (ADC) Channel Enable Register */
#define REG_ADC_CHDR                           (0xF8018014U) /**< \brief (ADC) Channel Disable Register */
#define REG_ADC_CHSR                           (0xF8018018U) /**< \brief (ADC) Channel Status Register */
#define REG_ADC_LCDR                           (0xF8018020U) /**< \brief (ADC) Last Converted Data Register */
#define REG_ADC_IER                            (0xF8018024U) /**< \brief (ADC) Interrupt Enable Register */
#define REG_ADC_IDR                            (0xF8018028U) /**< \brief (ADC) Interrupt Disable Register */
#define REG_ADC_IMR                            (0xF801802CU) /**< \brief (ADC) Interrupt Mask Register */
#define REG_ADC_ISR                            (0xF8018030U) /**< \brief (ADC) Interrupt Status Register */
#define REG_ADC_OVER                           (0xF801803CU) /**< \brief (ADC) Overrun Status Register */
#define REG_ADC_EMR                            (0xF8018040U) /**< \brief (ADC) Extended Mode Register */
#define REG_ADC_CWR                            (0xF8018044U) /**< \brief (ADC) Compare Window Register */
#define REG_ADC_CGR                            (0xF8018048U) /**< \brief (ADC) Channel Gain Register */
#define REG_ADC_COR                            (0xF801804CU) /**< \brief (ADC) Channel Offset Register */
#define REG_ADC_CDR                            (0xF8018050U) /**< \brief (ADC) Channel Data Register */
#define REG_ADC_ACR                            (0xF8018094U) /**< \brief (ADC) Analog Control Register */
#define REG_ADC_TSMR                           (0xF80180B0U) /**< \brief (ADC) Touchscreen Mode Register */
#define REG_ADC_XPOSR                          (0xF80180B4U) /**< \brief (ADC) Touchscreen X Position Register */
#define REG_ADC_YPOSR                          (0xF80180B8U) /**< \brief (ADC) Touchscreen Y Position Register */
#define REG_ADC_PRESSR                         (0xF80180BCU) /**< \brief (ADC) Touchscreen Pressure Register */
#define REG_ADC_TRGR                           (0xF80180C0U) /**< \brief (ADC) Trigger Register */
#define REG_ADC_WPMR                           (0xF80180E4U) /**< \brief (ADC) Write Protect Mode Register */
#define REG_ADC_WPSR                           (0xF80180E8U) /**< \brief (ADC) Write Protect Status Register */
#else
#define REG_ADC_CR                    (*(WoReg*)0xF8018000U) /**< \brief (ADC) Control Register */
#define REG_ADC_MR                    (*(RwReg*)0xF8018004U) /**< \brief (ADC) Mode Register */
#define REG_ADC_SEQR1                 (*(RwReg*)0xF8018008U) /**< \brief (ADC) Channel Sequence Register 1 */
#define REG_ADC_SEQR2                 (*(RwReg*)0xF801800CU) /**< \brief (ADC) Channel Sequence Register 2 */
#define REG_ADC_CHER                  (*(WoReg*)0xF8018010U) /**< \brief (ADC) Channel Enable Register */
#define REG_ADC_CHDR                  (*(WoReg*)0xF8018014U) /**< \brief (ADC) Channel Disable Register */
#define REG_ADC_CHSR                  (*(RoReg*)0xF8018018U) /**< \brief (ADC) Channel Status Register */
#define REG_ADC_LCDR                  (*(RoReg*)0xF8018020U) /**< \brief (ADC) Last Converted Data Register */
#define REG_ADC_IER                   (*(WoReg*)0xF8018024U) /**< \brief (ADC) Interrupt Enable Register */
#define REG_ADC_IDR                   (*(WoReg*)0xF8018028U) /**< \brief (ADC) Interrupt Disable Register */
#define REG_ADC_IMR                   (*(RoReg*)0xF801802CU) /**< \brief (ADC) Interrupt Mask Register */
#define REG_ADC_ISR                   (*(RoReg*)0xF8018030U) /**< \brief (ADC) Interrupt Status Register */
#define REG_ADC_OVER                  (*(RoReg*)0xF801803CU) /**< \brief (ADC) Overrun Status Register */
#define REG_ADC_EMR                   (*(RwReg*)0xF8018040U) /**< \brief (ADC) Extended Mode Register */
#define REG_ADC_CWR                   (*(RwReg*)0xF8018044U) /**< \brief (ADC) Compare Window Register */
#define REG_ADC_CGR                   (*(RwReg*)0xF8018048U) /**< \brief (ADC) Channel Gain Register */
#define REG_ADC_COR                   (*(RwReg*)0xF801804CU) /**< \brief (ADC) Channel Offset Register */
#define REG_ADC_CDR                   (*(RoReg*)0xF8018050U) /**< \brief (ADC) Channel Data Register */
#define REG_ADC_ACR                   (*(RwReg*)0xF8018094U) /**< \brief (ADC) Analog Control Register */
#define REG_ADC_TSMR                  (*(RwReg*)0xF80180B0U) /**< \brief (ADC) Touchscreen Mode Register */
#define REG_ADC_XPOSR                 (*(RoReg*)0xF80180B4U) /**< \brief (ADC) Touchscreen X Position Register */
#define REG_ADC_YPOSR                 (*(RoReg*)0xF80180B8U) /**< \brief (ADC) Touchscreen Y Position Register */
#define REG_ADC_PRESSR                (*(RoReg*)0xF80180BCU) /**< \brief (ADC) Touchscreen Pressure Register */
#define REG_ADC_TRGR                  (*(RwReg*)0xF80180C0U) /**< \brief (ADC) Trigger Register */
#define REG_ADC_WPMR                  (*(RwReg*)0xF80180E4U) /**< \brief (ADC) Write Protect Mode Register */
#define REG_ADC_WPSR                  (*(RoReg*)0xF80180E8U) /**< \brief (ADC) Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for TWI2 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_TWI2_CR                            (0xF801C000U) /**< \brief (TWI2) Control Register */
#define REG_TWI2_MMR                           (0xF801C004U) /**< \brief (TWI2) Master Mode Register */
#define REG_TWI2_SMR                           (0xF801C008U) /**< \brief (TWI2) Slave Mode Register */
#define REG_TWI2_IADR                          (0xF801C00CU) /**< \brief (TWI2) Internal Address Register */
#define REG_TWI2_CWGR                          (0xF801C010U) /**< \brief (TWI2) Clock Waveform Generator Register */
#define REG_TWI2_SR                            (0xF801C020U) /**< \brief (TWI2) Status Register */
#define REG_TWI2_IER                           (0xF801C024U) /**< \brief (TWI2) Interrupt Enable Register */
#define REG_TWI2_IDR                           (0xF801C028U) /**< \brief (TWI2) Interrupt Disable Register */
#define REG_TWI2_IMR                           (0xF801C02CU) /**< \brief (TWI2) Interrupt Mask Register */
#define REG_TWI2_RHR                           (0xF801C030U) /**< \brief (TWI2) Receive Holding Register */
#define REG_TWI2_THR                           (0xF801C034U) /**< \brief (TWI2) Transmit Holding Register */
#define REG_TWI2_WPROT_MODE                    (0xF801C0E4U) /**< \brief (TWI2) Protection Mode Register */
#define REG_TWI2_WPROT_STATUS                  (0xF801C0E8U) /**< \brief (TWI2) Protection Status Register */
#else
#define REG_TWI2_CR                   (*(WoReg*)0xF801C000U) /**< \brief (TWI2) Control Register */
#define REG_TWI2_MMR                  (*(RwReg*)0xF801C004U) /**< \brief (TWI2) Master Mode Register */
#define REG_TWI2_SMR                  (*(RwReg*)0xF801C008U) /**< \brief (TWI2) Slave Mode Register */
#define REG_TWI2_IADR                 (*(RwReg*)0xF801C00CU) /**< \brief (TWI2) Internal Address Register */
#define REG_TWI2_CWGR                 (*(RwReg*)0xF801C010U) /**< \brief (TWI2) Clock Waveform Generator Register */
#define REG_TWI2_SR                   (*(RoReg*)0xF801C020U) /**< \brief (TWI2) Status Register */
#define REG_TWI2_IER                  (*(WoReg*)0xF801C024U) /**< \brief (TWI2) Interrupt Enable Register */
#define REG_TWI2_IDR                  (*(WoReg*)0xF801C028U) /**< \brief (TWI2) Interrupt Disable Register */
#define REG_TWI2_IMR                  (*(RoReg*)0xF801C02CU) /**< \brief (TWI2) Interrupt Mask Register */
#define REG_TWI2_RHR                  (*(RoReg*)0xF801C030U) /**< \brief (TWI2) Receive Holding Register */
#define REG_TWI2_THR                  (*(WoReg*)0xF801C034U) /**< \brief (TWI2) Transmit Holding Register */
#define REG_TWI2_WPROT_MODE           (*(RwReg*)0xF801C0E4U) /**< \brief (TWI2) Protection Mode Register */
#define REG_TWI2_WPROT_STATUS         (*(RoReg*)0xF801C0E8U) /**< \brief (TWI2) Protection Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for USART2 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_USART2_CR                          (0xF8020000U) /**< \brief (USART2) Control Register */
#define REG_USART2_MR                          (0xF8020004U) /**< \brief (USART2) Mode Register */
#define REG_USART2_IER                         (0xF8020008U) /**< \brief (USART2) Interrupt Enable Register */
#define REG_USART2_IDR                         (0xF802000CU) /**< \brief (USART2) Interrupt Disable Register */
#define REG_USART2_IMR                         (0xF8020010U) /**< \brief (USART2) Interrupt Mask Register */
#define REG_USART2_CSR                         (0xF8020014U) /**< \brief (USART2) Channel Status Register */
#define REG_USART2_RHR                         (0xF8020018U) /**< \brief (USART2) Receiver Holding Register */
#define REG_USART2_THR                         (0xF802001CU) /**< \brief (USART2) Transmitter Holding Register */
#define REG_USART2_BRGR                        (0xF8020020U) /**< \brief (USART2) Baud Rate Generator Register */
#define REG_USART2_RTOR                        (0xF8020024U) /**< \brief (USART2) Receiver Time-out Register */
#define REG_USART2_TTGR                        (0xF8020028U) /**< \brief (USART2) Transmitter Timeguard Register */
#define REG_USART2_FIDI                        (0xF8020040U) /**< \brief (USART2) FI DI Ratio Register */
#define REG_USART2_NER                         (0xF8020044U) /**< \brief (USART2) Number of Errors Register */
#define REG_USART2_IF                          (0xF802004CU) /**< \brief (USART2) IrDA Filter Register */
#define REG_USART2_MAN                         (0xF8020050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
#define REG_USART2_WPMR                        (0xF80200E4U) /**< \brief (USART2) Write Protect Mode Register */
#define REG_USART2_WPSR                        (0xF80200E8U) /**< \brief (USART2) Write Protect Status Register */
#else
#define REG_USART2_CR                 (*(WoReg*)0xF8020000U) /**< \brief (USART2) Control Register */
#define REG_USART2_MR                 (*(RwReg*)0xF8020004U) /**< \brief (USART2) Mode Register */
#define REG_USART2_IER                (*(WoReg*)0xF8020008U) /**< \brief (USART2) Interrupt Enable Register */
#define REG_USART2_IDR                (*(WoReg*)0xF802000CU) /**< \brief (USART2) Interrupt Disable Register */
#define REG_USART2_IMR                (*(RoReg*)0xF8020010U) /**< \brief (USART2) Interrupt Mask Register */
#define REG_USART2_CSR                (*(RoReg*)0xF8020014U) /**< \brief (USART2) Channel Status Register */
#define REG_USART2_RHR                (*(RoReg*)0xF8020018U) /**< \brief (USART2) Receiver Holding Register */
#define REG_USART2_THR                (*(WoReg*)0xF802001CU) /**< \brief (USART2) Transmitter Holding Register */
#define REG_USART2_BRGR               (*(RwReg*)0xF8020020U) /**< \brief (USART2) Baud Rate Generator Register */
#define REG_USART2_RTOR               (*(RwReg*)0xF8020024U) /**< \brief (USART2) Receiver Time-out Register */
#define REG_USART2_TTGR               (*(RwReg*)0xF8020028U) /**< \brief (USART2) Transmitter Timeguard Register */
#define REG_USART2_FIDI               (*(RwReg*)0xF8020040U) /**< \brief (USART2) FI DI Ratio Register */
#define REG_USART2_NER                (*(RoReg*)0xF8020044U) /**< \brief (USART2) Number of Errors Register */
#define REG_USART2_IF                 (*(RwReg*)0xF802004CU) /**< \brief (USART2) IrDA Filter Register */
#define REG_USART2_MAN                (*(RwReg*)0xF8020050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
#define REG_USART2_WPMR               (*(RwReg*)0xF80200E4U) /**< \brief (USART2) Write Protect Mode Register */
#define REG_USART2_WPSR               (*(RoReg*)0xF80200E8U) /**< \brief (USART2) Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for USART3 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_USART3_CR                          (0xF8024000U) /**< \brief (USART3) Control Register */
#define REG_USART3_MR                          (0xF8024004U) /**< \brief (USART3) Mode Register */
#define REG_USART3_IER                         (0xF8024008U) /**< \brief (USART3) Interrupt Enable Register */
#define REG_USART3_IDR                         (0xF802400CU) /**< \brief (USART3) Interrupt Disable Register */
#define REG_USART3_IMR                         (0xF8024010U) /**< \brief (USART3) Interrupt Mask Register */
#define REG_USART3_CSR                         (0xF8024014U) /**< \brief (USART3) Channel Status Register */
#define REG_USART3_RHR                         (0xF8024018U) /**< \brief (USART3) Receiver Holding Register */
#define REG_USART3_THR                         (0xF802401CU) /**< \brief (USART3) Transmitter Holding Register */
#define REG_USART3_BRGR                        (0xF8024020U) /**< \brief (USART3) Baud Rate Generator Register */
#define REG_USART3_RTOR                        (0xF8024024U) /**< \brief (USART3) Receiver Time-out Register */
#define REG_USART3_TTGR                        (0xF8024028U) /**< \brief (USART3) Transmitter Timeguard Register */
#define REG_USART3_FIDI                        (0xF8024040U) /**< \brief (USART3) FI DI Ratio Register */
#define REG_USART3_NER                         (0xF8024044U) /**< \brief (USART3) Number of Errors Register */
#define REG_USART3_IF                          (0xF802404CU) /**< \brief (USART3) IrDA Filter Register */
#define REG_USART3_MAN                         (0xF8024050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
#define REG_USART3_WPMR                        (0xF80240E4U) /**< \brief (USART3) Write Protect Mode Register */
#define REG_USART3_WPSR                        (0xF80240E8U) /**< \brief (USART3) Write Protect Status Register */
#else
#define REG_USART3_CR                 (*(WoReg*)0xF8024000U) /**< \brief (USART3) Control Register */
#define REG_USART3_MR                 (*(RwReg*)0xF8024004U) /**< \brief (USART3) Mode Register */
#define REG_USART3_IER                (*(WoReg*)0xF8024008U) /**< \brief (USART3) Interrupt Enable Register */
#define REG_USART3_IDR                (*(WoReg*)0xF802400CU) /**< \brief (USART3) Interrupt Disable Register */
#define REG_USART3_IMR                (*(RoReg*)0xF8024010U) /**< \brief (USART3) Interrupt Mask Register */
#define REG_USART3_CSR                (*(RoReg*)0xF8024014U) /**< \brief (USART3) Channel Status Register */
#define REG_USART3_RHR                (*(RoReg*)0xF8024018U) /**< \brief (USART3) Receiver Holding Register */
#define REG_USART3_THR                (*(WoReg*)0xF802401CU) /**< \brief (USART3) Transmitter Holding Register */
#define REG_USART3_BRGR               (*(RwReg*)0xF8024020U) /**< \brief (USART3) Baud Rate Generator Register */
#define REG_USART3_RTOR               (*(RwReg*)0xF8024024U) /**< \brief (USART3) Receiver Time-out Register */
#define REG_USART3_TTGR               (*(RwReg*)0xF8024028U) /**< \brief (USART3) Transmitter Timeguard Register */
#define REG_USART3_FIDI               (*(RwReg*)0xF8024040U) /**< \brief (USART3) FI DI Ratio Register */
#define REG_USART3_NER                (*(RoReg*)0xF8024044U) /**< \brief (USART3) Number of Errors Register */
#define REG_USART3_IF                 (*(RwReg*)0xF802404CU) /**< \brief (USART3) IrDA Filter Register */
#define REG_USART3_MAN                (*(RwReg*)0xF8024050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
#define REG_USART3_WPMR               (*(RwReg*)0xF80240E4U) /**< \brief (USART3) Write Protect Mode Register */
#define REG_USART3_WPSR               (*(RoReg*)0xF80240E8U) /**< \brief (USART3) Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for UART1 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_UART1_CR                           (0xF8028000U) /**< \brief (UART1) Control Register */
#define REG_UART1_MR                           (0xF8028004U) /**< \brief (UART1) Mode Register */
#define REG_UART1_IER                          (0xF8028008U) /**< \brief (UART1) Interrupt Enable Register */
#define REG_UART1_IDR                          (0xF802800CU) /**< \brief (UART1) Interrupt Disable Register */
#define REG_UART1_IMR                          (0xF8028010U) /**< \brief (UART1) Interrupt Mask Register */
#define REG_UART1_SR                           (0xF8028014U) /**< \brief (UART1) Status Register */
#define REG_UART1_RHR                          (0xF8028018U) /**< \brief (UART1) Receive Holding Register */
#define REG_UART1_THR                          (0xF802801CU) /**< \brief (UART1) Transmit Holding Register */
#define REG_UART1_BRGR                         (0xF8028020U) /**< \brief (UART1) Baud Rate Generator Register */
#else
#define REG_UART1_CR                  (*(WoReg*)0xF8028000U) /**< \brief (UART1) Control Register */
#define REG_UART1_MR                  (*(RwReg*)0xF8028004U) /**< \brief (UART1) Mode Register */
#define REG_UART1_IER                 (*(WoReg*)0xF8028008U) /**< \brief (UART1) Interrupt Enable Register */
#define REG_UART1_IDR                 (*(WoReg*)0xF802800CU) /**< \brief (UART1) Interrupt Disable Register */
#define REG_UART1_IMR                 (*(RoReg*)0xF8028010U) /**< \brief (UART1) Interrupt Mask Register */
#define REG_UART1_SR                  (*(RoReg*)0xF8028014U) /**< \brief (UART1) Status Register */
#define REG_UART1_RHR                 (*(RoReg*)0xF8028018U) /**< \brief (UART1) Receive Holding Register */
#define REG_UART1_THR                 (*(WoReg*)0xF802801CU) /**< \brief (UART1) Transmit Holding Register */
#define REG_UART1_BRGR                (*(RwReg*)0xF8028020U) /**< \brief (UART1) Baud Rate Generator Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for EMAC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_EMAC_NCR                           (0xF802C000U) /**< \brief (EMAC) Network Control Register */
#define REG_EMAC_NCFGR                         (0xF802C004U) /**< \brief (EMAC) Network Configuration Register */
#define REG_EMAC_NSR                           (0xF802C008U) /**< \brief (EMAC) Network Status Register */
#define REG_EMAC_TSR                           (0xF802C014U) /**< \brief (EMAC) Transmit Status Register */
#define REG_EMAC_RBQP                          (0xF802C018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */
#define REG_EMAC_TBQP                          (0xF802C01CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */
#define REG_EMAC_RSR                           (0xF802C020U) /**< \brief (EMAC) Receive Status Register */
#define REG_EMAC_ISR                           (0xF802C024U) /**< \brief (EMAC) Interrupt Status Register */
#define REG_EMAC_IER                           (0xF802C028U) /**< \brief (EMAC) Interrupt Enable Register */
#define REG_EMAC_IDR                           (0xF802C02CU) /**< \brief (EMAC) Interrupt Disable Register */
#define REG_EMAC_IMR                           (0xF802C030U) /**< \brief (EMAC) Interrupt Mask Register */
#define REG_EMAC_MAN                           (0xF802C034U) /**< \brief (EMAC) Phy Maintenance Register */
#define REG_EMAC_PTR                           (0xF802C038U) /**< \brief (EMAC) Pause Time Register */
#define REG_EMAC_PFR                           (0xF802C03CU) /**< \brief (EMAC) Pause Frames Received Register */
#define REG_EMAC_FTO                           (0xF802C040U) /**< \brief (EMAC) Frames Transmitted Ok Register */
#define REG_EMAC_SCF                           (0xF802C044U) /**< \brief (EMAC) Single Collision Frames Register */
#define REG_EMAC_MCF                           (0xF802C048U) /**< \brief (EMAC) Multiple Collision Frames Register */
#define REG_EMAC_FRO                           (0xF802C04CU) /**< \brief (EMAC) Frames Received Ok Register */
#define REG_EMAC_FCSE                          (0xF802C050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */
#define REG_EMAC_ALE                           (0xF802C054U) /**< \brief (EMAC) Alignment Errors Register */
#define REG_EMAC_DTF                           (0xF802C058U) /**< \brief (EMAC) Deferred Transmission Frames Register */
#define REG_EMAC_LCOL                          (0xF802C05CU) /**< \brief (EMAC) Late Collisions Register */
#define REG_EMAC_ECOL                          (0xF802C060U) /**< \brief (EMAC) Excessive Collisions Register */
#define REG_EMAC_TUND                          (0xF802C064U) /**< \brief (EMAC) Transmit Underrun Errors Register */
#define REG_EMAC_CSE                           (0xF802C068U) /**< \brief (EMAC) Carrier Sense Errors Register */
#define REG_EMAC_RRE                           (0xF802C06CU) /**< \brief (EMAC) Receive Resource Errors Register */
#define REG_EMAC_ROV                           (0xF802C070U) /**< \brief (EMAC) Receive Overrun Errors Register */
#define REG_EMAC_RSE                           (0xF802C074U) /**< \brief (EMAC) Receive Symbol Errors Register */
#define REG_EMAC_ELE                           (0xF802C078U) /**< \brief (EMAC) Excessive Length Errors Register */
#define REG_EMAC_RJA                           (0xF802C07CU) /**< \brief (EMAC) Receive Jabbers Register */
#define REG_EMAC_USF                           (0xF802C080U) /**< \brief (EMAC) Undersize Frames Register */
#define REG_EMAC_STE                           (0xF802C084U) /**< \brief (EMAC) SQE Test Errors Register */
#define REG_EMAC_RLE                           (0xF802C088U) /**< \brief (EMAC) Received Length Field Mismatch Register */
#define REG_EMAC_HRB                           (0xF802C090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */
#define REG_EMAC_HRT                           (0xF802C094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */
#define REG_EMAC_SA1B                          (0xF802C098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */
#define REG_EMAC_SA1T                          (0xF802C09CU) /**< \brief (EMAC) Specific Address 1 Top Register */
#define REG_EMAC_SA2B                          (0xF802C0A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */
#define REG_EMAC_SA2T                          (0xF802C0A4U) /**< \brief (EMAC) Specific Address 2 Top Register */
#define REG_EMAC_SA3B                          (0xF802C0A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */
#define REG_EMAC_SA3T                          (0xF802C0ACU) /**< \brief (EMAC) Specific Address 3 Top Register */
#define REG_EMAC_SA4B                          (0xF802C0B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */
#define REG_EMAC_SA4T                          (0xF802C0B4U) /**< \brief (EMAC) Specific Address 4 Top Register */
#define REG_EMAC_TID                           (0xF802C0B8U) /**< \brief (EMAC) Type ID Checking Register */
#define REG_EMAC_USRIO                         (0xF802C0C0U) /**< \brief (EMAC) User Input/Output Register */
#else
#define REG_EMAC_NCR                  (*(RwReg*)0xF802C000U) /**< \brief (EMAC) Network Control Register */
#define REG_EMAC_NCFGR                (*(RwReg*)0xF802C004U) /**< \brief (EMAC) Network Configuration Register */
#define REG_EMAC_NSR                  (*(RoReg*)0xF802C008U) /**< \brief (EMAC) Network Status Register */
#define REG_EMAC_TSR                  (*(RwReg*)0xF802C014U) /**< \brief (EMAC) Transmit Status Register */
#define REG_EMAC_RBQP                 (*(RwReg*)0xF802C018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */
#define REG_EMAC_TBQP                 (*(RwReg*)0xF802C01CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */
#define REG_EMAC_RSR                  (*(RwReg*)0xF802C020U) /**< \brief (EMAC) Receive Status Register */
#define REG_EMAC_ISR                  (*(RwReg*)0xF802C024U) /**< \brief (EMAC) Interrupt Status Register */
#define REG_EMAC_IER                  (*(WoReg*)0xF802C028U) /**< \brief (EMAC) Interrupt Enable Register */
#define REG_EMAC_IDR                  (*(WoReg*)0xF802C02CU) /**< \brief (EMAC) Interrupt Disable Register */
#define REG_EMAC_IMR                  (*(RoReg*)0xF802C030U) /**< \brief (EMAC) Interrupt Mask Register */
#define REG_EMAC_MAN                  (*(RwReg*)0xF802C034U) /**< \brief (EMAC) Phy Maintenance Register */
#define REG_EMAC_PTR                  (*(RwReg*)0xF802C038U) /**< \brief (EMAC) Pause Time Register */
#define REG_EMAC_PFR                  (*(RwReg*)0xF802C03CU) /**< \brief (EMAC) Pause Frames Received Register */
#define REG_EMAC_FTO                  (*(RwReg*)0xF802C040U) /**< \brief (EMAC) Frames Transmitted Ok Register */
#define REG_EMAC_SCF                  (*(RwReg*)0xF802C044U) /**< \brief (EMAC) Single Collision Frames Register */
#define REG_EMAC_MCF                  (*(RwReg*)0xF802C048U) /**< \brief (EMAC) Multiple Collision Frames Register */
#define REG_EMAC_FRO                  (*(RwReg*)0xF802C04CU) /**< \brief (EMAC) Frames Received Ok Register */
#define REG_EMAC_FCSE                 (*(RwReg*)0xF802C050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */
#define REG_EMAC_ALE                  (*(RwReg*)0xF802C054U) /**< \brief (EMAC) Alignment Errors Register */
#define REG_EMAC_DTF                  (*(RwReg*)0xF802C058U) /**< \brief (EMAC) Deferred Transmission Frames Register */
#define REG_EMAC_LCOL                 (*(RwReg*)0xF802C05CU) /**< \brief (EMAC) Late Collisions Register */
#define REG_EMAC_ECOL                 (*(RwReg*)0xF802C060U) /**< \brief (EMAC) Excessive Collisions Register */
#define REG_EMAC_TUND                 (*(RwReg*)0xF802C064U) /**< \brief (EMAC) Transmit Underrun Errors Register */
#define REG_EMAC_CSE                  (*(RwReg*)0xF802C068U) /**< \brief (EMAC) Carrier Sense Errors Register */
#define REG_EMAC_RRE                  (*(RwReg*)0xF802C06CU) /**< \brief (EMAC) Receive Resource Errors Register */
#define REG_EMAC_ROV                  (*(RwReg*)0xF802C070U) /**< \brief (EMAC) Receive Overrun Errors Register */
#define REG_EMAC_RSE                  (*(RwReg*)0xF802C074U) /**< \brief (EMAC) Receive Symbol Errors Register */
#define REG_EMAC_ELE                  (*(RwReg*)0xF802C078U) /**< \brief (EMAC) Excessive Length Errors Register */
#define REG_EMAC_RJA                  (*(RwReg*)0xF802C07CU) /**< \brief (EMAC) Receive Jabbers Register */
#define REG_EMAC_USF                  (*(RwReg*)0xF802C080U) /**< \brief (EMAC) Undersize Frames Register */
#define REG_EMAC_STE                  (*(RwReg*)0xF802C084U) /**< \brief (EMAC) SQE Test Errors Register */
#define REG_EMAC_RLE                  (*(RwReg*)0xF802C088U) /**< \brief (EMAC) Received Length Field Mismatch Register */
#define REG_EMAC_HRB                  (*(RwReg*)0xF802C090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */
#define REG_EMAC_HRT                  (*(RwReg*)0xF802C094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */
#define REG_EMAC_SA1B                 (*(RwReg*)0xF802C098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */
#define REG_EMAC_SA1T                 (*(RwReg*)0xF802C09CU) /**< \brief (EMAC) Specific Address 1 Top Register */
#define REG_EMAC_SA2B                 (*(RwReg*)0xF802C0A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */
#define REG_EMAC_SA2T                 (*(RwReg*)0xF802C0A4U) /**< \brief (EMAC) Specific Address 2 Top Register */
#define REG_EMAC_SA3B                 (*(RwReg*)0xF802C0A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */
#define REG_EMAC_SA3T                 (*(RwReg*)0xF802C0ACU) /**< \brief (EMAC) Specific Address 3 Top Register */
#define REG_EMAC_SA4B                 (*(RwReg*)0xF802C0B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */
#define REG_EMAC_SA4T                 (*(RwReg*)0xF802C0B4U) /**< \brief (EMAC) Specific Address 4 Top Register */
#define REG_EMAC_TID                  (*(RwReg*)0xF802C0B8U) /**< \brief (EMAC) Type ID Checking Register */
#define REG_EMAC_USRIO                (*(RwReg*)0xF802C0C0U) /**< \brief (EMAC) User Input/Output Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for UDPHS peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_UDPHS_CTRL                         (0xF8030000U) /**< \brief (UDPHS) UDPHS Control Register */
#define REG_UDPHS_FNUM                         (0xF8030004U) /**< \brief (UDPHS) UDPHS Frame Number Register */
#define REG_UDPHS_IEN                          (0xF8030010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */
#define REG_UDPHS_INTSTA                       (0xF8030014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */
#define REG_UDPHS_CLRINT                       (0xF8030018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */
#define REG_UDPHS_EPTRST                       (0xF803001CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */
#define REG_UDPHS_TST                          (0xF80300E0U) /**< \brief (UDPHS) UDPHS Test Register */
#define REG_UDPHS_IPNAME1                      (0xF80300F0U) /**< \brief (UDPHS) UDPHS Name1 Register */
#define REG_UDPHS_IPNAME2                      (0xF80300F4U) /**< \brief (UDPHS) UDPHS Name2 Register */
#define REG_UDPHS_IPFEATURES                   (0xF80300F8U) /**< \brief (UDPHS) UDPHS Features Register */
#define REG_UDPHS_EPTCFG0                      (0xF8030100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */
#define REG_UDPHS_EPTCTLENB0                   (0xF8030104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */
#define REG_UDPHS_EPTCTLDIS0                   (0xF8030108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */
#define REG_UDPHS_EPTCTL0                      (0xF803010CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */
#define REG_UDPHS_EPTSETSTA0                   (0xF8030114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */
#define REG_UDPHS_EPTCLRSTA0                   (0xF8030118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */
#define REG_UDPHS_EPTSTA0                      (0xF803011CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */
#define REG_UDPHS_EPTCFG1                      (0xF8030120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */
#define REG_UDPHS_EPTCTLENB1                   (0xF8030124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */
#define REG_UDPHS_EPTCTLDIS1                   (0xF8030128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */
#define REG_UDPHS_EPTCTL1                      (0xF803012CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */
#define REG_UDPHS_EPTSETSTA1                   (0xF8030134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */
#define REG_UDPHS_EPTCLRSTA1                   (0xF8030138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */
#define REG_UDPHS_EPTSTA1                      (0xF803013CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */
#define REG_UDPHS_EPTCFG2                      (0xF8030140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */
#define REG_UDPHS_EPTCTLENB2                   (0xF8030144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */
#define REG_UDPHS_EPTCTLDIS2                   (0xF8030148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */
#define REG_UDPHS_EPTCTL2                      (0xF803014CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */
#define REG_UDPHS_EPTSETSTA2                   (0xF8030154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */
#define REG_UDPHS_EPTCLRSTA2                   (0xF8030158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */
#define REG_UDPHS_EPTSTA2                      (0xF803015CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */
#define REG_UDPHS_EPTCFG3                      (0xF8030160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */
#define REG_UDPHS_EPTCTLENB3                   (0xF8030164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */
#define REG_UDPHS_EPTCTLDIS3                   (0xF8030168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */
#define REG_UDPHS_EPTCTL3                      (0xF803016CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */
#define REG_UDPHS_EPTSETSTA3                   (0xF8030174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */
#define REG_UDPHS_EPTCLRSTA3                   (0xF8030178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */
#define REG_UDPHS_EPTSTA3                      (0xF803017CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */
#define REG_UDPHS_EPTCFG4                      (0xF8030180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */
#define REG_UDPHS_EPTCTLENB4                   (0xF8030184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */
#define REG_UDPHS_EPTCTLDIS4                   (0xF8030188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */
#define REG_UDPHS_EPTCTL4                      (0xF803018CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */
#define REG_UDPHS_EPTSETSTA4                   (0xF8030194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */
#define REG_UDPHS_EPTCLRSTA4                   (0xF8030198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */
#define REG_UDPHS_EPTSTA4                      (0xF803019CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */
#define REG_UDPHS_EPTCFG5                      (0xF80301A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */
#define REG_UDPHS_EPTCTLENB5                   (0xF80301A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */
#define REG_UDPHS_EPTCTLDIS5                   (0xF80301A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */
#define REG_UDPHS_EPTCTL5                      (0xF80301ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */
#define REG_UDPHS_EPTSETSTA5                   (0xF80301B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */
#define REG_UDPHS_EPTCLRSTA5                   (0xF80301B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */
#define REG_UDPHS_EPTSTA5                      (0xF80301BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */
#define REG_UDPHS_EPTCFG6                      (0xF80301C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */
#define REG_UDPHS_EPTCTLENB6                   (0xF80301C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */
#define REG_UDPHS_EPTCTLDIS6                   (0xF80301C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */
#define REG_UDPHS_EPTCTL6                      (0xF80301CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */
#define REG_UDPHS_EPTSETSTA6                   (0xF80301D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */
#define REG_UDPHS_EPTCLRSTA6                   (0xF80301D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */
#define REG_UDPHS_EPTSTA6                      (0xF80301DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */
#define REG_UDPHS_EPTCFG7                      (0xF80301E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 7) */
#define REG_UDPHS_EPTCTLENB7                   (0xF80301E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 7) */
#define REG_UDPHS_EPTCTLDIS7                   (0xF80301E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 7) */
#define REG_UDPHS_EPTCTL7                      (0xF80301ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 7) */
#define REG_UDPHS_EPTSETSTA7                   (0xF80301F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 7) */
#define REG_UDPHS_EPTCLRSTA7                   (0xF80301F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 7) */
#define REG_UDPHS_EPTSTA7                      (0xF80301FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 7) */
#define REG_UDPHS_EPTCFG8                      (0xF8030200U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 8) */
#define REG_UDPHS_EPTCTLENB8                   (0xF8030204U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 8) */
#define REG_UDPHS_EPTCTLDIS8                   (0xF8030208U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 8) */
#define REG_UDPHS_EPTCTL8                      (0xF803020CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 8) */
#define REG_UDPHS_EPTSETSTA8                   (0xF8030214U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 8) */
#define REG_UDPHS_EPTCLRSTA8                   (0xF8030218U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 8) */
#define REG_UDPHS_EPTSTA8                      (0xF803021CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 8) */
#define REG_UDPHS_EPTCFG9                      (0xF8030220U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 9) */
#define REG_UDPHS_EPTCTLENB9                   (0xF8030224U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 9) */
#define REG_UDPHS_EPTCTLDIS9                   (0xF8030228U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 9) */
#define REG_UDPHS_EPTCTL9                      (0xF803022CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 9) */
#define REG_UDPHS_EPTSETSTA9                   (0xF8030234U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 9) */
#define REG_UDPHS_EPTCLRSTA9                   (0xF8030238U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 9) */
#define REG_UDPHS_EPTSTA9                      (0xF803023CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 9) */
#define REG_UDPHS_EPTCFG10                     (0xF8030240U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 10) */
#define REG_UDPHS_EPTCTLENB10                  (0xF8030244U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 10) */
#define REG_UDPHS_EPTCTLDIS10                  (0xF8030248U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 10) */
#define REG_UDPHS_EPTCTL10                     (0xF803024CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 10) */
#define REG_UDPHS_EPTSETSTA10                  (0xF8030254U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 10) */
#define REG_UDPHS_EPTCLRSTA10                  (0xF8030258U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 10) */
#define REG_UDPHS_EPTSTA10                     (0xF803025CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 10) */
#define REG_UDPHS_EPTCFG11                     (0xF8030260U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 11) */
#define REG_UDPHS_EPTCTLENB11                  (0xF8030264U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 11) */
#define REG_UDPHS_EPTCTLDIS11                  (0xF8030268U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 11) */
#define REG_UDPHS_EPTCTL11                     (0xF803026CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 11) */
#define REG_UDPHS_EPTSETSTA11                  (0xF8030274U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 11) */
#define REG_UDPHS_EPTCLRSTA11                  (0xF8030278U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 11) */
#define REG_UDPHS_EPTSTA11                     (0xF803027CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 11) */
#define REG_UDPHS_EPTCFG12                     (0xF8030280U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 12) */
#define REG_UDPHS_EPTCTLENB12                  (0xF8030284U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 12) */
#define REG_UDPHS_EPTCTLDIS12                  (0xF8030288U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 12) */
#define REG_UDPHS_EPTCTL12                     (0xF803028CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 12) */
#define REG_UDPHS_EPTSETSTA12                  (0xF8030294U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 12) */
#define REG_UDPHS_EPTCLRSTA12                  (0xF8030298U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 12) */
#define REG_UDPHS_EPTSTA12                     (0xF803029CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 12) */
#define REG_UDPHS_EPTCFG13                     (0xF80302A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 13) */
#define REG_UDPHS_EPTCTLENB13                  (0xF80302A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 13) */
#define REG_UDPHS_EPTCTLDIS13                  (0xF80302A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 13) */
#define REG_UDPHS_EPTCTL13                     (0xF80302ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 13) */
#define REG_UDPHS_EPTSETSTA13                  (0xF80302B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 13) */
#define REG_UDPHS_EPTCLRSTA13                  (0xF80302B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 13) */
#define REG_UDPHS_EPTSTA13                     (0xF80302BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 13) */
#define REG_UDPHS_EPTCFG14                     (0xF80302C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 14) */
#define REG_UDPHS_EPTCTLENB14                  (0xF80302C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 14) */
#define REG_UDPHS_EPTCTLDIS14                  (0xF80302C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 14) */
#define REG_UDPHS_EPTCTL14                     (0xF80302CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 14) */
#define REG_UDPHS_EPTSETSTA14                  (0xF80302D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 14) */
#define REG_UDPHS_EPTCLRSTA14                  (0xF80302D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 14) */
#define REG_UDPHS_EPTSTA14                     (0xF80302DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 14) */
#define REG_UDPHS_EPTCFG15                     (0xF80302E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 15) */
#define REG_UDPHS_EPTCTLENB15                  (0xF80302E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 15) */
#define REG_UDPHS_EPTCTLDIS15                  (0xF80302E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 15) */
#define REG_UDPHS_EPTCTL15                     (0xF80302ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 15) */
#define REG_UDPHS_EPTSETSTA15                  (0xF80302F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 15) */
#define REG_UDPHS_EPTCLRSTA15                  (0xF80302F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 15) */
#define REG_UDPHS_EPTSTA15                     (0xF80302FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 15) */
#define REG_UDPHS_DMANXTDSC0                   (0xF8030300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */
#define REG_UDPHS_DMAADDRESS0                  (0xF8030304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */
#define REG_UDPHS_DMACONTROL0                  (0xF8030308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */
#define REG_UDPHS_DMASTATUS0                   (0xF803030CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */
#define REG_UDPHS_DMANXTDSC1                   (0xF8030310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */
#define REG_UDPHS_DMAADDRESS1                  (0xF8030314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */
#define REG_UDPHS_DMACONTROL1                  (0xF8030318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */
#define REG_UDPHS_DMASTATUS1                   (0xF803031CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */
#define REG_UDPHS_DMANXTDSC2                   (0xF8030320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */
#define REG_UDPHS_DMAADDRESS2                  (0xF8030324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */
#define REG_UDPHS_DMACONTROL2                  (0xF8030328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */
#define REG_UDPHS_DMASTATUS2                   (0xF803032CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */
#define REG_UDPHS_DMANXTDSC3                   (0xF8030330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */
#define REG_UDPHS_DMAADDRESS3                  (0xF8030334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */
#define REG_UDPHS_DMACONTROL3                  (0xF8030338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */
#define REG_UDPHS_DMASTATUS3                   (0xF803033CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */
#define REG_UDPHS_DMANXTDSC4                   (0xF8030340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */
#define REG_UDPHS_DMAADDRESS4                  (0xF8030344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */
#define REG_UDPHS_DMACONTROL4                  (0xF8030348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */
#define REG_UDPHS_DMASTATUS4                   (0xF803034CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */
#define REG_UDPHS_DMANXTDSC5                   (0xF8030350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */
#define REG_UDPHS_DMAADDRESS5                  (0xF8030354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */
#define REG_UDPHS_DMACONTROL5                  (0xF8030358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */
#define REG_UDPHS_DMASTATUS5                   (0xF803035CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */
#define REG_UDPHS_DMANXTDSC6                   (0xF8030360U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 6) */
#define REG_UDPHS_DMAADDRESS6                  (0xF8030364U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 6) */
#define REG_UDPHS_DMACONTROL6                  (0xF8030368U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 6) */
#define REG_UDPHS_DMASTATUS6                   (0xF803036CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 6) */
#else
#define REG_UDPHS_CTRL                (*(RwReg*)0xF8030000U) /**< \brief (UDPHS) UDPHS Control Register */
#define REG_UDPHS_FNUM                (*(RoReg*)0xF8030004U) /**< \brief (UDPHS) UDPHS Frame Number Register */
#define REG_UDPHS_IEN                 (*(RwReg*)0xF8030010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */
#define REG_UDPHS_INTSTA              (*(RoReg*)0xF8030014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */
#define REG_UDPHS_CLRINT              (*(WoReg*)0xF8030018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */
#define REG_UDPHS_EPTRST              (*(WoReg*)0xF803001CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */
#define REG_UDPHS_TST                 (*(RwReg*)0xF80300E0U) /**< \brief (UDPHS) UDPHS Test Register */
#define REG_UDPHS_IPNAME1             (*(RoReg*)0xF80300F0U) /**< \brief (UDPHS) UDPHS Name1 Register */
#define REG_UDPHS_IPNAME2             (*(RoReg*)0xF80300F4U) /**< \brief (UDPHS) UDPHS Name2 Register */
#define REG_UDPHS_IPFEATURES          (*(RoReg*)0xF80300F8U) /**< \brief (UDPHS) UDPHS Features Register */
#define REG_UDPHS_EPTCFG0             (*(RwReg*)0xF8030100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */
#define REG_UDPHS_EPTCTLENB0          (*(WoReg*)0xF8030104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */
#define REG_UDPHS_EPTCTLDIS0          (*(WoReg*)0xF8030108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */
#define REG_UDPHS_EPTCTL0             (*(RoReg*)0xF803010CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */
#define REG_UDPHS_EPTSETSTA0          (*(WoReg*)0xF8030114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */
#define REG_UDPHS_EPTCLRSTA0          (*(WoReg*)0xF8030118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */
#define REG_UDPHS_EPTSTA0             (*(RoReg*)0xF803011CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */
#define REG_UDPHS_EPTCFG1             (*(RwReg*)0xF8030120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */
#define REG_UDPHS_EPTCTLENB1          (*(WoReg*)0xF8030124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */
#define REG_UDPHS_EPTCTLDIS1          (*(WoReg*)0xF8030128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */
#define REG_UDPHS_EPTCTL1             (*(RoReg*)0xF803012CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */
#define REG_UDPHS_EPTSETSTA1          (*(WoReg*)0xF8030134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */
#define REG_UDPHS_EPTCLRSTA1          (*(WoReg*)0xF8030138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */
#define REG_UDPHS_EPTSTA1             (*(RoReg*)0xF803013CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */
#define REG_UDPHS_EPTCFG2             (*(RwReg*)0xF8030140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */
#define REG_UDPHS_EPTCTLENB2          (*(WoReg*)0xF8030144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */
#define REG_UDPHS_EPTCTLDIS2          (*(WoReg*)0xF8030148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */
#define REG_UDPHS_EPTCTL2             (*(RoReg*)0xF803014CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */
#define REG_UDPHS_EPTSETSTA2          (*(WoReg*)0xF8030154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */
#define REG_UDPHS_EPTCLRSTA2          (*(WoReg*)0xF8030158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */
#define REG_UDPHS_EPTSTA2             (*(RoReg*)0xF803015CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */
#define REG_UDPHS_EPTCFG3             (*(RwReg*)0xF8030160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */
#define REG_UDPHS_EPTCTLENB3          (*(WoReg*)0xF8030164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */
#define REG_UDPHS_EPTCTLDIS3          (*(WoReg*)0xF8030168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */
#define REG_UDPHS_EPTCTL3             (*(RoReg*)0xF803016CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */
#define REG_UDPHS_EPTSETSTA3          (*(WoReg*)0xF8030174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */
#define REG_UDPHS_EPTCLRSTA3          (*(WoReg*)0xF8030178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */
#define REG_UDPHS_EPTSTA3             (*(RoReg*)0xF803017CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */
#define REG_UDPHS_EPTCFG4             (*(RwReg*)0xF8030180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */
#define REG_UDPHS_EPTCTLENB4          (*(WoReg*)0xF8030184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */
#define REG_UDPHS_EPTCTLDIS4          (*(WoReg*)0xF8030188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */
#define REG_UDPHS_EPTCTL4             (*(RoReg*)0xF803018CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */
#define REG_UDPHS_EPTSETSTA4          (*(WoReg*)0xF8030194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */
#define REG_UDPHS_EPTCLRSTA4          (*(WoReg*)0xF8030198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */
#define REG_UDPHS_EPTSTA4             (*(RoReg*)0xF803019CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */
#define REG_UDPHS_EPTCFG5             (*(RwReg*)0xF80301A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */
#define REG_UDPHS_EPTCTLENB5          (*(WoReg*)0xF80301A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */
#define REG_UDPHS_EPTCTLDIS5          (*(WoReg*)0xF80301A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */
#define REG_UDPHS_EPTCTL5             (*(RoReg*)0xF80301ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */
#define REG_UDPHS_EPTSETSTA5          (*(WoReg*)0xF80301B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */
#define REG_UDPHS_EPTCLRSTA5          (*(WoReg*)0xF80301B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */
#define REG_UDPHS_EPTSTA5             (*(RoReg*)0xF80301BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */
#define REG_UDPHS_EPTCFG6             (*(RwReg*)0xF80301C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */
#define REG_UDPHS_EPTCTLENB6          (*(WoReg*)0xF80301C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */
#define REG_UDPHS_EPTCTLDIS6          (*(WoReg*)0xF80301C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */
#define REG_UDPHS_EPTCTL6             (*(RoReg*)0xF80301CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */
#define REG_UDPHS_EPTSETSTA6          (*(WoReg*)0xF80301D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */
#define REG_UDPHS_EPTCLRSTA6          (*(WoReg*)0xF80301D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */
#define REG_UDPHS_EPTSTA6             (*(RoReg*)0xF80301DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */
#define REG_UDPHS_EPTCFG7             (*(RwReg*)0xF80301E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 7) */
#define REG_UDPHS_EPTCTLENB7          (*(WoReg*)0xF80301E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 7) */
#define REG_UDPHS_EPTCTLDIS7          (*(WoReg*)0xF80301E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 7) */
#define REG_UDPHS_EPTCTL7             (*(RoReg*)0xF80301ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 7) */
#define REG_UDPHS_EPTSETSTA7          (*(WoReg*)0xF80301F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 7) */
#define REG_UDPHS_EPTCLRSTA7          (*(WoReg*)0xF80301F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 7) */
#define REG_UDPHS_EPTSTA7             (*(RoReg*)0xF80301FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 7) */
#define REG_UDPHS_EPTCFG8             (*(RwReg*)0xF8030200U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 8) */
#define REG_UDPHS_EPTCTLENB8          (*(WoReg*)0xF8030204U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 8) */
#define REG_UDPHS_EPTCTLDIS8          (*(WoReg*)0xF8030208U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 8) */
#define REG_UDPHS_EPTCTL8             (*(RoReg*)0xF803020CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 8) */
#define REG_UDPHS_EPTSETSTA8          (*(WoReg*)0xF8030214U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 8) */
#define REG_UDPHS_EPTCLRSTA8          (*(WoReg*)0xF8030218U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 8) */
#define REG_UDPHS_EPTSTA8             (*(RoReg*)0xF803021CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 8) */
#define REG_UDPHS_EPTCFG9             (*(RwReg*)0xF8030220U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 9) */
#define REG_UDPHS_EPTCTLENB9          (*(WoReg*)0xF8030224U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 9) */
#define REG_UDPHS_EPTCTLDIS9          (*(WoReg*)0xF8030228U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 9) */
#define REG_UDPHS_EPTCTL9             (*(RoReg*)0xF803022CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 9) */
#define REG_UDPHS_EPTSETSTA9          (*(WoReg*)0xF8030234U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 9) */
#define REG_UDPHS_EPTCLRSTA9          (*(WoReg*)0xF8030238U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 9) */
#define REG_UDPHS_EPTSTA9             (*(RoReg*)0xF803023CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 9) */
#define REG_UDPHS_EPTCFG10            (*(RwReg*)0xF8030240U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 10) */
#define REG_UDPHS_EPTCTLENB10         (*(WoReg*)0xF8030244U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 10) */
#define REG_UDPHS_EPTCTLDIS10         (*(WoReg*)0xF8030248U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 10) */
#define REG_UDPHS_EPTCTL10            (*(RoReg*)0xF803024CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 10) */
#define REG_UDPHS_EPTSETSTA10         (*(WoReg*)0xF8030254U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 10) */
#define REG_UDPHS_EPTCLRSTA10         (*(WoReg*)0xF8030258U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 10) */
#define REG_UDPHS_EPTSTA10            (*(RoReg*)0xF803025CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 10) */
#define REG_UDPHS_EPTCFG11            (*(RwReg*)0xF8030260U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 11) */
#define REG_UDPHS_EPTCTLENB11         (*(WoReg*)0xF8030264U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 11) */
#define REG_UDPHS_EPTCTLDIS11         (*(WoReg*)0xF8030268U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 11) */
#define REG_UDPHS_EPTCTL11            (*(RoReg*)0xF803026CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 11) */
#define REG_UDPHS_EPTSETSTA11         (*(WoReg*)0xF8030274U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 11) */
#define REG_UDPHS_EPTCLRSTA11         (*(WoReg*)0xF8030278U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 11) */
#define REG_UDPHS_EPTSTA11            (*(RoReg*)0xF803027CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 11) */
#define REG_UDPHS_EPTCFG12            (*(RwReg*)0xF8030280U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 12) */
#define REG_UDPHS_EPTCTLENB12         (*(WoReg*)0xF8030284U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 12) */
#define REG_UDPHS_EPTCTLDIS12         (*(WoReg*)0xF8030288U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 12) */
#define REG_UDPHS_EPTCTL12            (*(RoReg*)0xF803028CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 12) */
#define REG_UDPHS_EPTSETSTA12         (*(WoReg*)0xF8030294U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 12) */
#define REG_UDPHS_EPTCLRSTA12         (*(WoReg*)0xF8030298U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 12) */
#define REG_UDPHS_EPTSTA12            (*(RoReg*)0xF803029CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 12) */
#define REG_UDPHS_EPTCFG13            (*(RwReg*)0xF80302A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 13) */
#define REG_UDPHS_EPTCTLENB13         (*(WoReg*)0xF80302A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 13) */
#define REG_UDPHS_EPTCTLDIS13         (*(WoReg*)0xF80302A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 13) */
#define REG_UDPHS_EPTCTL13            (*(RoReg*)0xF80302ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 13) */
#define REG_UDPHS_EPTSETSTA13         (*(WoReg*)0xF80302B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 13) */
#define REG_UDPHS_EPTCLRSTA13         (*(WoReg*)0xF80302B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 13) */
#define REG_UDPHS_EPTSTA13            (*(RoReg*)0xF80302BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 13) */
#define REG_UDPHS_EPTCFG14            (*(RwReg*)0xF80302C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 14) */
#define REG_UDPHS_EPTCTLENB14         (*(WoReg*)0xF80302C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 14) */
#define REG_UDPHS_EPTCTLDIS14         (*(WoReg*)0xF80302C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 14) */
#define REG_UDPHS_EPTCTL14            (*(RoReg*)0xF80302CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 14) */
#define REG_UDPHS_EPTSETSTA14         (*(WoReg*)0xF80302D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 14) */
#define REG_UDPHS_EPTCLRSTA14         (*(WoReg*)0xF80302D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 14) */
#define REG_UDPHS_EPTSTA14            (*(RoReg*)0xF80302DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 14) */
#define REG_UDPHS_EPTCFG15            (*(RwReg*)0xF80302E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 15) */
#define REG_UDPHS_EPTCTLENB15         (*(WoReg*)0xF80302E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 15) */
#define REG_UDPHS_EPTCTLDIS15         (*(WoReg*)0xF80302E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 15) */
#define REG_UDPHS_EPTCTL15            (*(RoReg*)0xF80302ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 15) */
#define REG_UDPHS_EPTSETSTA15         (*(WoReg*)0xF80302F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 15) */
#define REG_UDPHS_EPTCLRSTA15         (*(WoReg*)0xF80302F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 15) */
#define REG_UDPHS_EPTSTA15            (*(RoReg*)0xF80302FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 15) */
#define REG_UDPHS_DMANXTDSC0          (*(RwReg*)0xF8030300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */
#define REG_UDPHS_DMAADDRESS0         (*(RwReg*)0xF8030304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */
#define REG_UDPHS_DMACONTROL0         (*(RwReg*)0xF8030308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */
#define REG_UDPHS_DMASTATUS0          (*(RwReg*)0xF803030CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */
#define REG_UDPHS_DMANXTDSC1          (*(RwReg*)0xF8030310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */
#define REG_UDPHS_DMAADDRESS1         (*(RwReg*)0xF8030314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */
#define REG_UDPHS_DMACONTROL1         (*(RwReg*)0xF8030318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */
#define REG_UDPHS_DMASTATUS1          (*(RwReg*)0xF803031CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */
#define REG_UDPHS_DMANXTDSC2          (*(RwReg*)0xF8030320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */
#define REG_UDPHS_DMAADDRESS2         (*(RwReg*)0xF8030324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */
#define REG_UDPHS_DMACONTROL2         (*(RwReg*)0xF8030328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */
#define REG_UDPHS_DMASTATUS2          (*(RwReg*)0xF803032CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */
#define REG_UDPHS_DMANXTDSC3          (*(RwReg*)0xF8030330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */
#define REG_UDPHS_DMAADDRESS3         (*(RwReg*)0xF8030334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */
#define REG_UDPHS_DMACONTROL3         (*(RwReg*)0xF8030338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */
#define REG_UDPHS_DMASTATUS3          (*(RwReg*)0xF803033CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */
#define REG_UDPHS_DMANXTDSC4          (*(RwReg*)0xF8030340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */
#define REG_UDPHS_DMAADDRESS4         (*(RwReg*)0xF8030344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */
#define REG_UDPHS_DMACONTROL4         (*(RwReg*)0xF8030348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */
#define REG_UDPHS_DMASTATUS4          (*(RwReg*)0xF803034CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */
#define REG_UDPHS_DMANXTDSC5          (*(RwReg*)0xF8030350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */
#define REG_UDPHS_DMAADDRESS5         (*(RwReg*)0xF8030354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */
#define REG_UDPHS_DMACONTROL5         (*(RwReg*)0xF8030358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */
#define REG_UDPHS_DMASTATUS5          (*(RwReg*)0xF803035CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */
#define REG_UDPHS_DMANXTDSC6          (*(RwReg*)0xF8030360U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 6) */
#define REG_UDPHS_DMAADDRESS6         (*(RwReg*)0xF8030364U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 6) */
#define REG_UDPHS_DMACONTROL6         (*(RwReg*)0xF8030368U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 6) */
#define REG_UDPHS_DMASTATUS6          (*(RwReg*)0xF803036CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 6) */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for SHA peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_SHA_CR                             (0xF8034000U) /**< \brief (SHA) Control Register */
#define REG_SHA_MR                             (0xF8034004U) /**< \brief (SHA) Mode Register */
#define REG_SHA_IER                            (0xF8034010U) /**< \brief (SHA) Interrupt Enable Register */
#define REG_SHA_IDR                            (0xF8034014U) /**< \brief (SHA) Interrupt Disable Register */
#define REG_SHA_IMR                            (0xF8034018U) /**< \brief (SHA) Interrupt Mask Register */
#define REG_SHA_ISR                            (0xF803401CU) /**< \brief (SHA) Interrupt Status Register */
#define REG_SHA_IDATAR                         (0xF8034040U) /**< \brief (SHA) Input Data 0 Register */
#define REG_SHA_IODATAR                        (0xF8034080U) /**< \brief (SHA) Input/Output Data 0 Register */
#else
#define REG_SHA_CR                    (*(WoReg*)0xF8034000U) /**< \brief (SHA) Control Register */
#define REG_SHA_MR                    (*(RwReg*)0xF8034004U) /**< \brief (SHA) Mode Register */
#define REG_SHA_IER                   (*(WoReg*)0xF8034010U) /**< \brief (SHA) Interrupt Enable Register */
#define REG_SHA_IDR                   (*(WoReg*)0xF8034014U) /**< \brief (SHA) Interrupt Disable Register */
#define REG_SHA_IMR                   (*(RoReg*)0xF8034018U) /**< \brief (SHA) Interrupt Mask Register */
#define REG_SHA_ISR                   (*(RoReg*)0xF803401CU) /**< \brief (SHA) Interrupt Status Register */
#define REG_SHA_IDATAR                (*(WoReg*)0xF8034040U) /**< \brief (SHA) Input Data 0 Register */
#define REG_SHA_IODATAR               (*(RwReg*)0xF8034080U) /**< \brief (SHA) Input/Output Data 0 Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for AES peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_AES_CR                             (0xF8038000U) /**< \brief (AES) Control Register */
#define REG_AES_MR                             (0xF8038004U) /**< \brief (AES) Mode Register */
#define REG_AES_IER                            (0xF8038010U) /**< \brief (AES) Interrupt Enable Register */
#define REG_AES_IDR                            (0xF8038014U) /**< \brief (AES) Interrupt Disable Register */
#define REG_AES_IMR                            (0xF8038018U) /**< \brief (AES) Interrupt Mask Register */
#define REG_AES_ISR                            (0xF803801CU) /**< \brief (AES) Interrupt Status Register */
#define REG_AES_KEYWR                          (0xF8038020U) /**< \brief (AES) Key Word Register */
#define REG_AES_IDATAR                         (0xF8038040U) /**< \brief (AES) Input Data Register */
#define REG_AES_ODATAR                         (0xF8038050U) /**< \brief (AES) Output Data Register */
#define REG_AES_IVR                            (0xF8038060U) /**< \brief (AES) Initialization Vector Register */
#define REG_AES_AADLENR                        (0xF8038070U) /**< \brief (AES) Additional Authenticated Data Length Register */
#define REG_AES_CLENR                          (0xF8038074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */
#define REG_AES_GHASHR                         (0xF8038078U) /**< \brief (AES) GCM Intermediate Hash Word Register */
#define REG_AES_TAGR                           (0xF8038088U) /**< \brief (AES) GCM Authentication Tag Word Register */
#define REG_AES_CTRR                           (0xF8038098U) /**< \brief (AES) GCM Encryption Counter Value Register */
#define REG_AES_GCMHR                          (0xF803809CU) /**< \brief (AES) GCM H World Register */
#else
#define REG_AES_CR                    (*(WoReg*)0xF8038000U) /**< \brief (AES) Control Register */
#define REG_AES_MR                    (*(RwReg*)0xF8038004U) /**< \brief (AES) Mode Register */
#define REG_AES_IER                   (*(WoReg*)0xF8038010U) /**< \brief (AES) Interrupt Enable Register */
#define REG_AES_IDR                   (*(WoReg*)0xF8038014U) /**< \brief (AES) Interrupt Disable Register */
#define REG_AES_IMR                   (*(RoReg*)0xF8038018U) /**< \brief (AES) Interrupt Mask Register */
#define REG_AES_ISR                   (*(RoReg*)0xF803801CU) /**< \brief (AES) Interrupt Status Register */
#define REG_AES_KEYWR                 (*(WoReg*)0xF8038020U) /**< \brief (AES) Key Word Register */
#define REG_AES_IDATAR                (*(WoReg*)0xF8038040U) /**< \brief (AES) Input Data Register */
#define REG_AES_ODATAR                (*(RoReg*)0xF8038050U) /**< \brief (AES) Output Data Register */
#define REG_AES_IVR                   (*(WoReg*)0xF8038060U) /**< \brief (AES) Initialization Vector Register */
#define REG_AES_AADLENR               (*(RwReg*)0xF8038070U) /**< \brief (AES) Additional Authenticated Data Length Register */
#define REG_AES_CLENR                 (*(RwReg*)0xF8038074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */
#define REG_AES_GHASHR                (*(RwReg*)0xF8038078U) /**< \brief (AES) GCM Intermediate Hash Word Register */
#define REG_AES_TAGR                  (*(RoReg*)0xF8038088U) /**< \brief (AES) GCM Authentication Tag Word Register */
#define REG_AES_CTRR                  (*(RoReg*)0xF8038098U) /**< \brief (AES) GCM Encryption Counter Value Register */
#define REG_AES_GCMHR                 (*(RwReg*)0xF803809CU) /**< \brief (AES) GCM H World Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for TDES peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_TDES_CR                            (0xF803C000U) /**< \brief (TDES) Control Register */
#define REG_TDES_MR                            (0xF803C004U) /**< \brief (TDES) Mode Register */
#define REG_TDES_IER                           (0xF803C010U) /**< \brief (TDES) Interrupt Enable Register */
#define REG_TDES_IDR                           (0xF803C014U) /**< \brief (TDES) Interrupt Disable Register */
#define REG_TDES_IMR                           (0xF803C018U) /**< \brief (TDES) Interrupt Mask Register */
#define REG_TDES_ISR                           (0xF803C01CU) /**< \brief (TDES) Interrupt Status Register */
#define REG_TDES_KEY1WR                        (0xF803C020U) /**< \brief (TDES) Key 1 Word Register */
#define REG_TDES_KEY2WR                        (0xF803C028U) /**< \brief (TDES) Key 2 Word Register */
#define REG_TDES_KEY3WR                        (0xF803C030U) /**< \brief (TDES) Key 3 Word Register */
#define REG_TDES_IDATAR                        (0xF803C040U) /**< \brief (TDES) Input Data Register */
#define REG_TDES_ODATAR                        (0xF803C050U) /**< \brief (TDES) Output Data Register */
#define REG_TDES_IVR                           (0xF803C060U) /**< \brief (TDES) Initialization Vector Register */
#define REG_TDES_XTEARNDR                      (0xF803C070U) /**< \brief (TDES) XTEA Rounds Register */
#else
#define REG_TDES_CR                   (*(WoReg*)0xF803C000U) /**< \brief (TDES) Control Register */
#define REG_TDES_MR                   (*(RwReg*)0xF803C004U) /**< \brief (TDES) Mode Register */
#define REG_TDES_IER                  (*(WoReg*)0xF803C010U) /**< \brief (TDES) Interrupt Enable Register */
#define REG_TDES_IDR                  (*(WoReg*)0xF803C014U) /**< \brief (TDES) Interrupt Disable Register */
#define REG_TDES_IMR                  (*(RoReg*)0xF803C018U) /**< \brief (TDES) Interrupt Mask Register */
#define REG_TDES_ISR                  (*(RoReg*)0xF803C01CU) /**< \brief (TDES) Interrupt Status Register */
#define REG_TDES_KEY1WR               (*(WoReg*)0xF803C020U) /**< \brief (TDES) Key 1 Word Register */
#define REG_TDES_KEY2WR               (*(WoReg*)0xF803C028U) /**< \brief (TDES) Key 2 Word Register */
#define REG_TDES_KEY3WR               (*(WoReg*)0xF803C030U) /**< \brief (TDES) Key 3 Word Register */
#define REG_TDES_IDATAR               (*(WoReg*)0xF803C040U) /**< \brief (TDES) Input Data Register */
#define REG_TDES_ODATAR               (*(RoReg*)0xF803C050U) /**< \brief (TDES) Output Data Register */
#define REG_TDES_IVR                  (*(WoReg*)0xF803C060U) /**< \brief (TDES) Initialization Vector Register */
#define REG_TDES_XTEARNDR             (*(RwReg*)0xF803C070U) /**< \brief (TDES) XTEA Rounds Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for TRNG peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_TRNG_CR                            (0xF8040000U) /**< \brief (TRNG) Control Register */
#define REG_TRNG_IER                           (0xF8040010U) /**< \brief (TRNG) Interrupt Enable Register */
#define REG_TRNG_IDR                           (0xF8040014U) /**< \brief (TRNG) Interrupt Disable Register */
#define REG_TRNG_IMR                           (0xF8040018U) /**< \brief (TRNG) Interrupt Mask Register */
#define REG_TRNG_ISR                           (0xF804001CU) /**< \brief (TRNG) Interrupt Status Register */
#define REG_TRNG_ODATA                         (0xF8040050U) /**< \brief (TRNG) Output Data Register */
#else
#define REG_TRNG_CR                   (*(WoReg*)0xF8040000U) /**< \brief (TRNG) Control Register */
#define REG_TRNG_IER                  (*(WoReg*)0xF8040010U) /**< \brief (TRNG) Interrupt Enable Register */
#define REG_TRNG_IDR                  (*(WoReg*)0xF8040014U) /**< \brief (TRNG) Interrupt Disable Register */
#define REG_TRNG_IMR                  (*(RoReg*)0xF8040018U) /**< \brief (TRNG) Interrupt Mask Register */
#define REG_TRNG_ISR                  (*(RoReg*)0xF804001CU) /**< \brief (TRNG) Interrupt Status Register */
#define REG_TRNG_ODATA                (*(RoReg*)0xF8040050U) /**< \brief (TRNG) Output Data Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for SMC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_SMC_CFG                            (0xFFFFC000U) /**< \brief (SMC) SMC NFC Configuration Register */
#define REG_SMC_CTRL                           (0xFFFFC004U) /**< \brief (SMC) SMC NFC Control Register */
#define REG_SMC_SR                             (0xFFFFC008U) /**< \brief (SMC) SMC NFC Status Register */
#define REG_SMC_IER                            (0xFFFFC00CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
#define REG_SMC_IDR                            (0xFFFFC010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
#define REG_SMC_IMR                            (0xFFFFC014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
#define REG_SMC_ADDR                           (0xFFFFC018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
#define REG_SMC_BANK                           (0xFFFFC01CU) /**< \brief (SMC) SMC Bank Address Register */
#define REG_SMC_ECC_CTRL                       (0xFFFFC020U) /**< \brief (SMC) SMC ECC Control Register */
#define REG_SMC_ECC_MD                         (0xFFFFC024U) /**< \brief (SMC) SMC ECC Mode Register */
#define REG_SMC_ECC_SR1                        (0xFFFFC028U) /**< \brief (SMC) SMC ECC Status 1 Register */
#define REG_SMC_ECC_PR0                        (0xFFFFC02CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
#define REG_SMC_ECC_PR1                        (0xFFFFC030U) /**< \brief (SMC) SMC ECC parity 1 Register */
#define REG_SMC_ECC_SR2                        (0xFFFFC034U) /**< \brief (SMC) SMC ECC status 2 Register */
#define REG_SMC_ECC_PR2                        (0xFFFFC038U) /**< \brief (SMC) SMC ECC parity 2 Register */
#define REG_SMC_ECC_PR3                        (0xFFFFC03CU) /**< \brief (SMC) SMC ECC parity 3 Register */
#define REG_SMC_ECC_PR4                        (0xFFFFC040U) /**< \brief (SMC) SMC ECC parity 4 Register */
#define REG_SMC_ECC_PR5                        (0xFFFFC044U) /**< \brief (SMC) SMC ECC parity 5 Register */
#define REG_SMC_ECC_PR6                        (0xFFFFC048U) /**< \brief (SMC) SMC ECC parity 6 Register */
#define REG_SMC_ECC_PR7                        (0xFFFFC04CU) /**< \brief (SMC) SMC ECC parity 7 Register */
#define REG_SMC_ECC_PR8                        (0xFFFFC050U) /**< \brief (SMC) SMC ECC parity 8 Register */
#define REG_SMC_ECC_PR9                        (0xFFFFC054U) /**< \brief (SMC) SMC ECC parity 9 Register */
#define REG_SMC_ECC_PR10                       (0xFFFFC058U) /**< \brief (SMC) SMC ECC parity 10 Register */
#define REG_SMC_ECC_PR11                       (0xFFFFC05CU) /**< \brief (SMC) SMC ECC parity 11 Register */
#define REG_SMC_ECC_PR12                       (0xFFFFC060U) /**< \brief (SMC) SMC ECC parity 12 Register */
#define REG_SMC_ECC_PR13                       (0xFFFFC064U) /**< \brief (SMC) SMC ECC parity 13 Register */
#define REG_SMC_ECC_PR14                       (0xFFFFC068U) /**< \brief (SMC) SMC ECC parity 14 Register */
#define REG_SMC_ECC_PR15                       (0xFFFFC06CU) /**< \brief (SMC) SMC ECC parity 15 Register */
#define REG_SMC_PMECCFG                        (0xFFFFC070U) /**< \brief (SMC) PMECC Configuration Register */
#define REG_SMC_PMECCSAREA                     (0xFFFFC074U) /**< \brief (SMC) PMECC Spare Area Size Register */
#define REG_SMC_PMECCSADDR                     (0xFFFFC078U) /**< \brief (SMC) PMECC Start Address Register */
#define REG_SMC_PMECCEADDR                     (0xFFFFC07CU) /**< \brief (SMC) PMECC End Address Register */
#define REG_SMC_PMECCTRL                       (0xFFFFC084U) /**< \brief (SMC) PMECC Control Register */
#define REG_SMC_PMECCSR                        (0xFFFFC088U) /**< \brief (SMC) PMECC Status Register */
#define REG_SMC_PMECCIER                       (0xFFFFC08CU) /**< \brief (SMC) PMECC Interrupt Enable register */
#define REG_SMC_PMECCIDR                       (0xFFFFC090U) /**< \brief (SMC) PMECC Interrupt Disable Register */
#define REG_SMC_PMECCIMR                       (0xFFFFC094U) /**< \brief (SMC) PMECC Interrupt Mask Register */
#define REG_SMC_PMECCISR                       (0xFFFFC098U) /**< \brief (SMC) PMECC Interrupt Status Register */
#define REG_SMC_PMECC0_0                       (0xFFFFC0B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 0) */
#define REG_SMC_PMECC1_0                       (0xFFFFC0B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 0) */
#define REG_SMC_PMECC2_0                       (0xFFFFC0B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 0) */
#define REG_SMC_PMECC3_0                       (0xFFFFC0BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 0) */
#define REG_SMC_PMECC4_0                       (0xFFFFC0C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 0) */
#define REG_SMC_PMECC5_0                       (0xFFFFC0C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 0) */
#define REG_SMC_PMECC6_0                       (0xFFFFC0C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 0) */
#define REG_SMC_PMECC7_0                       (0xFFFFC0CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 0) */
#define REG_SMC_PMECC8_0                       (0xFFFFC0D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 0) */
#define REG_SMC_PMECC9_0                       (0xFFFFC0D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 0) */
#define REG_SMC_PMECC10_0                      (0xFFFFC0D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 0) */
#define REG_SMC_PMECC0_1                       (0xFFFFC0F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 1) */
#define REG_SMC_PMECC1_1                       (0xFFFFC0F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 1) */
#define REG_SMC_PMECC2_1                       (0xFFFFC0F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 1) */
#define REG_SMC_PMECC3_1                       (0xFFFFC0FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 1) */
#define REG_SMC_PMECC4_1                       (0xFFFFC100U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 1) */
#define REG_SMC_PMECC5_1                       (0xFFFFC104U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 1) */
#define REG_SMC_PMECC6_1                       (0xFFFFC108U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 1) */
#define REG_SMC_PMECC7_1                       (0xFFFFC10CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 1) */
#define REG_SMC_PMECC8_1                       (0xFFFFC110U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 1) */
#define REG_SMC_PMECC9_1                       (0xFFFFC114U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 1) */
#define REG_SMC_PMECC10_1                      (0xFFFFC118U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 1) */
#define REG_SMC_PMECC0_2                       (0xFFFFC130U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 2) */
#define REG_SMC_PMECC1_2                       (0xFFFFC134U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 2) */
#define REG_SMC_PMECC2_2                       (0xFFFFC138U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 2) */
#define REG_SMC_PMECC3_2                       (0xFFFFC13CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 2) */
#define REG_SMC_PMECC4_2                       (0xFFFFC140U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 2) */
#define REG_SMC_PMECC5_2                       (0xFFFFC144U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 2) */
#define REG_SMC_PMECC6_2                       (0xFFFFC148U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 2) */
#define REG_SMC_PMECC7_2                       (0xFFFFC14CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 2) */
#define REG_SMC_PMECC8_2                       (0xFFFFC150U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 2) */
#define REG_SMC_PMECC9_2                       (0xFFFFC154U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 2) */
#define REG_SMC_PMECC10_2                      (0xFFFFC158U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 2) */
#define REG_SMC_PMECC0_3                       (0xFFFFC170U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 3) */
#define REG_SMC_PMECC1_3                       (0xFFFFC174U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 3) */
#define REG_SMC_PMECC2_3                       (0xFFFFC178U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 3) */
#define REG_SMC_PMECC3_3                       (0xFFFFC17CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 3) */
#define REG_SMC_PMECC4_3                       (0xFFFFC180U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 3) */
#define REG_SMC_PMECC5_3                       (0xFFFFC184U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 3) */
#define REG_SMC_PMECC6_3                       (0xFFFFC188U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 3) */
#define REG_SMC_PMECC7_3                       (0xFFFFC18CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 3) */
#define REG_SMC_PMECC8_3                       (0xFFFFC190U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 3) */
#define REG_SMC_PMECC9_3                       (0xFFFFC194U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 3) */
#define REG_SMC_PMECC10_3                      (0xFFFFC198U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 3) */
#define REG_SMC_PMECC0_4                       (0xFFFFC1B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 4) */
#define REG_SMC_PMECC1_4                       (0xFFFFC1B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 4) */
#define REG_SMC_PMECC2_4                       (0xFFFFC1B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 4) */
#define REG_SMC_PMECC3_4                       (0xFFFFC1BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 4) */
#define REG_SMC_PMECC4_4                       (0xFFFFC1C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 4) */
#define REG_SMC_PMECC5_4                       (0xFFFFC1C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 4) */
#define REG_SMC_PMECC6_4                       (0xFFFFC1C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 4) */
#define REG_SMC_PMECC7_4                       (0xFFFFC1CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 4) */
#define REG_SMC_PMECC8_4                       (0xFFFFC1D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 4) */
#define REG_SMC_PMECC9_4                       (0xFFFFC1D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 4) */
#define REG_SMC_PMECC10_4                      (0xFFFFC1D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 4) */
#define REG_SMC_PMECC0_5                       (0xFFFFC1F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 5) */
#define REG_SMC_PMECC1_5                       (0xFFFFC1F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 5) */
#define REG_SMC_PMECC2_5                       (0xFFFFC1F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 5) */
#define REG_SMC_PMECC3_5                       (0xFFFFC1FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 5) */
#define REG_SMC_PMECC4_5                       (0xFFFFC200U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 5) */
#define REG_SMC_PMECC5_5                       (0xFFFFC204U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 5) */
#define REG_SMC_PMECC6_5                       (0xFFFFC208U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 5) */
#define REG_SMC_PMECC7_5                       (0xFFFFC20CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 5) */
#define REG_SMC_PMECC8_5                       (0xFFFFC210U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 5) */
#define REG_SMC_PMECC9_5                       (0xFFFFC214U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 5) */
#define REG_SMC_PMECC10_5                      (0xFFFFC218U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 5) */
#define REG_SMC_PMECC0_6                       (0xFFFFC230U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 6) */
#define REG_SMC_PMECC1_6                       (0xFFFFC234U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 6) */
#define REG_SMC_PMECC2_6                       (0xFFFFC238U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 6) */
#define REG_SMC_PMECC3_6                       (0xFFFFC23CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 6) */
#define REG_SMC_PMECC4_6                       (0xFFFFC240U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 6) */
#define REG_SMC_PMECC5_6                       (0xFFFFC244U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 6) */
#define REG_SMC_PMECC6_6                       (0xFFFFC248U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 6) */
#define REG_SMC_PMECC7_6                       (0xFFFFC24CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 6) */
#define REG_SMC_PMECC8_6                       (0xFFFFC250U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 6) */
#define REG_SMC_PMECC9_6                       (0xFFFFC254U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 6) */
#define REG_SMC_PMECC10_6                      (0xFFFFC258U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 6) */
#define REG_SMC_PMECC0_7                       (0xFFFFC270U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 7) */
#define REG_SMC_PMECC1_7                       (0xFFFFC274U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 7) */
#define REG_SMC_PMECC2_7                       (0xFFFFC278U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 7) */
#define REG_SMC_PMECC3_7                       (0xFFFFC27CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 7) */
#define REG_SMC_PMECC4_7                       (0xFFFFC280U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 7) */
#define REG_SMC_PMECC5_7                       (0xFFFFC284U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 7) */
#define REG_SMC_PMECC6_7                       (0xFFFFC288U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 7) */
#define REG_SMC_PMECC7_7                       (0xFFFFC28CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 7) */
#define REG_SMC_PMECC8_7                       (0xFFFFC290U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 7) */
#define REG_SMC_PMECC9_7                       (0xFFFFC294U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 7) */
#define REG_SMC_PMECC10_7                      (0xFFFFC298U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 7) */
#define REG_SMC_REM0_0                         (0xFFFFC2B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 0) */
#define REG_SMC_REM1_0                         (0xFFFFC2B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 0) */
#define REG_SMC_REM2_0                         (0xFFFFC2B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 0) */
#define REG_SMC_REM3_0                         (0xFFFFC2BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 0) */
#define REG_SMC_REM4_0                         (0xFFFFC2C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 0) */
#define REG_SMC_REM5_0                         (0xFFFFC2C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 0) */
#define REG_SMC_REM6_0                         (0xFFFFC2C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 0) */
#define REG_SMC_REM7_0                         (0xFFFFC2CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 0) */
#define REG_SMC_REM8_0                         (0xFFFFC2D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 0) */
#define REG_SMC_REM9_0                         (0xFFFFC2D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 0) */
#define REG_SMC_REM10_0                        (0xFFFFC2D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 0) */
#define REG_SMC_REM11_0                        (0xFFFFC2DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 0) */
#define REG_SMC_REM0_1                         (0xFFFFC2F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 1) */
#define REG_SMC_REM1_1                         (0xFFFFC2F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 1) */
#define REG_SMC_REM2_1                         (0xFFFFC2F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 1) */
#define REG_SMC_REM3_1                         (0xFFFFC2FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 1) */
#define REG_SMC_REM4_1                         (0xFFFFC300U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 1) */
#define REG_SMC_REM5_1                         (0xFFFFC304U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 1) */
#define REG_SMC_REM6_1                         (0xFFFFC308U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 1) */
#define REG_SMC_REM7_1                         (0xFFFFC30CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 1) */
#define REG_SMC_REM8_1                         (0xFFFFC310U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 1) */
#define REG_SMC_REM9_1                         (0xFFFFC314U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 1) */
#define REG_SMC_REM10_1                        (0xFFFFC318U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 1) */
#define REG_SMC_REM11_1                        (0xFFFFC31CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 1) */
#define REG_SMC_REM0_2                         (0xFFFFC330U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 2) */
#define REG_SMC_REM1_2                         (0xFFFFC334U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 2) */
#define REG_SMC_REM2_2                         (0xFFFFC338U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 2) */
#define REG_SMC_REM3_2                         (0xFFFFC33CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 2) */
#define REG_SMC_REM4_2                         (0xFFFFC340U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 2) */
#define REG_SMC_REM5_2                         (0xFFFFC344U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 2) */
#define REG_SMC_REM6_2                         (0xFFFFC348U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 2) */
#define REG_SMC_REM7_2                         (0xFFFFC34CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 2) */
#define REG_SMC_REM8_2                         (0xFFFFC350U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 2) */
#define REG_SMC_REM9_2                         (0xFFFFC354U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 2) */
#define REG_SMC_REM10_2                        (0xFFFFC358U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 2) */
#define REG_SMC_REM11_2                        (0xFFFFC35CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 2) */
#define REG_SMC_REM0_3                         (0xFFFFC370U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 3) */
#define REG_SMC_REM1_3                         (0xFFFFC374U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 3) */
#define REG_SMC_REM2_3                         (0xFFFFC378U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 3) */
#define REG_SMC_REM3_3                         (0xFFFFC37CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 3) */
#define REG_SMC_REM4_3                         (0xFFFFC380U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 3) */
#define REG_SMC_REM5_3                         (0xFFFFC384U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 3) */
#define REG_SMC_REM6_3                         (0xFFFFC388U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 3) */
#define REG_SMC_REM7_3                         (0xFFFFC38CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 3) */
#define REG_SMC_REM8_3                         (0xFFFFC390U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 3) */
#define REG_SMC_REM9_3                         (0xFFFFC394U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 3) */
#define REG_SMC_REM10_3                        (0xFFFFC398U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 3) */
#define REG_SMC_REM11_3                        (0xFFFFC39CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 3) */
#define REG_SMC_REM0_4                         (0xFFFFC3B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 4) */
#define REG_SMC_REM1_4                         (0xFFFFC3B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 4) */
#define REG_SMC_REM2_4                         (0xFFFFC3B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 4) */
#define REG_SMC_REM3_4                         (0xFFFFC3BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 4) */
#define REG_SMC_REM4_4                         (0xFFFFC3C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 4) */
#define REG_SMC_REM5_4                         (0xFFFFC3C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 4) */
#define REG_SMC_REM6_4                         (0xFFFFC3C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 4) */
#define REG_SMC_REM7_4                         (0xFFFFC3CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 4) */
#define REG_SMC_REM8_4                         (0xFFFFC3D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 4) */
#define REG_SMC_REM9_4                         (0xFFFFC3D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 4) */
#define REG_SMC_REM10_4                        (0xFFFFC3D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 4) */
#define REG_SMC_REM11_4                        (0xFFFFC3DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 4) */
#define REG_SMC_REM0_5                         (0xFFFFC3F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 5) */
#define REG_SMC_REM1_5                         (0xFFFFC3F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 5) */
#define REG_SMC_REM2_5                         (0xFFFFC3F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 5) */
#define REG_SMC_REM3_5                         (0xFFFFC3FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 5) */
#define REG_SMC_REM4_5                         (0xFFFFC400U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 5) */
#define REG_SMC_REM5_5                         (0xFFFFC404U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 5) */
#define REG_SMC_REM6_5                         (0xFFFFC408U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 5) */
#define REG_SMC_REM7_5                         (0xFFFFC40CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 5) */
#define REG_SMC_REM8_5                         (0xFFFFC410U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 5) */
#define REG_SMC_REM9_5                         (0xFFFFC414U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 5) */
#define REG_SMC_REM10_5                        (0xFFFFC418U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 5) */
#define REG_SMC_REM11_5                        (0xFFFFC41CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 5) */
#define REG_SMC_REM0_6                         (0xFFFFC430U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 6) */
#define REG_SMC_REM1_6                         (0xFFFFC434U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 6) */
#define REG_SMC_REM2_6                         (0xFFFFC438U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 6) */
#define REG_SMC_REM3_6                         (0xFFFFC43CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 6) */
#define REG_SMC_REM4_6                         (0xFFFFC440U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 6) */
#define REG_SMC_REM5_6                         (0xFFFFC444U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 6) */
#define REG_SMC_REM6_6                         (0xFFFFC448U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 6) */
#define REG_SMC_REM7_6                         (0xFFFFC44CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 6) */
#define REG_SMC_REM8_6                         (0xFFFFC450U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 6) */
#define REG_SMC_REM9_6                         (0xFFFFC454U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 6) */
#define REG_SMC_REM10_6                        (0xFFFFC458U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 6) */
#define REG_SMC_REM11_6                        (0xFFFFC45CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 6) */
#define REG_SMC_REM0_7                         (0xFFFFC470U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 7) */
#define REG_SMC_REM1_7                         (0xFFFFC474U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 7) */
#define REG_SMC_REM2_7                         (0xFFFFC478U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 7) */
#define REG_SMC_REM3_7                         (0xFFFFC47CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 7) */
#define REG_SMC_REM4_7                         (0xFFFFC480U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 7) */
#define REG_SMC_REM5_7                         (0xFFFFC484U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 7) */
#define REG_SMC_REM6_7                         (0xFFFFC488U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 7) */
#define REG_SMC_REM7_7                         (0xFFFFC48CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 7) */
#define REG_SMC_REM8_7                         (0xFFFFC490U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 7) */
#define REG_SMC_REM9_7                         (0xFFFFC494U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 7) */
#define REG_SMC_REM10_7                        (0xFFFFC498U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 7) */
#define REG_SMC_REM11_7                        (0xFFFFC49CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 7) */
#define REG_SMC_ELCFG                          (0xFFFFC500U) /**< \brief (SMC) PMECCError Location Configuration Register */
#define REG_SMC_ELPRIM                         (0xFFFFC504U) /**< \brief (SMC) PMECC Error Location Primitive Register */
#define REG_SMC_ELEN                           (0xFFFFC508U) /**< \brief (SMC) PMECC Error Location Enable Register */
#define REG_SMC_ELDIS                          (0xFFFFC50CU) /**< \brief (SMC) PMECC Error Location Disable Register */
#define REG_SMC_ELSR                           (0xFFFFC510U) /**< \brief (SMC) PMECC Error Location Status Register */
#define REG_SMC_ELIER                          (0xFFFFC514U) /**< \brief (SMC) PMECC Error Location Interrupt Enable register */
#define REG_SMC_ELIDR                          (0xFFFFC518U) /**< \brief (SMC) PMECC Error Location Interrupt Disable Register */
#define REG_SMC_ELIMR                          (0xFFFFC51CU) /**< \brief (SMC) PMECC Error Location Interrupt Mask Register */
#define REG_SMC_ELISR                          (0xFFFFC520U) /**< \brief (SMC) PMECC Error Location Interrupt Status Register */
#define REG_SMC_SIGMA0                         (0xFFFFC528U) /**< \brief (SMC) PMECC Error Location SIGMA 0 Register */
#define REG_SMC_SIGMA1                         (0xFFFFC52CU) /**< \brief (SMC) PMECC Error Location SIGMA 1 Register */
#define REG_SMC_SIGMA2                         (0xFFFFC530U) /**< \brief (SMC) PMECC Error Location SIGMA 2 Register */
#define REG_SMC_SIGMA3                         (0xFFFFC534U) /**< \brief (SMC) PMECC Error Location SIGMA 3 Register */
#define REG_SMC_SIGMA4                         (0xFFFFC538U) /**< \brief (SMC) PMECC Error Location SIGMA 4 Register */
#define REG_SMC_SIGMA5                         (0xFFFFC53CU) /**< \brief (SMC) PMECC Error Location SIGMA 5 Register */
#define REG_SMC_SIGMA6                         (0xFFFFC540U) /**< \brief (SMC) PMECC Error Location SIGMA 6 Register */
#define REG_SMC_SIGMA7                         (0xFFFFC544U) /**< \brief (SMC) PMECC Error Location SIGMA 7 Register */
#define REG_SMC_SIGMA8                         (0xFFFFC548U) /**< \brief (SMC) PMECC Error Location SIGMA 8 Register */
#define REG_SMC_SIGMA9                         (0xFFFFC54CU) /**< \brief (SMC) PMECC Error Location SIGMA 9 Register */
#define REG_SMC_SIGMA10                        (0xFFFFC550U) /**< \brief (SMC) PMECC Error Location SIGMA 10 Register */
#define REG_SMC_SIGMA11                        (0xFFFFC554U) /**< \brief (SMC) PMECC Error Location SIGMA 11 Register */
#define REG_SMC_SIGMA12                        (0xFFFFC558U) /**< \brief (SMC) PMECC Error Location SIGMA 12 Register */
#define REG_SMC_SIGMA13                        (0xFFFFC55CU) /**< \brief (SMC) PMECC Error Location SIGMA 13 Register */
#define REG_SMC_SIGMA14                        (0xFFFFC560U) /**< \brief (SMC) PMECC Error Location SIGMA 14 Register */
#define REG_SMC_SIGMA15                        (0xFFFFC564U) /**< \brief (SMC) PMECC Error Location SIGMA 15 Register */
#define REG_SMC_SIGMA16                        (0xFFFFC568U) /**< \brief (SMC) PMECC Error Location SIGMA 16 Register */
#define REG_SMC_SIGMA17                        (0xFFFFC56CU) /**< \brief (SMC) PMECC Error Location SIGMA 17 Register */
#define REG_SMC_SIGMA18                        (0xFFFFC570U) /**< \brief (SMC) PMECC Error Location SIGMA 18 Register */
#define REG_SMC_SIGMA19                        (0xFFFFC574U) /**< \brief (SMC) PMECC Error Location SIGMA 19 Register */
#define REG_SMC_SIGMA20                        (0xFFFFC578U) /**< \brief (SMC) PMECC Error Location SIGMA 20 Register */
#define REG_SMC_SIGMA21                        (0xFFFFC57CU) /**< \brief (SMC) PMECC Error Location SIGMA 21 Register */
#define REG_SMC_SIGMA22                        (0xFFFFC580U) /**< \brief (SMC) PMECC Error Location SIGMA 22 Register */
#define REG_SMC_SIGMA23                        (0xFFFFC584U) /**< \brief (SMC) PMECC Error Location SIGMA 23 Register */
#define REG_SMC_SIGMA24                        (0xFFFFC588U) /**< \brief (SMC) PMECC Error Location SIGMA 24 Register */
#define REG_SMC_ERRLOC                         (0xFFFFC58CU) /**< \brief (SMC) PMECC Error Location 0 Register */
#define REG_SMC_SETUP0                         (0xFFFFC600U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
#define REG_SMC_PULSE0                         (0xFFFFC604U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
#define REG_SMC_CYCLE0                         (0xFFFFC608U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
#define REG_SMC_TIMINGS0                       (0xFFFFC60CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
#define REG_SMC_MODE0                          (0xFFFFC610U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
#define REG_SMC_SETUP1                         (0xFFFFC614U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
#define REG_SMC_PULSE1                         (0xFFFFC618U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
#define REG_SMC_CYCLE1                         (0xFFFFC61CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
#define REG_SMC_TIMINGS1                       (0xFFFFC620U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
#define REG_SMC_MODE1                          (0xFFFFC624U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
#define REG_SMC_SETUP2                         (0xFFFFC628U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
#define REG_SMC_PULSE2                         (0xFFFFC62CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
#define REG_SMC_CYCLE2                         (0xFFFFC630U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
#define REG_SMC_TIMINGS2                       (0xFFFFC634U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
#define REG_SMC_MODE2                          (0xFFFFC638U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
#define REG_SMC_SETUP3                         (0xFFFFC63CU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
#define REG_SMC_PULSE3                         (0xFFFFC640U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
#define REG_SMC_CYCLE3                         (0xFFFFC644U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
#define REG_SMC_TIMINGS3                       (0xFFFFC648U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
#define REG_SMC_MODE3                          (0xFFFFC64CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
#define REG_SMC_OCMS                           (0xFFFFC6A0U) /**< \brief (SMC) SMC OCMS Register */
#define REG_SMC_KEY1                           (0xFFFFC6A4U) /**< \brief (SMC) SMC OCMS KEY1 Register */
#define REG_SMC_KEY2                           (0xFFFFC6A8U) /**< \brief (SMC) SMC OCMS KEY2 Register */
#define REG_SMC_WPCR                           (0xFFFFC6E4U) /**< \brief (SMC) SMC Write Protection Control Register */
#define REG_SMC_WPSR                           (0xFFFFC6E8U) /**< \brief (SMC) SMC Write Protection Status Register */
#else
#define REG_SMC_CFG                   (*(RwReg*)0xFFFFC000U) /**< \brief (SMC) SMC NFC Configuration Register */
#define REG_SMC_CTRL                  (*(WoReg*)0xFFFFC004U) /**< \brief (SMC) SMC NFC Control Register */
#define REG_SMC_SR                    (*(RoReg*)0xFFFFC008U) /**< \brief (SMC) SMC NFC Status Register */
#define REG_SMC_IER                   (*(WoReg*)0xFFFFC00CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
#define REG_SMC_IDR                   (*(WoReg*)0xFFFFC010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
#define REG_SMC_IMR                   (*(RoReg*)0xFFFFC014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
#define REG_SMC_ADDR                  (*(RwReg*)0xFFFFC018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
#define REG_SMC_BANK                  (*(RwReg*)0xFFFFC01CU) /**< \brief (SMC) SMC Bank Address Register */
#define REG_SMC_ECC_CTRL              (*(WoReg*)0xFFFFC020U) /**< \brief (SMC) SMC ECC Control Register */
#define REG_SMC_ECC_MD                (*(RwReg*)0xFFFFC024U) /**< \brief (SMC) SMC ECC Mode Register */
#define REG_SMC_ECC_SR1               (*(RoReg*)0xFFFFC028U) /**< \brief (SMC) SMC ECC Status 1 Register */
#define REG_SMC_ECC_PR0               (*(RoReg*)0xFFFFC02CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
#define REG_SMC_ECC_PR1               (*(RoReg*)0xFFFFC030U) /**< \brief (SMC) SMC ECC parity 1 Register */
#define REG_SMC_ECC_SR2               (*(RoReg*)0xFFFFC034U) /**< \brief (SMC) SMC ECC status 2 Register */
#define REG_SMC_ECC_PR2               (*(RoReg*)0xFFFFC038U) /**< \brief (SMC) SMC ECC parity 2 Register */
#define REG_SMC_ECC_PR3               (*(RoReg*)0xFFFFC03CU) /**< \brief (SMC) SMC ECC parity 3 Register */
#define REG_SMC_ECC_PR4               (*(RoReg*)0xFFFFC040U) /**< \brief (SMC) SMC ECC parity 4 Register */
#define REG_SMC_ECC_PR5               (*(RoReg*)0xFFFFC044U) /**< \brief (SMC) SMC ECC parity 5 Register */
#define REG_SMC_ECC_PR6               (*(RoReg*)0xFFFFC048U) /**< \brief (SMC) SMC ECC parity 6 Register */
#define REG_SMC_ECC_PR7               (*(RoReg*)0xFFFFC04CU) /**< \brief (SMC) SMC ECC parity 7 Register */
#define REG_SMC_ECC_PR8               (*(RoReg*)0xFFFFC050U) /**< \brief (SMC) SMC ECC parity 8 Register */
#define REG_SMC_ECC_PR9               (*(RoReg*)0xFFFFC054U) /**< \brief (SMC) SMC ECC parity 9 Register */
#define REG_SMC_ECC_PR10              (*(RoReg*)0xFFFFC058U) /**< \brief (SMC) SMC ECC parity 10 Register */
#define REG_SMC_ECC_PR11              (*(RoReg*)0xFFFFC05CU) /**< \brief (SMC) SMC ECC parity 11 Register */
#define REG_SMC_ECC_PR12              (*(RoReg*)0xFFFFC060U) /**< \brief (SMC) SMC ECC parity 12 Register */
#define REG_SMC_ECC_PR13              (*(RoReg*)0xFFFFC064U) /**< \brief (SMC) SMC ECC parity 13 Register */
#define REG_SMC_ECC_PR14              (*(RoReg*)0xFFFFC068U) /**< \brief (SMC) SMC ECC parity 14 Register */
#define REG_SMC_ECC_PR15              (*(RoReg*)0xFFFFC06CU) /**< \brief (SMC) SMC ECC parity 15 Register */
#define REG_SMC_PMECCFG               (*(RwReg*)0xFFFFC070U) /**< \brief (SMC) PMECC Configuration Register */
#define REG_SMC_PMECCSAREA            (*(RwReg*)0xFFFFC074U) /**< \brief (SMC) PMECC Spare Area Size Register */
#define REG_SMC_PMECCSADDR            (*(RwReg*)0xFFFFC078U) /**< \brief (SMC) PMECC Start Address Register */
#define REG_SMC_PMECCEADDR            (*(RwReg*)0xFFFFC07CU) /**< \brief (SMC) PMECC End Address Register */
#define REG_SMC_PMECCTRL              (*(WoReg*)0xFFFFC084U) /**< \brief (SMC) PMECC Control Register */
#define REG_SMC_PMECCSR               (*(RoReg*)0xFFFFC088U) /**< \brief (SMC) PMECC Status Register */
#define REG_SMC_PMECCIER              (*(WoReg*)0xFFFFC08CU) /**< \brief (SMC) PMECC Interrupt Enable register */
#define REG_SMC_PMECCIDR              (*(WoReg*)0xFFFFC090U) /**< \brief (SMC) PMECC Interrupt Disable Register */
#define REG_SMC_PMECCIMR              (*(RoReg*)0xFFFFC094U) /**< \brief (SMC) PMECC Interrupt Mask Register */
#define REG_SMC_PMECCISR              (*(RoReg*)0xFFFFC098U) /**< \brief (SMC) PMECC Interrupt Status Register */
#define REG_SMC_PMECC0_0              (*(RoReg*)0xFFFFC0B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 0) */
#define REG_SMC_PMECC1_0              (*(RoReg*)0xFFFFC0B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 0) */
#define REG_SMC_PMECC2_0              (*(RoReg*)0xFFFFC0B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 0) */
#define REG_SMC_PMECC3_0              (*(RoReg*)0xFFFFC0BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 0) */
#define REG_SMC_PMECC4_0              (*(RoReg*)0xFFFFC0C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 0) */
#define REG_SMC_PMECC5_0              (*(RoReg*)0xFFFFC0C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 0) */
#define REG_SMC_PMECC6_0              (*(RoReg*)0xFFFFC0C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 0) */
#define REG_SMC_PMECC7_0              (*(RoReg*)0xFFFFC0CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 0) */
#define REG_SMC_PMECC8_0              (*(RoReg*)0xFFFFC0D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 0) */
#define REG_SMC_PMECC9_0              (*(RoReg*)0xFFFFC0D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 0) */
#define REG_SMC_PMECC10_0             (*(RoReg*)0xFFFFC0D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 0) */
#define REG_SMC_PMECC0_1              (*(RoReg*)0xFFFFC0F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 1) */
#define REG_SMC_PMECC1_1              (*(RoReg*)0xFFFFC0F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 1) */
#define REG_SMC_PMECC2_1              (*(RoReg*)0xFFFFC0F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 1) */
#define REG_SMC_PMECC3_1              (*(RoReg*)0xFFFFC0FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 1) */
#define REG_SMC_PMECC4_1              (*(RoReg*)0xFFFFC100U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 1) */
#define REG_SMC_PMECC5_1              (*(RoReg*)0xFFFFC104U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 1) */
#define REG_SMC_PMECC6_1              (*(RoReg*)0xFFFFC108U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 1) */
#define REG_SMC_PMECC7_1              (*(RoReg*)0xFFFFC10CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 1) */
#define REG_SMC_PMECC8_1              (*(RoReg*)0xFFFFC110U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 1) */
#define REG_SMC_PMECC9_1              (*(RoReg*)0xFFFFC114U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 1) */
#define REG_SMC_PMECC10_1             (*(RoReg*)0xFFFFC118U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 1) */
#define REG_SMC_PMECC0_2              (*(RoReg*)0xFFFFC130U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 2) */
#define REG_SMC_PMECC1_2              (*(RoReg*)0xFFFFC134U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 2) */
#define REG_SMC_PMECC2_2              (*(RoReg*)0xFFFFC138U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 2) */
#define REG_SMC_PMECC3_2              (*(RoReg*)0xFFFFC13CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 2) */
#define REG_SMC_PMECC4_2              (*(RoReg*)0xFFFFC140U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 2) */
#define REG_SMC_PMECC5_2              (*(RoReg*)0xFFFFC144U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 2) */
#define REG_SMC_PMECC6_2              (*(RoReg*)0xFFFFC148U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 2) */
#define REG_SMC_PMECC7_2              (*(RoReg*)0xFFFFC14CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 2) */
#define REG_SMC_PMECC8_2              (*(RoReg*)0xFFFFC150U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 2) */
#define REG_SMC_PMECC9_2              (*(RoReg*)0xFFFFC154U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 2) */
#define REG_SMC_PMECC10_2             (*(RoReg*)0xFFFFC158U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 2) */
#define REG_SMC_PMECC0_3              (*(RoReg*)0xFFFFC170U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 3) */
#define REG_SMC_PMECC1_3              (*(RoReg*)0xFFFFC174U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 3) */
#define REG_SMC_PMECC2_3              (*(RoReg*)0xFFFFC178U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 3) */
#define REG_SMC_PMECC3_3              (*(RoReg*)0xFFFFC17CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 3) */
#define REG_SMC_PMECC4_3              (*(RoReg*)0xFFFFC180U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 3) */
#define REG_SMC_PMECC5_3              (*(RoReg*)0xFFFFC184U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 3) */
#define REG_SMC_PMECC6_3              (*(RoReg*)0xFFFFC188U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 3) */
#define REG_SMC_PMECC7_3              (*(RoReg*)0xFFFFC18CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 3) */
#define REG_SMC_PMECC8_3              (*(RoReg*)0xFFFFC190U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 3) */
#define REG_SMC_PMECC9_3              (*(RoReg*)0xFFFFC194U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 3) */
#define REG_SMC_PMECC10_3             (*(RoReg*)0xFFFFC198U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 3) */
#define REG_SMC_PMECC0_4              (*(RoReg*)0xFFFFC1B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 4) */
#define REG_SMC_PMECC1_4              (*(RoReg*)0xFFFFC1B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 4) */
#define REG_SMC_PMECC2_4              (*(RoReg*)0xFFFFC1B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 4) */
#define REG_SMC_PMECC3_4              (*(RoReg*)0xFFFFC1BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 4) */
#define REG_SMC_PMECC4_4              (*(RoReg*)0xFFFFC1C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 4) */
#define REG_SMC_PMECC5_4              (*(RoReg*)0xFFFFC1C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 4) */
#define REG_SMC_PMECC6_4              (*(RoReg*)0xFFFFC1C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 4) */
#define REG_SMC_PMECC7_4              (*(RoReg*)0xFFFFC1CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 4) */
#define REG_SMC_PMECC8_4              (*(RoReg*)0xFFFFC1D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 4) */
#define REG_SMC_PMECC9_4              (*(RoReg*)0xFFFFC1D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 4) */
#define REG_SMC_PMECC10_4             (*(RoReg*)0xFFFFC1D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 4) */
#define REG_SMC_PMECC0_5              (*(RoReg*)0xFFFFC1F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 5) */
#define REG_SMC_PMECC1_5              (*(RoReg*)0xFFFFC1F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 5) */
#define REG_SMC_PMECC2_5              (*(RoReg*)0xFFFFC1F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 5) */
#define REG_SMC_PMECC3_5              (*(RoReg*)0xFFFFC1FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 5) */
#define REG_SMC_PMECC4_5              (*(RoReg*)0xFFFFC200U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 5) */
#define REG_SMC_PMECC5_5              (*(RoReg*)0xFFFFC204U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 5) */
#define REG_SMC_PMECC6_5              (*(RoReg*)0xFFFFC208U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 5) */
#define REG_SMC_PMECC7_5              (*(RoReg*)0xFFFFC20CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 5) */
#define REG_SMC_PMECC8_5              (*(RoReg*)0xFFFFC210U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 5) */
#define REG_SMC_PMECC9_5              (*(RoReg*)0xFFFFC214U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 5) */
#define REG_SMC_PMECC10_5             (*(RoReg*)0xFFFFC218U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 5) */
#define REG_SMC_PMECC0_6              (*(RoReg*)0xFFFFC230U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 6) */
#define REG_SMC_PMECC1_6              (*(RoReg*)0xFFFFC234U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 6) */
#define REG_SMC_PMECC2_6              (*(RoReg*)0xFFFFC238U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 6) */
#define REG_SMC_PMECC3_6              (*(RoReg*)0xFFFFC23CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 6) */
#define REG_SMC_PMECC4_6              (*(RoReg*)0xFFFFC240U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 6) */
#define REG_SMC_PMECC5_6              (*(RoReg*)0xFFFFC244U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 6) */
#define REG_SMC_PMECC6_6              (*(RoReg*)0xFFFFC248U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 6) */
#define REG_SMC_PMECC7_6              (*(RoReg*)0xFFFFC24CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 6) */
#define REG_SMC_PMECC8_6              (*(RoReg*)0xFFFFC250U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 6) */
#define REG_SMC_PMECC9_6              (*(RoReg*)0xFFFFC254U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 6) */
#define REG_SMC_PMECC10_6             (*(RoReg*)0xFFFFC258U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 6) */
#define REG_SMC_PMECC0_7              (*(RoReg*)0xFFFFC270U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 7) */
#define REG_SMC_PMECC1_7              (*(RoReg*)0xFFFFC274U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 7) */
#define REG_SMC_PMECC2_7              (*(RoReg*)0xFFFFC278U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 7) */
#define REG_SMC_PMECC3_7              (*(RoReg*)0xFFFFC27CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 7) */
#define REG_SMC_PMECC4_7              (*(RoReg*)0xFFFFC280U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 7) */
#define REG_SMC_PMECC5_7              (*(RoReg*)0xFFFFC284U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 7) */
#define REG_SMC_PMECC6_7              (*(RoReg*)0xFFFFC288U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 7) */
#define REG_SMC_PMECC7_7              (*(RoReg*)0xFFFFC28CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 7) */
#define REG_SMC_PMECC8_7              (*(RoReg*)0xFFFFC290U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 7) */
#define REG_SMC_PMECC9_7              (*(RoReg*)0xFFFFC294U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 7) */
#define REG_SMC_PMECC10_7             (*(RoReg*)0xFFFFC298U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 7) */
#define REG_SMC_REM0_0                (*(RoReg*)0xFFFFC2B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 0) */
#define REG_SMC_REM1_0                (*(RoReg*)0xFFFFC2B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 0) */
#define REG_SMC_REM2_0                (*(RoReg*)0xFFFFC2B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 0) */
#define REG_SMC_REM3_0                (*(RoReg*)0xFFFFC2BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 0) */
#define REG_SMC_REM4_0                (*(RoReg*)0xFFFFC2C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 0) */
#define REG_SMC_REM5_0                (*(RoReg*)0xFFFFC2C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 0) */
#define REG_SMC_REM6_0                (*(RoReg*)0xFFFFC2C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 0) */
#define REG_SMC_REM7_0                (*(RoReg*)0xFFFFC2CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 0) */
#define REG_SMC_REM8_0                (*(RoReg*)0xFFFFC2D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 0) */
#define REG_SMC_REM9_0                (*(RoReg*)0xFFFFC2D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 0) */
#define REG_SMC_REM10_0               (*(RoReg*)0xFFFFC2D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 0) */
#define REG_SMC_REM11_0               (*(RoReg*)0xFFFFC2DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 0) */
#define REG_SMC_REM0_1                (*(RoReg*)0xFFFFC2F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 1) */
#define REG_SMC_REM1_1                (*(RoReg*)0xFFFFC2F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 1) */
#define REG_SMC_REM2_1                (*(RoReg*)0xFFFFC2F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 1) */
#define REG_SMC_REM3_1                (*(RoReg*)0xFFFFC2FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 1) */
#define REG_SMC_REM4_1                (*(RoReg*)0xFFFFC300U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 1) */
#define REG_SMC_REM5_1                (*(RoReg*)0xFFFFC304U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 1) */
#define REG_SMC_REM6_1                (*(RoReg*)0xFFFFC308U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 1) */
#define REG_SMC_REM7_1                (*(RoReg*)0xFFFFC30CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 1) */
#define REG_SMC_REM8_1                (*(RoReg*)0xFFFFC310U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 1) */
#define REG_SMC_REM9_1                (*(RoReg*)0xFFFFC314U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 1) */
#define REG_SMC_REM10_1               (*(RoReg*)0xFFFFC318U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 1) */
#define REG_SMC_REM11_1               (*(RoReg*)0xFFFFC31CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 1) */
#define REG_SMC_REM0_2                (*(RoReg*)0xFFFFC330U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 2) */
#define REG_SMC_REM1_2                (*(RoReg*)0xFFFFC334U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 2) */
#define REG_SMC_REM2_2                (*(RoReg*)0xFFFFC338U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 2) */
#define REG_SMC_REM3_2                (*(RoReg*)0xFFFFC33CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 2) */
#define REG_SMC_REM4_2                (*(RoReg*)0xFFFFC340U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 2) */
#define REG_SMC_REM5_2                (*(RoReg*)0xFFFFC344U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 2) */
#define REG_SMC_REM6_2                (*(RoReg*)0xFFFFC348U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 2) */
#define REG_SMC_REM7_2                (*(RoReg*)0xFFFFC34CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 2) */
#define REG_SMC_REM8_2                (*(RoReg*)0xFFFFC350U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 2) */
#define REG_SMC_REM9_2                (*(RoReg*)0xFFFFC354U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 2) */
#define REG_SMC_REM10_2               (*(RoReg*)0xFFFFC358U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 2) */
#define REG_SMC_REM11_2               (*(RoReg*)0xFFFFC35CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 2) */
#define REG_SMC_REM0_3                (*(RoReg*)0xFFFFC370U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 3) */
#define REG_SMC_REM1_3                (*(RoReg*)0xFFFFC374U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 3) */
#define REG_SMC_REM2_3                (*(RoReg*)0xFFFFC378U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 3) */
#define REG_SMC_REM3_3                (*(RoReg*)0xFFFFC37CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 3) */
#define REG_SMC_REM4_3                (*(RoReg*)0xFFFFC380U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 3) */
#define REG_SMC_REM5_3                (*(RoReg*)0xFFFFC384U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 3) */
#define REG_SMC_REM6_3                (*(RoReg*)0xFFFFC388U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 3) */
#define REG_SMC_REM7_3                (*(RoReg*)0xFFFFC38CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 3) */
#define REG_SMC_REM8_3                (*(RoReg*)0xFFFFC390U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 3) */
#define REG_SMC_REM9_3                (*(RoReg*)0xFFFFC394U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 3) */
#define REG_SMC_REM10_3               (*(RoReg*)0xFFFFC398U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 3) */
#define REG_SMC_REM11_3               (*(RoReg*)0xFFFFC39CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 3) */
#define REG_SMC_REM0_4                (*(RoReg*)0xFFFFC3B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 4) */
#define REG_SMC_REM1_4                (*(RoReg*)0xFFFFC3B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 4) */
#define REG_SMC_REM2_4                (*(RoReg*)0xFFFFC3B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 4) */
#define REG_SMC_REM3_4                (*(RoReg*)0xFFFFC3BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 4) */
#define REG_SMC_REM4_4                (*(RoReg*)0xFFFFC3C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 4) */
#define REG_SMC_REM5_4                (*(RoReg*)0xFFFFC3C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 4) */
#define REG_SMC_REM6_4                (*(RoReg*)0xFFFFC3C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 4) */
#define REG_SMC_REM7_4                (*(RoReg*)0xFFFFC3CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 4) */
#define REG_SMC_REM8_4                (*(RoReg*)0xFFFFC3D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 4) */
#define REG_SMC_REM9_4                (*(RoReg*)0xFFFFC3D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 4) */
#define REG_SMC_REM10_4               (*(RoReg*)0xFFFFC3D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 4) */
#define REG_SMC_REM11_4               (*(RoReg*)0xFFFFC3DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 4) */
#define REG_SMC_REM0_5                (*(RoReg*)0xFFFFC3F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 5) */
#define REG_SMC_REM1_5                (*(RoReg*)0xFFFFC3F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 5) */
#define REG_SMC_REM2_5                (*(RoReg*)0xFFFFC3F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 5) */
#define REG_SMC_REM3_5                (*(RoReg*)0xFFFFC3FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 5) */
#define REG_SMC_REM4_5                (*(RoReg*)0xFFFFC400U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 5) */
#define REG_SMC_REM5_5                (*(RoReg*)0xFFFFC404U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 5) */
#define REG_SMC_REM6_5                (*(RoReg*)0xFFFFC408U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 5) */
#define REG_SMC_REM7_5                (*(RoReg*)0xFFFFC40CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 5) */
#define REG_SMC_REM8_5                (*(RoReg*)0xFFFFC410U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 5) */
#define REG_SMC_REM9_5                (*(RoReg*)0xFFFFC414U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 5) */
#define REG_SMC_REM10_5               (*(RoReg*)0xFFFFC418U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 5) */
#define REG_SMC_REM11_5               (*(RoReg*)0xFFFFC41CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 5) */
#define REG_SMC_REM0_6                (*(RoReg*)0xFFFFC430U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 6) */
#define REG_SMC_REM1_6                (*(RoReg*)0xFFFFC434U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 6) */
#define REG_SMC_REM2_6                (*(RoReg*)0xFFFFC438U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 6) */
#define REG_SMC_REM3_6                (*(RoReg*)0xFFFFC43CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 6) */
#define REG_SMC_REM4_6                (*(RoReg*)0xFFFFC440U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 6) */
#define REG_SMC_REM5_6                (*(RoReg*)0xFFFFC444U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 6) */
#define REG_SMC_REM6_6                (*(RoReg*)0xFFFFC448U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 6) */
#define REG_SMC_REM7_6                (*(RoReg*)0xFFFFC44CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 6) */
#define REG_SMC_REM8_6                (*(RoReg*)0xFFFFC450U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 6) */
#define REG_SMC_REM9_6                (*(RoReg*)0xFFFFC454U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 6) */
#define REG_SMC_REM10_6               (*(RoReg*)0xFFFFC458U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 6) */
#define REG_SMC_REM11_6               (*(RoReg*)0xFFFFC45CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 6) */
#define REG_SMC_REM0_7                (*(RoReg*)0xFFFFC470U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 7) */
#define REG_SMC_REM1_7                (*(RoReg*)0xFFFFC474U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 7) */
#define REG_SMC_REM2_7                (*(RoReg*)0xFFFFC478U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 7) */
#define REG_SMC_REM3_7                (*(RoReg*)0xFFFFC47CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 7) */
#define REG_SMC_REM4_7                (*(RoReg*)0xFFFFC480U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 7) */
#define REG_SMC_REM5_7                (*(RoReg*)0xFFFFC484U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 7) */
#define REG_SMC_REM6_7                (*(RoReg*)0xFFFFC488U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 7) */
#define REG_SMC_REM7_7                (*(RoReg*)0xFFFFC48CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 7) */
#define REG_SMC_REM8_7                (*(RoReg*)0xFFFFC490U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 7) */
#define REG_SMC_REM9_7                (*(RoReg*)0xFFFFC494U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 7) */
#define REG_SMC_REM10_7               (*(RoReg*)0xFFFFC498U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 7) */
#define REG_SMC_REM11_7               (*(RoReg*)0xFFFFC49CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 7) */
#define REG_SMC_ELCFG                 (*(RwReg*)0xFFFFC500U) /**< \brief (SMC) PMECCError Location Configuration Register */
#define REG_SMC_ELPRIM                (*(RoReg*)0xFFFFC504U) /**< \brief (SMC) PMECC Error Location Primitive Register */
#define REG_SMC_ELEN                  (*(WoReg*)0xFFFFC508U) /**< \brief (SMC) PMECC Error Location Enable Register */
#define REG_SMC_ELDIS                 (*(WoReg*)0xFFFFC50CU) /**< \brief (SMC) PMECC Error Location Disable Register */
#define REG_SMC_ELSR                  (*(RoReg*)0xFFFFC510U) /**< \brief (SMC) PMECC Error Location Status Register */
#define REG_SMC_ELIER                 (*(WoReg*)0xFFFFC514U) /**< \brief (SMC) PMECC Error Location Interrupt Enable register */
#define REG_SMC_ELIDR                 (*(WoReg*)0xFFFFC518U) /**< \brief (SMC) PMECC Error Location Interrupt Disable Register */
#define REG_SMC_ELIMR                 (*(RoReg*)0xFFFFC51CU) /**< \brief (SMC) PMECC Error Location Interrupt Mask Register */
#define REG_SMC_ELISR                 (*(RoReg*)0xFFFFC520U) /**< \brief (SMC) PMECC Error Location Interrupt Status Register */
#define REG_SMC_SIGMA0                (*(RwReg*)0xFFFFC528U) /**< \brief (SMC) PMECC Error Location SIGMA 0 Register */
#define REG_SMC_SIGMA1                (*(RwReg*)0xFFFFC52CU) /**< \brief (SMC) PMECC Error Location SIGMA 1 Register */
#define REG_SMC_SIGMA2                (*(RwReg*)0xFFFFC530U) /**< \brief (SMC) PMECC Error Location SIGMA 2 Register */
#define REG_SMC_SIGMA3                (*(RwReg*)0xFFFFC534U) /**< \brief (SMC) PMECC Error Location SIGMA 3 Register */
#define REG_SMC_SIGMA4                (*(RwReg*)0xFFFFC538U) /**< \brief (SMC) PMECC Error Location SIGMA 4 Register */
#define REG_SMC_SIGMA5                (*(RwReg*)0xFFFFC53CU) /**< \brief (SMC) PMECC Error Location SIGMA 5 Register */
#define REG_SMC_SIGMA6                (*(RwReg*)0xFFFFC540U) /**< \brief (SMC) PMECC Error Location SIGMA 6 Register */
#define REG_SMC_SIGMA7                (*(RwReg*)0xFFFFC544U) /**< \brief (SMC) PMECC Error Location SIGMA 7 Register */
#define REG_SMC_SIGMA8                (*(RwReg*)0xFFFFC548U) /**< \brief (SMC) PMECC Error Location SIGMA 8 Register */
#define REG_SMC_SIGMA9                (*(RwReg*)0xFFFFC54CU) /**< \brief (SMC) PMECC Error Location SIGMA 9 Register */
#define REG_SMC_SIGMA10               (*(RwReg*)0xFFFFC550U) /**< \brief (SMC) PMECC Error Location SIGMA 10 Register */
#define REG_SMC_SIGMA11               (*(RwReg*)0xFFFFC554U) /**< \brief (SMC) PMECC Error Location SIGMA 11 Register */
#define REG_SMC_SIGMA12               (*(RwReg*)0xFFFFC558U) /**< \brief (SMC) PMECC Error Location SIGMA 12 Register */
#define REG_SMC_SIGMA13               (*(RwReg*)0xFFFFC55CU) /**< \brief (SMC) PMECC Error Location SIGMA 13 Register */
#define REG_SMC_SIGMA14               (*(RwReg*)0xFFFFC560U) /**< \brief (SMC) PMECC Error Location SIGMA 14 Register */
#define REG_SMC_SIGMA15               (*(RwReg*)0xFFFFC564U) /**< \brief (SMC) PMECC Error Location SIGMA 15 Register */
#define REG_SMC_SIGMA16               (*(RwReg*)0xFFFFC568U) /**< \brief (SMC) PMECC Error Location SIGMA 16 Register */
#define REG_SMC_SIGMA17               (*(RwReg*)0xFFFFC56CU) /**< \brief (SMC) PMECC Error Location SIGMA 17 Register */
#define REG_SMC_SIGMA18               (*(RwReg*)0xFFFFC570U) /**< \brief (SMC) PMECC Error Location SIGMA 18 Register */
#define REG_SMC_SIGMA19               (*(RwReg*)0xFFFFC574U) /**< \brief (SMC) PMECC Error Location SIGMA 19 Register */
#define REG_SMC_SIGMA20               (*(RwReg*)0xFFFFC578U) /**< \brief (SMC) PMECC Error Location SIGMA 20 Register */
#define REG_SMC_SIGMA21               (*(RwReg*)0xFFFFC57CU) /**< \brief (SMC) PMECC Error Location SIGMA 21 Register */
#define REG_SMC_SIGMA22               (*(RwReg*)0xFFFFC580U) /**< \brief (SMC) PMECC Error Location SIGMA 22 Register */
#define REG_SMC_SIGMA23               (*(RwReg*)0xFFFFC584U) /**< \brief (SMC) PMECC Error Location SIGMA 23 Register */
#define REG_SMC_SIGMA24               (*(RwReg*)0xFFFFC588U) /**< \brief (SMC) PMECC Error Location SIGMA 24 Register */
#define REG_SMC_ERRLOC                (*(RoReg*)0xFFFFC58CU) /**< \brief (SMC) PMECC Error Location 0 Register */
#define REG_SMC_SETUP0                (*(RwReg*)0xFFFFC600U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
#define REG_SMC_PULSE0                (*(RwReg*)0xFFFFC604U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
#define REG_SMC_CYCLE0                (*(RwReg*)0xFFFFC608U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
#define REG_SMC_TIMINGS0              (*(RwReg*)0xFFFFC60CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
#define REG_SMC_MODE0                 (*(RwReg*)0xFFFFC610U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
#define REG_SMC_SETUP1                (*(RwReg*)0xFFFFC614U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
#define REG_SMC_PULSE1                (*(RwReg*)0xFFFFC618U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
#define REG_SMC_CYCLE1                (*(RwReg*)0xFFFFC61CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
#define REG_SMC_TIMINGS1              (*(RwReg*)0xFFFFC620U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
#define REG_SMC_MODE1                 (*(RwReg*)0xFFFFC624U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
#define REG_SMC_SETUP2                (*(RwReg*)0xFFFFC628U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
#define REG_SMC_PULSE2                (*(RwReg*)0xFFFFC62CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
#define REG_SMC_CYCLE2                (*(RwReg*)0xFFFFC630U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
#define REG_SMC_TIMINGS2              (*(RwReg*)0xFFFFC634U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
#define REG_SMC_MODE2                 (*(RwReg*)0xFFFFC638U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
#define REG_SMC_SETUP3                (*(RwReg*)0xFFFFC63CU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
#define REG_SMC_PULSE3                (*(RwReg*)0xFFFFC640U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
#define REG_SMC_CYCLE3                (*(RwReg*)0xFFFFC644U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
#define REG_SMC_TIMINGS3              (*(RwReg*)0xFFFFC648U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
#define REG_SMC_MODE3                 (*(RwReg*)0xFFFFC64CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
#define REG_SMC_OCMS                  (*(RwReg*)0xFFFFC6A0U) /**< \brief (SMC) SMC OCMS Register */
#define REG_SMC_KEY1                  (*(WoReg*)0xFFFFC6A4U) /**< \brief (SMC) SMC OCMS KEY1 Register */
#define REG_SMC_KEY2                  (*(WoReg*)0xFFFFC6A8U) /**< \brief (SMC) SMC OCMS KEY2 Register */
#define REG_SMC_WPCR                  (*(WoReg*)0xFFFFC6E4U) /**< \brief (SMC) SMC Write Protection Control Register */
#define REG_SMC_WPSR                  (*(RoReg*)0xFFFFC6E8U) /**< \brief (SMC) SMC Write Protection Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for FUSE peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_FUSE_CR                            (0xFFFFE400U) /**< \brief (FUSE) Fuse Control Register */
#define REG_FUSE_MR                            (0xFFFFE404U) /**< \brief (FUSE) Fuse Mode Register */
#define REG_FUSE_IR                            (0xFFFFE408U) /**< \brief (FUSE) Fuse Index Register */
#define REG_FUSE_DR                            (0xFFFFE40CU) /**< \brief (FUSE) Fuse Data Register */
#define REG_FUSE_SR                            (0xFFFFE410U) /**< \brief (FUSE) Fuse Status Register */
#else
#define REG_FUSE_CR                   (*(WoReg*)0xFFFFE400U) /**< \brief (FUSE) Fuse Control Register */
#define REG_FUSE_MR                   (*(WoReg*)0xFFFFE404U) /**< \brief (FUSE) Fuse Mode Register */
#define REG_FUSE_IR                   (*(RwReg*)0xFFFFE408U) /**< \brief (FUSE) Fuse Index Register */
#define REG_FUSE_DR                   (*(WoReg*)0xFFFFE40CU) /**< \brief (FUSE) Fuse Data Register */
#define REG_FUSE_SR                   (*(RoReg*)0xFFFFE410U) /**< \brief (FUSE) Fuse Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for DMAC0 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_DMAC0_GCFG                         (0xFFFFE600U) /**< \brief (DMAC0) DMAC Global Configuration Register */
#define REG_DMAC0_EN                           (0xFFFFE604U) /**< \brief (DMAC0) DMAC Enable Register */
#define REG_DMAC0_SREQ                         (0xFFFFE608U) /**< \brief (DMAC0) DMAC Software Single Request Register */
#define REG_DMAC0_CREQ                         (0xFFFFE60CU) /**< \brief (DMAC0) DMAC Software Chunk Transfer Request Register */
#define REG_DMAC0_LAST                         (0xFFFFE610U) /**< \brief (DMAC0) DMAC Software Last Transfer Flag Register */
#define REG_DMAC0_EBCIER                       (0xFFFFE618U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
#define REG_DMAC0_EBCIDR                       (0xFFFFE61CU) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
#define REG_DMAC0_EBCIMR                       (0xFFFFE620U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
#define REG_DMAC0_EBCISR                       (0xFFFFE624U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
#define REG_DMAC0_CHER                         (0xFFFFE628U) /**< \brief (DMAC0) DMAC Channel Handler Enable Register */
#define REG_DMAC0_CHDR                         (0xFFFFE62CU) /**< \brief (DMAC0) DMAC Channel Handler Disable Register */
#define REG_DMAC0_CHSR                         (0xFFFFE630U) /**< \brief (DMAC0) DMAC Channel Handler Status Register */
#define REG_DMAC0_SADDR0                       (0xFFFFE63CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 0) */
#define REG_DMAC0_DADDR0                       (0xFFFFE640U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 0) */
#define REG_DMAC0_DSCR0                        (0xFFFFE644U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 0) */
#define REG_DMAC0_CTRLA0                       (0xFFFFE648U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 0) */
#define REG_DMAC0_CTRLB0                       (0xFFFFE64CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 0) */
#define REG_DMAC0_CFG0                         (0xFFFFE650U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 0) */
#define REG_DMAC0_SPIP0                        (0xFFFFE654U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */
#define REG_DMAC0_DPIP0                        (0xFFFFE658U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */
#define REG_DMAC0_SADDR1                       (0xFFFFE664U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 1) */
#define REG_DMAC0_DADDR1                       (0xFFFFE668U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 1) */
#define REG_DMAC0_DSCR1                        (0xFFFFE66CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 1) */
#define REG_DMAC0_CTRLA1                       (0xFFFFE670U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 1) */
#define REG_DMAC0_CTRLB1                       (0xFFFFE674U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 1) */
#define REG_DMAC0_CFG1                         (0xFFFFE678U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 1) */
#define REG_DMAC0_SPIP1                        (0xFFFFE67CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */
#define REG_DMAC0_DPIP1                        (0xFFFFE680U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */
#define REG_DMAC0_SADDR2                       (0xFFFFE68CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 2) */
#define REG_DMAC0_DADDR2                       (0xFFFFE690U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 2) */
#define REG_DMAC0_DSCR2                        (0xFFFFE694U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 2) */
#define REG_DMAC0_CTRLA2                       (0xFFFFE698U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 2) */
#define REG_DMAC0_CTRLB2                       (0xFFFFE69CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 2) */
#define REG_DMAC0_CFG2                         (0xFFFFE6A0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 2) */
#define REG_DMAC0_SPIP2                        (0xFFFFE6A4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */
#define REG_DMAC0_DPIP2                        (0xFFFFE6A8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */
#define REG_DMAC0_SADDR3                       (0xFFFFE6B4U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 3) */
#define REG_DMAC0_DADDR3                       (0xFFFFE6B8U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 3) */
#define REG_DMAC0_DSCR3                        (0xFFFFE6BCU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 3) */
#define REG_DMAC0_CTRLA3                       (0xFFFFE6C0U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 3) */
#define REG_DMAC0_CTRLB3                       (0xFFFFE6C4U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 3) */
#define REG_DMAC0_CFG3                         (0xFFFFE6C8U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 3) */
#define REG_DMAC0_SPIP3                        (0xFFFFE6CCU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */
#define REG_DMAC0_DPIP3                        (0xFFFFE6D0U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */
#define REG_DMAC0_SADDR4                       (0xFFFFE6DCU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 4) */
#define REG_DMAC0_DADDR4                       (0xFFFFE6E0U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 4) */
#define REG_DMAC0_DSCR4                        (0xFFFFE6E4U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 4) */
#define REG_DMAC0_CTRLA4                       (0xFFFFE6E8U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 4) */
#define REG_DMAC0_CTRLB4                       (0xFFFFE6ECU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 4) */
#define REG_DMAC0_CFG4                         (0xFFFFE6F0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 4) */
#define REG_DMAC0_SPIP4                        (0xFFFFE6F4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */
#define REG_DMAC0_DPIP4                        (0xFFFFE6F8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */
#define REG_DMAC0_SADDR5                       (0xFFFFE704U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 5) */
#define REG_DMAC0_DADDR5                       (0xFFFFE708U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 5) */
#define REG_DMAC0_DSCR5                        (0xFFFFE70CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 5) */
#define REG_DMAC0_CTRLA5                       (0xFFFFE710U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 5) */
#define REG_DMAC0_CTRLB5                       (0xFFFFE714U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 5) */
#define REG_DMAC0_CFG5                         (0xFFFFE718U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 5) */
#define REG_DMAC0_SPIP5                        (0xFFFFE71CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */
#define REG_DMAC0_DPIP5                        (0xFFFFE720U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */
#define REG_DMAC0_SADDR6                       (0xFFFFE72CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 6) */
#define REG_DMAC0_DADDR6                       (0xFFFFE730U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 6) */
#define REG_DMAC0_DSCR6                        (0xFFFFE734U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 6) */
#define REG_DMAC0_CTRLA6                       (0xFFFFE738U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 6) */
#define REG_DMAC0_CTRLB6                       (0xFFFFE73CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 6) */
#define REG_DMAC0_CFG6                         (0xFFFFE740U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 6) */
#define REG_DMAC0_SPIP6                        (0xFFFFE744U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */
#define REG_DMAC0_DPIP6                        (0xFFFFE748U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */
#define REG_DMAC0_SADDR7                       (0xFFFFE754U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 7) */
#define REG_DMAC0_DADDR7                       (0xFFFFE758U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 7) */
#define REG_DMAC0_DSCR7                        (0xFFFFE75CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 7) */
#define REG_DMAC0_CTRLA7                       (0xFFFFE760U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 7) */
#define REG_DMAC0_CTRLB7                       (0xFFFFE764U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 7) */
#define REG_DMAC0_CFG7                         (0xFFFFE768U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 7) */
#define REG_DMAC0_SPIP7                        (0xFFFFE76CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */
#define REG_DMAC0_DPIP7                        (0xFFFFE770U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */
#define REG_DMAC0_WPMR                         (0xFFFFE7E4U) /**< \brief (DMAC0) DMAC Write Protect Mode Register */
#define REG_DMAC0_WPSR                         (0xFFFFE7E8U) /**< \brief (DMAC0) DMAC Write Protect Status Register */
#else
#define REG_DMAC0_GCFG                (*(RwReg*)0xFFFFE600U) /**< \brief (DMAC0) DMAC Global Configuration Register */
#define REG_DMAC0_EN                  (*(RwReg*)0xFFFFE604U) /**< \brief (DMAC0) DMAC Enable Register */
#define REG_DMAC0_SREQ                (*(RwReg*)0xFFFFE608U) /**< \brief (DMAC0) DMAC Software Single Request Register */
#define REG_DMAC0_CREQ                (*(RwReg*)0xFFFFE60CU) /**< \brief (DMAC0) DMAC Software Chunk Transfer Request Register */
#define REG_DMAC0_LAST                (*(RwReg*)0xFFFFE610U) /**< \brief (DMAC0) DMAC Software Last Transfer Flag Register */
#define REG_DMAC0_EBCIER              (*(WoReg*)0xFFFFE618U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
#define REG_DMAC0_EBCIDR              (*(WoReg*)0xFFFFE61CU) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
#define REG_DMAC0_EBCIMR              (*(RoReg*)0xFFFFE620U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
#define REG_DMAC0_EBCISR              (*(RoReg*)0xFFFFE624U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
#define REG_DMAC0_CHER                (*(WoReg*)0xFFFFE628U) /**< \brief (DMAC0) DMAC Channel Handler Enable Register */
#define REG_DMAC0_CHDR                (*(WoReg*)0xFFFFE62CU) /**< \brief (DMAC0) DMAC Channel Handler Disable Register */
#define REG_DMAC0_CHSR                (*(RoReg*)0xFFFFE630U) /**< \brief (DMAC0) DMAC Channel Handler Status Register */
#define REG_DMAC0_SADDR0              (*(RwReg*)0xFFFFE63CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 0) */
#define REG_DMAC0_DADDR0              (*(RwReg*)0xFFFFE640U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 0) */
#define REG_DMAC0_DSCR0               (*(RwReg*)0xFFFFE644U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 0) */
#define REG_DMAC0_CTRLA0              (*(RwReg*)0xFFFFE648U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 0) */
#define REG_DMAC0_CTRLB0              (*(RwReg*)0xFFFFE64CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 0) */
#define REG_DMAC0_CFG0                (*(RwReg*)0xFFFFE650U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 0) */
#define REG_DMAC0_SPIP0               (*(RwReg*)0xFFFFE654U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */
#define REG_DMAC0_DPIP0               (*(RwReg*)0xFFFFE658U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */
#define REG_DMAC0_SADDR1              (*(RwReg*)0xFFFFE664U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 1) */
#define REG_DMAC0_DADDR1              (*(RwReg*)0xFFFFE668U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 1) */
#define REG_DMAC0_DSCR1               (*(RwReg*)0xFFFFE66CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 1) */
#define REG_DMAC0_CTRLA1              (*(RwReg*)0xFFFFE670U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 1) */
#define REG_DMAC0_CTRLB1              (*(RwReg*)0xFFFFE674U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 1) */
#define REG_DMAC0_CFG1                (*(RwReg*)0xFFFFE678U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 1) */
#define REG_DMAC0_SPIP1               (*(RwReg*)0xFFFFE67CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */
#define REG_DMAC0_DPIP1               (*(RwReg*)0xFFFFE680U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */
#define REG_DMAC0_SADDR2              (*(RwReg*)0xFFFFE68CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 2) */
#define REG_DMAC0_DADDR2              (*(RwReg*)0xFFFFE690U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 2) */
#define REG_DMAC0_DSCR2               (*(RwReg*)0xFFFFE694U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 2) */
#define REG_DMAC0_CTRLA2              (*(RwReg*)0xFFFFE698U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 2) */
#define REG_DMAC0_CTRLB2              (*(RwReg*)0xFFFFE69CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 2) */
#define REG_DMAC0_CFG2                (*(RwReg*)0xFFFFE6A0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 2) */
#define REG_DMAC0_SPIP2               (*(RwReg*)0xFFFFE6A4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */
#define REG_DMAC0_DPIP2               (*(RwReg*)0xFFFFE6A8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */
#define REG_DMAC0_SADDR3              (*(RwReg*)0xFFFFE6B4U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 3) */
#define REG_DMAC0_DADDR3              (*(RwReg*)0xFFFFE6B8U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 3) */
#define REG_DMAC0_DSCR3               (*(RwReg*)0xFFFFE6BCU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 3) */
#define REG_DMAC0_CTRLA3              (*(RwReg*)0xFFFFE6C0U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 3) */
#define REG_DMAC0_CTRLB3              (*(RwReg*)0xFFFFE6C4U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 3) */
#define REG_DMAC0_CFG3                (*(RwReg*)0xFFFFE6C8U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 3) */
#define REG_DMAC0_SPIP3               (*(RwReg*)0xFFFFE6CCU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */
#define REG_DMAC0_DPIP3               (*(RwReg*)0xFFFFE6D0U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */
#define REG_DMAC0_SADDR4              (*(RwReg*)0xFFFFE6DCU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 4) */
#define REG_DMAC0_DADDR4              (*(RwReg*)0xFFFFE6E0U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 4) */
#define REG_DMAC0_DSCR4               (*(RwReg*)0xFFFFE6E4U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 4) */
#define REG_DMAC0_CTRLA4              (*(RwReg*)0xFFFFE6E8U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 4) */
#define REG_DMAC0_CTRLB4              (*(RwReg*)0xFFFFE6ECU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 4) */
#define REG_DMAC0_CFG4                (*(RwReg*)0xFFFFE6F0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 4) */
#define REG_DMAC0_SPIP4               (*(RwReg*)0xFFFFE6F4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */
#define REG_DMAC0_DPIP4               (*(RwReg*)0xFFFFE6F8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */
#define REG_DMAC0_SADDR5              (*(RwReg*)0xFFFFE704U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 5) */
#define REG_DMAC0_DADDR5              (*(RwReg*)0xFFFFE708U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 5) */
#define REG_DMAC0_DSCR5               (*(RwReg*)0xFFFFE70CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 5) */
#define REG_DMAC0_CTRLA5              (*(RwReg*)0xFFFFE710U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 5) */
#define REG_DMAC0_CTRLB5              (*(RwReg*)0xFFFFE714U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 5) */
#define REG_DMAC0_CFG5                (*(RwReg*)0xFFFFE718U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 5) */
#define REG_DMAC0_SPIP5               (*(RwReg*)0xFFFFE71CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */
#define REG_DMAC0_DPIP5               (*(RwReg*)0xFFFFE720U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */
#define REG_DMAC0_SADDR6              (*(RwReg*)0xFFFFE72CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 6) */
#define REG_DMAC0_DADDR6              (*(RwReg*)0xFFFFE730U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 6) */
#define REG_DMAC0_DSCR6               (*(RwReg*)0xFFFFE734U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 6) */
#define REG_DMAC0_CTRLA6              (*(RwReg*)0xFFFFE738U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 6) */
#define REG_DMAC0_CTRLB6              (*(RwReg*)0xFFFFE73CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 6) */
#define REG_DMAC0_CFG6                (*(RwReg*)0xFFFFE740U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 6) */
#define REG_DMAC0_SPIP6               (*(RwReg*)0xFFFFE744U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */
#define REG_DMAC0_DPIP6               (*(RwReg*)0xFFFFE748U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */
#define REG_DMAC0_SADDR7              (*(RwReg*)0xFFFFE754U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 7) */
#define REG_DMAC0_DADDR7              (*(RwReg*)0xFFFFE758U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 7) */
#define REG_DMAC0_DSCR7               (*(RwReg*)0xFFFFE75CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 7) */
#define REG_DMAC0_CTRLA7              (*(RwReg*)0xFFFFE760U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 7) */
#define REG_DMAC0_CTRLB7              (*(RwReg*)0xFFFFE764U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 7) */
#define REG_DMAC0_CFG7                (*(RwReg*)0xFFFFE768U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 7) */
#define REG_DMAC0_SPIP7               (*(RwReg*)0xFFFFE76CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */
#define REG_DMAC0_DPIP7               (*(RwReg*)0xFFFFE770U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */
#define REG_DMAC0_WPMR                (*(RwReg*)0xFFFFE7E4U) /**< \brief (DMAC0) DMAC Write Protect Mode Register */
#define REG_DMAC0_WPSR                (*(RoReg*)0xFFFFE7E8U) /**< \brief (DMAC0) DMAC Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for DMAC1 peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_DMAC1_GCFG                         (0xFFFFE800U) /**< \brief (DMAC1) DMAC Global Configuration Register */
#define REG_DMAC1_EN                           (0xFFFFE804U) /**< \brief (DMAC1) DMAC Enable Register */
#define REG_DMAC1_SREQ                         (0xFFFFE808U) /**< \brief (DMAC1) DMAC Software Single Request Register */
#define REG_DMAC1_CREQ                         (0xFFFFE80CU) /**< \brief (DMAC1) DMAC Software Chunk Transfer Request Register */
#define REG_DMAC1_LAST                         (0xFFFFE810U) /**< \brief (DMAC1) DMAC Software Last Transfer Flag Register */
#define REG_DMAC1_EBCIER                       (0xFFFFE818U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
#define REG_DMAC1_EBCIDR                       (0xFFFFE81CU) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
#define REG_DMAC1_EBCIMR                       (0xFFFFE820U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
#define REG_DMAC1_EBCISR                       (0xFFFFE824U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
#define REG_DMAC1_CHER                         (0xFFFFE828U) /**< \brief (DMAC1) DMAC Channel Handler Enable Register */
#define REG_DMAC1_CHDR                         (0xFFFFE82CU) /**< \brief (DMAC1) DMAC Channel Handler Disable Register */
#define REG_DMAC1_CHSR                         (0xFFFFE830U) /**< \brief (DMAC1) DMAC Channel Handler Status Register */
#define REG_DMAC1_SADDR0                       (0xFFFFE83CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 0) */
#define REG_DMAC1_DADDR0                       (0xFFFFE840U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 0) */
#define REG_DMAC1_DSCR0                        (0xFFFFE844U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 0) */
#define REG_DMAC1_CTRLA0                       (0xFFFFE848U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 0) */
#define REG_DMAC1_CTRLB0                       (0xFFFFE84CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 0) */
#define REG_DMAC1_CFG0                         (0xFFFFE850U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 0) */
#define REG_DMAC1_SPIP0                        (0xFFFFE854U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */
#define REG_DMAC1_DPIP0                        (0xFFFFE858U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */
#define REG_DMAC1_SADDR1                       (0xFFFFE864U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 1) */
#define REG_DMAC1_DADDR1                       (0xFFFFE868U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 1) */
#define REG_DMAC1_DSCR1                        (0xFFFFE86CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 1) */
#define REG_DMAC1_CTRLA1                       (0xFFFFE870U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 1) */
#define REG_DMAC1_CTRLB1                       (0xFFFFE874U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 1) */
#define REG_DMAC1_CFG1                         (0xFFFFE878U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 1) */
#define REG_DMAC1_SPIP1                        (0xFFFFE87CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */
#define REG_DMAC1_DPIP1                        (0xFFFFE880U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */
#define REG_DMAC1_SADDR2                       (0xFFFFE88CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 2) */
#define REG_DMAC1_DADDR2                       (0xFFFFE890U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 2) */
#define REG_DMAC1_DSCR2                        (0xFFFFE894U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 2) */
#define REG_DMAC1_CTRLA2                       (0xFFFFE898U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 2) */
#define REG_DMAC1_CTRLB2                       (0xFFFFE89CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 2) */
#define REG_DMAC1_CFG2                         (0xFFFFE8A0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 2) */
#define REG_DMAC1_SPIP2                        (0xFFFFE8A4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */
#define REG_DMAC1_DPIP2                        (0xFFFFE8A8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */
#define REG_DMAC1_SADDR3                       (0xFFFFE8B4U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 3) */
#define REG_DMAC1_DADDR3                       (0xFFFFE8B8U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 3) */
#define REG_DMAC1_DSCR3                        (0xFFFFE8BCU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 3) */
#define REG_DMAC1_CTRLA3                       (0xFFFFE8C0U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 3) */
#define REG_DMAC1_CTRLB3                       (0xFFFFE8C4U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 3) */
#define REG_DMAC1_CFG3                         (0xFFFFE8C8U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 3) */
#define REG_DMAC1_SPIP3                        (0xFFFFE8CCU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */
#define REG_DMAC1_DPIP3                        (0xFFFFE8D0U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */
#define REG_DMAC1_SADDR4                       (0xFFFFE8DCU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 4) */
#define REG_DMAC1_DADDR4                       (0xFFFFE8E0U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 4) */
#define REG_DMAC1_DSCR4                        (0xFFFFE8E4U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 4) */
#define REG_DMAC1_CTRLA4                       (0xFFFFE8E8U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 4) */
#define REG_DMAC1_CTRLB4                       (0xFFFFE8ECU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 4) */
#define REG_DMAC1_CFG4                         (0xFFFFE8F0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 4) */
#define REG_DMAC1_SPIP4                        (0xFFFFE8F4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */
#define REG_DMAC1_DPIP4                        (0xFFFFE8F8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */
#define REG_DMAC1_SADDR5                       (0xFFFFE904U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 5) */
#define REG_DMAC1_DADDR5                       (0xFFFFE908U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 5) */
#define REG_DMAC1_DSCR5                        (0xFFFFE90CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 5) */
#define REG_DMAC1_CTRLA5                       (0xFFFFE910U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 5) */
#define REG_DMAC1_CTRLB5                       (0xFFFFE914U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 5) */
#define REG_DMAC1_CFG5                         (0xFFFFE918U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 5) */
#define REG_DMAC1_SPIP5                        (0xFFFFE91CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */
#define REG_DMAC1_DPIP5                        (0xFFFFE920U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */
#define REG_DMAC1_SADDR6                       (0xFFFFE92CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 6) */
#define REG_DMAC1_DADDR6                       (0xFFFFE930U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 6) */
#define REG_DMAC1_DSCR6                        (0xFFFFE934U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 6) */
#define REG_DMAC1_CTRLA6                       (0xFFFFE938U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 6) */
#define REG_DMAC1_CTRLB6                       (0xFFFFE93CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 6) */
#define REG_DMAC1_CFG6                         (0xFFFFE940U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 6) */
#define REG_DMAC1_SPIP6                        (0xFFFFE944U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */
#define REG_DMAC1_DPIP6                        (0xFFFFE948U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */
#define REG_DMAC1_SADDR7                       (0xFFFFE954U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 7) */
#define REG_DMAC1_DADDR7                       (0xFFFFE958U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 7) */
#define REG_DMAC1_DSCR7                        (0xFFFFE95CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 7) */
#define REG_DMAC1_CTRLA7                       (0xFFFFE960U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 7) */
#define REG_DMAC1_CTRLB7                       (0xFFFFE964U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 7) */
#define REG_DMAC1_CFG7                         (0xFFFFE968U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 7) */
#define REG_DMAC1_SPIP7                        (0xFFFFE96CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */
#define REG_DMAC1_DPIP7                        (0xFFFFE970U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */
#define REG_DMAC1_WPMR                         (0xFFFFE9E4U) /**< \brief (DMAC1) DMAC Write Protect Mode Register */
#define REG_DMAC1_WPSR                         (0xFFFFE9E8U) /**< \brief (DMAC1) DMAC Write Protect Status Register */
#else
#define REG_DMAC1_GCFG                (*(RwReg*)0xFFFFE800U) /**< \brief (DMAC1) DMAC Global Configuration Register */
#define REG_DMAC1_EN                  (*(RwReg*)0xFFFFE804U) /**< \brief (DMAC1) DMAC Enable Register */
#define REG_DMAC1_SREQ                (*(RwReg*)0xFFFFE808U) /**< \brief (DMAC1) DMAC Software Single Request Register */
#define REG_DMAC1_CREQ                (*(RwReg*)0xFFFFE80CU) /**< \brief (DMAC1) DMAC Software Chunk Transfer Request Register */
#define REG_DMAC1_LAST                (*(RwReg*)0xFFFFE810U) /**< \brief (DMAC1) DMAC Software Last Transfer Flag Register */
#define REG_DMAC1_EBCIER              (*(WoReg*)0xFFFFE818U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
#define REG_DMAC1_EBCIDR              (*(WoReg*)0xFFFFE81CU) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
#define REG_DMAC1_EBCIMR              (*(RoReg*)0xFFFFE820U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
#define REG_DMAC1_EBCISR              (*(RoReg*)0xFFFFE824U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
#define REG_DMAC1_CHER                (*(WoReg*)0xFFFFE828U) /**< \brief (DMAC1) DMAC Channel Handler Enable Register */
#define REG_DMAC1_CHDR                (*(WoReg*)0xFFFFE82CU) /**< \brief (DMAC1) DMAC Channel Handler Disable Register */
#define REG_DMAC1_CHSR                (*(RoReg*)0xFFFFE830U) /**< \brief (DMAC1) DMAC Channel Handler Status Register */
#define REG_DMAC1_SADDR0              (*(RwReg*)0xFFFFE83CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 0) */
#define REG_DMAC1_DADDR0              (*(RwReg*)0xFFFFE840U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 0) */
#define REG_DMAC1_DSCR0               (*(RwReg*)0xFFFFE844U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 0) */
#define REG_DMAC1_CTRLA0              (*(RwReg*)0xFFFFE848U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 0) */
#define REG_DMAC1_CTRLB0              (*(RwReg*)0xFFFFE84CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 0) */
#define REG_DMAC1_CFG0                (*(RwReg*)0xFFFFE850U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 0) */
#define REG_DMAC1_SPIP0               (*(RwReg*)0xFFFFE854U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */
#define REG_DMAC1_DPIP0               (*(RwReg*)0xFFFFE858U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */
#define REG_DMAC1_SADDR1              (*(RwReg*)0xFFFFE864U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 1) */
#define REG_DMAC1_DADDR1              (*(RwReg*)0xFFFFE868U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 1) */
#define REG_DMAC1_DSCR1               (*(RwReg*)0xFFFFE86CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 1) */
#define REG_DMAC1_CTRLA1              (*(RwReg*)0xFFFFE870U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 1) */
#define REG_DMAC1_CTRLB1              (*(RwReg*)0xFFFFE874U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 1) */
#define REG_DMAC1_CFG1                (*(RwReg*)0xFFFFE878U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 1) */
#define REG_DMAC1_SPIP1               (*(RwReg*)0xFFFFE87CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */
#define REG_DMAC1_DPIP1               (*(RwReg*)0xFFFFE880U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */
#define REG_DMAC1_SADDR2              (*(RwReg*)0xFFFFE88CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 2) */
#define REG_DMAC1_DADDR2              (*(RwReg*)0xFFFFE890U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 2) */
#define REG_DMAC1_DSCR2               (*(RwReg*)0xFFFFE894U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 2) */
#define REG_DMAC1_CTRLA2              (*(RwReg*)0xFFFFE898U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 2) */
#define REG_DMAC1_CTRLB2              (*(RwReg*)0xFFFFE89CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 2) */
#define REG_DMAC1_CFG2                (*(RwReg*)0xFFFFE8A0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 2) */
#define REG_DMAC1_SPIP2               (*(RwReg*)0xFFFFE8A4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */
#define REG_DMAC1_DPIP2               (*(RwReg*)0xFFFFE8A8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */
#define REG_DMAC1_SADDR3              (*(RwReg*)0xFFFFE8B4U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 3) */
#define REG_DMAC1_DADDR3              (*(RwReg*)0xFFFFE8B8U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 3) */
#define REG_DMAC1_DSCR3               (*(RwReg*)0xFFFFE8BCU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 3) */
#define REG_DMAC1_CTRLA3              (*(RwReg*)0xFFFFE8C0U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 3) */
#define REG_DMAC1_CTRLB3              (*(RwReg*)0xFFFFE8C4U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 3) */
#define REG_DMAC1_CFG3                (*(RwReg*)0xFFFFE8C8U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 3) */
#define REG_DMAC1_SPIP3               (*(RwReg*)0xFFFFE8CCU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */
#define REG_DMAC1_DPIP3               (*(RwReg*)0xFFFFE8D0U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */
#define REG_DMAC1_SADDR4              (*(RwReg*)0xFFFFE8DCU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 4) */
#define REG_DMAC1_DADDR4              (*(RwReg*)0xFFFFE8E0U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 4) */
#define REG_DMAC1_DSCR4               (*(RwReg*)0xFFFFE8E4U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 4) */
#define REG_DMAC1_CTRLA4              (*(RwReg*)0xFFFFE8E8U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 4) */
#define REG_DMAC1_CTRLB4              (*(RwReg*)0xFFFFE8ECU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 4) */
#define REG_DMAC1_CFG4                (*(RwReg*)0xFFFFE8F0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 4) */
#define REG_DMAC1_SPIP4               (*(RwReg*)0xFFFFE8F4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */
#define REG_DMAC1_DPIP4               (*(RwReg*)0xFFFFE8F8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */
#define REG_DMAC1_SADDR5              (*(RwReg*)0xFFFFE904U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 5) */
#define REG_DMAC1_DADDR5              (*(RwReg*)0xFFFFE908U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 5) */
#define REG_DMAC1_DSCR5               (*(RwReg*)0xFFFFE90CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 5) */
#define REG_DMAC1_CTRLA5              (*(RwReg*)0xFFFFE910U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 5) */
#define REG_DMAC1_CTRLB5              (*(RwReg*)0xFFFFE914U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 5) */
#define REG_DMAC1_CFG5                (*(RwReg*)0xFFFFE918U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 5) */
#define REG_DMAC1_SPIP5               (*(RwReg*)0xFFFFE91CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */
#define REG_DMAC1_DPIP5               (*(RwReg*)0xFFFFE920U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */
#define REG_DMAC1_SADDR6              (*(RwReg*)0xFFFFE92CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 6) */
#define REG_DMAC1_DADDR6              (*(RwReg*)0xFFFFE930U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 6) */
#define REG_DMAC1_DSCR6               (*(RwReg*)0xFFFFE934U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 6) */
#define REG_DMAC1_CTRLA6              (*(RwReg*)0xFFFFE938U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 6) */
#define REG_DMAC1_CTRLB6              (*(RwReg*)0xFFFFE93CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 6) */
#define REG_DMAC1_CFG6                (*(RwReg*)0xFFFFE940U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 6) */
#define REG_DMAC1_SPIP6               (*(RwReg*)0xFFFFE944U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */
#define REG_DMAC1_DPIP6               (*(RwReg*)0xFFFFE948U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */
#define REG_DMAC1_SADDR7              (*(RwReg*)0xFFFFE954U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 7) */
#define REG_DMAC1_DADDR7              (*(RwReg*)0xFFFFE958U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 7) */
#define REG_DMAC1_DSCR7               (*(RwReg*)0xFFFFE95CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 7) */
#define REG_DMAC1_CTRLA7              (*(RwReg*)0xFFFFE960U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 7) */
#define REG_DMAC1_CTRLB7              (*(RwReg*)0xFFFFE964U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 7) */
#define REG_DMAC1_CFG7                (*(RwReg*)0xFFFFE968U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 7) */
#define REG_DMAC1_SPIP7               (*(RwReg*)0xFFFFE96CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */
#define REG_DMAC1_DPIP7               (*(RwReg*)0xFFFFE970U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */
#define REG_DMAC1_WPMR                (*(RwReg*)0xFFFFE9E4U) /**< \brief (DMAC1) DMAC Write Protect Mode Register */
#define REG_DMAC1_WPSR                (*(RoReg*)0xFFFFE9E8U) /**< \brief (DMAC1) DMAC Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for MPDDRC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_MPDDRC_MR                          (0xFFFFEA00U) /**< \brief (MPDDRC) MPDDRC Mode Register */
#define REG_MPDDRC_RTR                         (0xFFFFEA04U) /**< \brief (MPDDRC) MPDDRC Refresh Timer Register */
#define REG_MPDDRC_CR                          (0xFFFFEA08U) /**< \brief (MPDDRC) MPDDRC Configuration Register */
#define REG_MPDDRC_TPR0                        (0xFFFFEA0CU) /**< \brief (MPDDRC) MPDDRC Timing Parameter 0 Register */
#define REG_MPDDRC_TPR1                        (0xFFFFEA10U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 1 Register */
#define REG_MPDDRC_TPR2                        (0xFFFFEA14U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 2 Register */
#define REG_MPDDRC_LPR                         (0xFFFFEA1CU) /**< \brief (MPDDRC) MPDDRC Low-power Register */
#define REG_MPDDRC_MD                          (0xFFFFEA20U) /**< \brief (MPDDRC) MPDDRC Memory Device Register */
#define REG_MPDDRC_LPDDR2_LPR                  (0xFFFFEA28U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Low-power Register */
#define REG_MPDDRC_LPDDR2_CAL_MR4              (0xFFFFEA2CU) /**< \brief (MPDDRC) MPDDRC LPDDR2 Calibration and MR4 Register */
#define REG_MPDDRC_LPDDR2_TIM_CAL              (0xFFFFEA30U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Timing Calibration Register */
#define REG_MPDDRC_IO_CALIBR                   (0xFFFFEA34U) /**< \brief (MPDDRC) MPDDRC IO Calibration */
#define REG_MPDDRC_OCMS                        (0xFFFFEA38U) /**< \brief (MPDDRC) MPDDRC OCMS Register */
#define REG_MPDDRC_OCMS_KEY1                   (0xFFFFEA3CU) /**< \brief (MPDDRC) MPDDRC OCMS KEY1 Register */
#define REG_MPDDRC_OCMS_KEY2                   (0xFFFFEA40U) /**< \brief (MPDDRC) MPDDRC OCMS KEY2 Register */
#define REG_MPDDRC_DLL_MOR                     (0xFFFFEA74U) /**< \brief (MPDDRC) MPDDRC DLL Master Offset Register */
#define REG_MPDDRC_DLL_SOR                     (0xFFFFEA78U) /**< \brief (MPDDRC) MPDDRC DLL Slave Offset Register */
#define REG_MPDDRC_DLL_MSR                     (0xFFFFEA7CU) /**< \brief (MPDDRC) MPDDRC DLL Master Status Register */
#define REG_MPDDRC_DLL_S0SR                    (0xFFFFEA80U) /**< \brief (MPDDRC) MPDDRC DLL Slave 0 Status Register */
#define REG_MPDDRC_DLL_S1SR                    (0xFFFFEA84U) /**< \brief (MPDDRC) MPDDRC DLL Slave 1 Status Register */
#define REG_MPDDRC_WPCR                        (0xFFFFEAE4U) /**< \brief (MPDDRC) MPDDRC Write Protect Control Register */
#define REG_MPDDRC_WPSR                        (0xFFFFEAE8U) /**< \brief (MPDDRC) MPDDRC Write Protect Status Register */
#else
#define REG_MPDDRC_MR                 (*(RwReg*)0xFFFFEA00U) /**< \brief (MPDDRC) MPDDRC Mode Register */
#define REG_MPDDRC_RTR                (*(RwReg*)0xFFFFEA04U) /**< \brief (MPDDRC) MPDDRC Refresh Timer Register */
#define REG_MPDDRC_CR                 (*(RwReg*)0xFFFFEA08U) /**< \brief (MPDDRC) MPDDRC Configuration Register */
#define REG_MPDDRC_TPR0               (*(RwReg*)0xFFFFEA0CU) /**< \brief (MPDDRC) MPDDRC Timing Parameter 0 Register */
#define REG_MPDDRC_TPR1               (*(RwReg*)0xFFFFEA10U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 1 Register */
#define REG_MPDDRC_TPR2               (*(RwReg*)0xFFFFEA14U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 2 Register */
#define REG_MPDDRC_LPR                (*(RwReg*)0xFFFFEA1CU) /**< \brief (MPDDRC) MPDDRC Low-power Register */
#define REG_MPDDRC_MD                 (*(RwReg*)0xFFFFEA20U) /**< \brief (MPDDRC) MPDDRC Memory Device Register */
#define REG_MPDDRC_LPDDR2_LPR         (*(RwReg*)0xFFFFEA28U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Low-power Register */
#define REG_MPDDRC_LPDDR2_CAL_MR4     (*(RwReg*)0xFFFFEA2CU) /**< \brief (MPDDRC) MPDDRC LPDDR2 Calibration and MR4 Register */
#define REG_MPDDRC_LPDDR2_TIM_CAL     (*(RwReg*)0xFFFFEA30U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Timing Calibration Register */
#define REG_MPDDRC_IO_CALIBR          (*(RwReg*)0xFFFFEA34U) /**< \brief (MPDDRC) MPDDRC IO Calibration */
#define REG_MPDDRC_OCMS               (*(RwReg*)0xFFFFEA38U) /**< \brief (MPDDRC) MPDDRC OCMS Register */
#define REG_MPDDRC_OCMS_KEY1          (*(WoReg*)0xFFFFEA3CU) /**< \brief (MPDDRC) MPDDRC OCMS KEY1 Register */
#define REG_MPDDRC_OCMS_KEY2          (*(WoReg*)0xFFFFEA40U) /**< \brief (MPDDRC) MPDDRC OCMS KEY2 Register */
#define REG_MPDDRC_DLL_MOR            (*(RwReg*)0xFFFFEA74U) /**< \brief (MPDDRC) MPDDRC DLL Master Offset Register */
#define REG_MPDDRC_DLL_SOR            (*(RwReg*)0xFFFFEA78U) /**< \brief (MPDDRC) MPDDRC DLL Slave Offset Register */
#define REG_MPDDRC_DLL_MSR            (*(RoReg*)0xFFFFEA7CU) /**< \brief (MPDDRC) MPDDRC DLL Master Status Register */
#define REG_MPDDRC_DLL_S0SR           (*(RoReg*)0xFFFFEA80U) /**< \brief (MPDDRC) MPDDRC DLL Slave 0 Status Register */
#define REG_MPDDRC_DLL_S1SR           (*(RoReg*)0xFFFFEA84U) /**< \brief (MPDDRC) MPDDRC DLL Slave 1 Status Register */
#define REG_MPDDRC_WPCR               (*(RwReg*)0xFFFFEAE4U) /**< \brief (MPDDRC) MPDDRC Write Protect Control Register */
#define REG_MPDDRC_WPSR               (*(RoReg*)0xFFFFEAE8U) /**< \brief (MPDDRC) MPDDRC Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for MATRIX peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_MATRIX_MCFG                        (0xFFFFEC00U) /**< \brief (MATRIX) Master Configuration Register */
#define REG_MATRIX_SCFG                        (0xFFFFEC40U) /**< \brief (MATRIX) Slave Configuration Register */
#define REG_MATRIX_PRAS0                       (0xFFFFEC80U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
#define REG_MATRIX_PRBS0                       (0xFFFFEC84U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
#define REG_MATRIX_PRAS1                       (0xFFFFEC88U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
#define REG_MATRIX_PRBS1                       (0xFFFFEC8CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
#define REG_MATRIX_PRAS2                       (0xFFFFEC90U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
#define REG_MATRIX_PRBS2                       (0xFFFFEC94U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
#define REG_MATRIX_PRAS3                       (0xFFFFEC98U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
#define REG_MATRIX_PRBS3                       (0xFFFFEC9CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
#define REG_MATRIX_PRAS4                       (0xFFFFECA0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
#define REG_MATRIX_PRBS4                       (0xFFFFECA4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
#define REG_MATRIX_PRAS5                       (0xFFFFECA8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
#define REG_MATRIX_PRBS5                       (0xFFFFECACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
#define REG_MATRIX_PRAS6                       (0xFFFFECB0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
#define REG_MATRIX_PRBS6                       (0xFFFFECB4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
#define REG_MATRIX_PRAS7                       (0xFFFFECB8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
#define REG_MATRIX_PRBS7                       (0xFFFFECBCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
#define REG_MATRIX_PRAS8                       (0xFFFFECC0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
#define REG_MATRIX_PRBS8                       (0xFFFFECC4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
#define REG_MATRIX_PRAS9                       (0xFFFFECC8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
#define REG_MATRIX_PRBS9                       (0xFFFFECCCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */
#define REG_MATRIX_PRAS10                      (0xFFFFECD0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */
#define REG_MATRIX_PRBS10                      (0xFFFFECD4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */
#define REG_MATRIX_PRAS11                      (0xFFFFECD8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */
#define REG_MATRIX_PRBS11                      (0xFFFFECDCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */
#define REG_MATRIX_PRAS12                      (0xFFFFECE0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */
#define REG_MATRIX_PRBS12                      (0xFFFFECE4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */
#define REG_MATRIX_PRAS13                      (0xFFFFECE8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */
#define REG_MATRIX_PRBS13                      (0xFFFFECECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */
#define REG_MATRIX_PRAS14                      (0xFFFFECF0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */
#define REG_MATRIX_PRBS14                      (0xFFFFECF4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */
#define REG_MATRIX_PRAS15                      (0xFFFFECF8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */
#define REG_MATRIX_PRBS15                      (0xFFFFECFCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */
#define REG_MATRIX_MRCR                        (0xFFFFED00U) /**< \brief (MATRIX) Master Remap Control Register */
#define REG_MATRIX_SFR                         (0xFFFFED10U) /**< \brief (MATRIX) Special Function Register */
#define REG_MATRIX_WPMR                        (0xFFFFEDE4U) /**< \brief (MATRIX) Write Protect Mode Register */
#define REG_MATRIX_WPSR                        (0xFFFFEDE8U) /**< \brief (MATRIX) Write Protect Status Register */
#else
#define REG_MATRIX_MCFG               (*(RwReg*)0xFFFFEC00U) /**< \brief (MATRIX) Master Configuration Register */
#define REG_MATRIX_SCFG               (*(RwReg*)0xFFFFEC40U) /**< \brief (MATRIX) Slave Configuration Register */
#define REG_MATRIX_PRAS0              (*(RwReg*)0xFFFFEC80U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
#define REG_MATRIX_PRBS0              (*(RwReg*)0xFFFFEC84U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
#define REG_MATRIX_PRAS1              (*(RwReg*)0xFFFFEC88U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
#define REG_MATRIX_PRBS1              (*(RwReg*)0xFFFFEC8CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
#define REG_MATRIX_PRAS2              (*(RwReg*)0xFFFFEC90U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
#define REG_MATRIX_PRBS2              (*(RwReg*)0xFFFFEC94U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
#define REG_MATRIX_PRAS3              (*(RwReg*)0xFFFFEC98U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
#define REG_MATRIX_PRBS3              (*(RwReg*)0xFFFFEC9CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
#define REG_MATRIX_PRAS4              (*(RwReg*)0xFFFFECA0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
#define REG_MATRIX_PRBS4              (*(RwReg*)0xFFFFECA4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
#define REG_MATRIX_PRAS5              (*(RwReg*)0xFFFFECA8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
#define REG_MATRIX_PRBS5              (*(RwReg*)0xFFFFECACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
#define REG_MATRIX_PRAS6              (*(RwReg*)0xFFFFECB0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
#define REG_MATRIX_PRBS6              (*(RwReg*)0xFFFFECB4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
#define REG_MATRIX_PRAS7              (*(RwReg*)0xFFFFECB8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
#define REG_MATRIX_PRBS7              (*(RwReg*)0xFFFFECBCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
#define REG_MATRIX_PRAS8              (*(RwReg*)0xFFFFECC0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
#define REG_MATRIX_PRBS8              (*(RwReg*)0xFFFFECC4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
#define REG_MATRIX_PRAS9              (*(RwReg*)0xFFFFECC8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
#define REG_MATRIX_PRBS9              (*(RwReg*)0xFFFFECCCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */
#define REG_MATRIX_PRAS10             (*(RwReg*)0xFFFFECD0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */
#define REG_MATRIX_PRBS10             (*(RwReg*)0xFFFFECD4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */
#define REG_MATRIX_PRAS11             (*(RwReg*)0xFFFFECD8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */
#define REG_MATRIX_PRBS11             (*(RwReg*)0xFFFFECDCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */
#define REG_MATRIX_PRAS12             (*(RwReg*)0xFFFFECE0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */
#define REG_MATRIX_PRBS12             (*(RwReg*)0xFFFFECE4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */
#define REG_MATRIX_PRAS13             (*(RwReg*)0xFFFFECE8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */
#define REG_MATRIX_PRBS13             (*(RwReg*)0xFFFFECECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */
#define REG_MATRIX_PRAS14             (*(RwReg*)0xFFFFECF0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */
#define REG_MATRIX_PRBS14             (*(RwReg*)0xFFFFECF4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */
#define REG_MATRIX_PRAS15             (*(RwReg*)0xFFFFECF8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */
#define REG_MATRIX_PRBS15             (*(RwReg*)0xFFFFECFCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */
#define REG_MATRIX_MRCR               (*(RwReg*)0xFFFFED00U) /**< \brief (MATRIX) Master Remap Control Register */
#define REG_MATRIX_SFR                (*(RwReg*)0xFFFFED10U) /**< \brief (MATRIX) Special Function Register */
#define REG_MATRIX_WPMR               (*(RwReg*)0xFFFFEDE4U) /**< \brief (MATRIX) Write Protect Mode Register */
#define REG_MATRIX_WPSR               (*(RoReg*)0xFFFFEDE8U) /**< \brief (MATRIX) Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for DBGU peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_DBGU_CR                            (0xFFFFEE00U) /**< \brief (DBGU) Control Register */
#define REG_DBGU_MR                            (0xFFFFEE04U) /**< \brief (DBGU) Mode Register */
#define REG_DBGU_IER                           (0xFFFFEE08U) /**< \brief (DBGU) Interrupt Enable Register */
#define REG_DBGU_IDR                           (0xFFFFEE0CU) /**< \brief (DBGU) Interrupt Disable Register */
#define REG_DBGU_IMR                           (0xFFFFEE10U) /**< \brief (DBGU) Interrupt Mask Register */
#define REG_DBGU_SR                            (0xFFFFEE14U) /**< \brief (DBGU) Status Register */
#define REG_DBGU_RHR                           (0xFFFFEE18U) /**< \brief (DBGU) Receive Holding Register */
#define REG_DBGU_THR                           (0xFFFFEE1CU) /**< \brief (DBGU) Transmit Holding Register */
#define REG_DBGU_BRGR                          (0xFFFFEE20U) /**< \brief (DBGU) Baud Rate Generator Register */
#define REG_DBGU_CIDR                          (0xFFFFEE40U) /**< \brief (DBGU) Chip ID Register */
#define REG_DBGU_EXID                          (0xFFFFEE44U) /**< \brief (DBGU) Chip ID Extension Register */
#define REG_DBGU_FNR                           (0xFFFFEE48U) /**< \brief (DBGU) Force NTRST Register */
#else
#define REG_DBGU_CR                   (*(WoReg*)0xFFFFEE00U) /**< \brief (DBGU) Control Register */
#define REG_DBGU_MR                   (*(RwReg*)0xFFFFEE04U) /**< \brief (DBGU) Mode Register */
#define REG_DBGU_IER                  (*(WoReg*)0xFFFFEE08U) /**< \brief (DBGU) Interrupt Enable Register */
#define REG_DBGU_IDR                  (*(WoReg*)0xFFFFEE0CU) /**< \brief (DBGU) Interrupt Disable Register */
#define REG_DBGU_IMR                  (*(RoReg*)0xFFFFEE10U) /**< \brief (DBGU) Interrupt Mask Register */
#define REG_DBGU_SR                   (*(RoReg*)0xFFFFEE14U) /**< \brief (DBGU) Status Register */
#define REG_DBGU_RHR                  (*(RoReg*)0xFFFFEE18U) /**< \brief (DBGU) Receive Holding Register */
#define REG_DBGU_THR                  (*(WoReg*)0xFFFFEE1CU) /**< \brief (DBGU) Transmit Holding Register */
#define REG_DBGU_BRGR                 (*(RwReg*)0xFFFFEE20U) /**< \brief (DBGU) Baud Rate Generator Register */
#define REG_DBGU_CIDR                 (*(RoReg*)0xFFFFEE40U) /**< \brief (DBGU) Chip ID Register */
#define REG_DBGU_EXID                 (*(RoReg*)0xFFFFEE44U) /**< \brief (DBGU) Chip ID Extension Register */
#define REG_DBGU_FNR                  (*(RwReg*)0xFFFFEE48U) /**< \brief (DBGU) Force NTRST Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for AIC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_AIC_SSR                            (0xFFFFF000U) /**< \brief (AIC) Source Select Register */
#define REG_AIC_SMR                            (0xFFFFF004U) /**< \brief (AIC) Source Mode Register */
#define REG_AIC_SVR                            (0xFFFFF008U) /**< \brief (AIC) Source Vector Register */
#define REG_AIC_IVR                            (0xFFFFF010U) /**< \brief (AIC) Interrupt Vector Register */
#define REG_AIC_FVR                            (0xFFFFF014U) /**< \brief (AIC) FIQ Interrupt Vector Register */
#define REG_AIC_ISR                            (0xFFFFF018U) /**< \brief (AIC) Interrupt Status Register */
#define REG_AIC_IPR0                           (0xFFFFF020U) /**< \brief (AIC) Interrupt Pending Register 0 */
#define REG_AIC_IPR1                           (0xFFFFF024U) /**< \brief (AIC) Interrupt Pending Register 1 */
#define REG_AIC_IPR2                           (0xFFFFF028U) /**< \brief (AIC) Interrupt Pending Register 2 */
#define REG_AIC_IPR3                           (0xFFFFF02CU) /**< \brief (AIC) Interrupt Pending Register 3 */
#define REG_AIC_IMR                            (0xFFFFF030U) /**< \brief (AIC) Interrupt Mask Register */
#define REG_AIC_CISR                           (0xFFFFF034U) /**< \brief (AIC) Core Interrupt Status Register */
#define REG_AIC_EOICR                          (0xFFFFF038U) /**< \brief (AIC) End of Interrupt Command Register */
#define REG_AIC_SPU                            (0xFFFFF03CU) /**< \brief (AIC) Spurious Interrupt Vector Register */
#define REG_AIC_IECR                           (0xFFFFF040U) /**< \brief (AIC) Interrupt Enable Command Register */
#define REG_AIC_IDCR                           (0xFFFFF044U) /**< \brief (AIC) Interrupt Disable Command Register */
#define REG_AIC_ICCR                           (0xFFFFF048U) /**< \brief (AIC) Interrupt Clear Command Register */
#define REG_AIC_ISCR                           (0xFFFFF04CU) /**< \brief (AIC) Interrupt Set Command Register */
#define REG_AIC_FFER                           (0xFFFFF050U) /**< \brief (AIC) Fast Forcing Enable Register */
#define REG_AIC_FFDR                           (0xFFFFF054U) /**< \brief (AIC) Fast Forcing Disable Register */
#define REG_AIC_FFSR                           (0xFFFFF058U) /**< \brief (AIC) Fast Forcing Status Register */
#define REG_AIC_DCR                            (0xFFFFF06CU) /**< \brief (AIC) Debug Control Register */
#define REG_AIC_WPMR                           (0xFFFFF0E4U) /**< \brief (AIC) Write Protect Mode Register */
#define REG_AIC_WPSR                           (0xFFFFF0E8U) /**< \brief (AIC) Write Protect Status Register */
#else
#define REG_AIC_SSR                   (*(RwReg*)0xFFFFF000U) /**< \brief (AIC) Source Select Register */
#define REG_AIC_SMR                   (*(RwReg*)0xFFFFF004U) /**< \brief (AIC) Source Mode Register */
#define REG_AIC_SVR                   (*(RwReg*)0xFFFFF008U) /**< \brief (AIC) Source Vector Register */
#define REG_AIC_IVR                   (*(RoReg*)0xFFFFF010U) /**< \brief (AIC) Interrupt Vector Register */
#define REG_AIC_FVR                   (*(RoReg*)0xFFFFF014U) /**< \brief (AIC) FIQ Interrupt Vector Register */
#define REG_AIC_ISR                   (*(RoReg*)0xFFFFF018U) /**< \brief (AIC) Interrupt Status Register */
#define REG_AIC_IPR0                  (*(RoReg*)0xFFFFF020U) /**< \brief (AIC) Interrupt Pending Register 0 */
#define REG_AIC_IPR1                  (*(RoReg*)0xFFFFF024U) /**< \brief (AIC) Interrupt Pending Register 1 */
#define REG_AIC_IPR2                  (*(RoReg*)0xFFFFF028U) /**< \brief (AIC) Interrupt Pending Register 2 */
#define REG_AIC_IPR3                  (*(RoReg*)0xFFFFF02CU) /**< \brief (AIC) Interrupt Pending Register 3 */
#define REG_AIC_IMR                   (*(RoReg*)0xFFFFF030U) /**< \brief (AIC) Interrupt Mask Register */
#define REG_AIC_CISR                  (*(RoReg*)0xFFFFF034U) /**< \brief (AIC) Core Interrupt Status Register */
#define REG_AIC_EOICR                 (*(WoReg*)0xFFFFF038U) /**< \brief (AIC) End of Interrupt Command Register */
#define REG_AIC_SPU                   (*(RwReg*)0xFFFFF03CU) /**< \brief (AIC) Spurious Interrupt Vector Register */
#define REG_AIC_IECR                  (*(WoReg*)0xFFFFF040U) /**< \brief (AIC) Interrupt Enable Command Register */
#define REG_AIC_IDCR                  (*(WoReg*)0xFFFFF044U) /**< \brief (AIC) Interrupt Disable Command Register */
#define REG_AIC_ICCR                  (*(WoReg*)0xFFFFF048U) /**< \brief (AIC) Interrupt Clear Command Register */
#define REG_AIC_ISCR                  (*(WoReg*)0xFFFFF04CU) /**< \brief (AIC) Interrupt Set Command Register */
#define REG_AIC_FFER                  (*(WoReg*)0xFFFFF050U) /**< \brief (AIC) Fast Forcing Enable Register */
#define REG_AIC_FFDR                  (*(WoReg*)0xFFFFF054U) /**< \brief (AIC) Fast Forcing Disable Register */
#define REG_AIC_FFSR                  (*(RoReg*)0xFFFFF058U) /**< \brief (AIC) Fast Forcing Status Register */
#define REG_AIC_DCR                   (*(RwReg*)0xFFFFF06CU) /**< \brief (AIC) Debug Control Register */
#define REG_AIC_WPMR                  (*(RwReg*)0xFFFFF0E4U) /**< \brief (AIC) Write Protect Mode Register */
#define REG_AIC_WPSR                  (*(RoReg*)0xFFFFF0E8U) /**< \brief (AIC) Write Protect Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for PIOA peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_PIOA_PER                           (0xFFFFF200U) /**< \brief (PIOA) PIO Enable Register */
#define REG_PIOA_PDR                           (0xFFFFF204U) /**< \brief (PIOA) PIO Disable Register */
#define REG_PIOA_PSR                           (0xFFFFF208U) /**< \brief (PIOA) PIO Status Register */
#define REG_PIOA_OER                           (0xFFFFF210U) /**< \brief (PIOA) Output Enable Register */
#define REG_PIOA_ODR                           (0xFFFFF214U) /**< \brief (PIOA) Output Disable Register */
#define REG_PIOA_OSR                           (0xFFFFF218U) /**< \brief (PIOA) Output Status Register */
#define REG_PIOA_IFER                          (0xFFFFF220U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
#define REG_PIOA_IFDR                          (0xFFFFF224U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
#define REG_PIOA_IFSR                          (0xFFFFF228U) /**< \brief (PIOA) Glitch Input Filter Status Register */
#define REG_PIOA_SODR                          (0xFFFFF230U) /**< \brief (PIOA) Set Output Data Register */
#define REG_PIOA_CODR                          (0xFFFFF234U) /**< \brief (PIOA) Clear Output Data Register */
#define REG_PIOA_ODSR                          (0xFFFFF238U) /**< \brief (PIOA) Output Data Status Register */
#define REG_PIOA_PDSR                          (0xFFFFF23CU) /**< \brief (PIOA) Pin Data Status Register */
#define REG_PIOA_IER                           (0xFFFFF240U) /**< \brief (PIOA) Interrupt Enable Register */
#define REG_PIOA_IDR                           (0xFFFFF244U) /**< \brief (PIOA) Interrupt Disable Register */
#define REG_PIOA_IMR                           (0xFFFFF248U) /**< \brief (PIOA) Interrupt Mask Register */
#define REG_PIOA_ISR                           (0xFFFFF24CU) /**< \brief (PIOA) Interrupt Status Register */
#define REG_PIOA_MDER                          (0xFFFFF250U) /**< \brief (PIOA) Multi-driver Enable Register */
#define REG_PIOA_MDDR                          (0xFFFFF254U) /**< \brief (PIOA) Multi-driver Disable Register */
#define REG_PIOA_MDSR                          (0xFFFFF258U) /**< \brief (PIOA) Multi-driver Status Register */
#define REG_PIOA_PUDR                          (0xFFFFF260U) /**< \brief (PIOA) Pull-up Disable Register */
#define REG_PIOA_PUER                          (0xFFFFF264U) /**< \brief (PIOA) Pull-up Enable Register */
#define REG_PIOA_PUSR                          (0xFFFFF268U) /**< \brief (PIOA) Pad Pull-up Status Register */
#define REG_PIOA_ABCDSR                        (0xFFFFF270U) /**< \brief (PIOA) Peripheral Select Register */
#define REG_PIOA_IFSCDR                        (0xFFFFF280U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
#define REG_PIOA_IFSCER                        (0xFFFFF284U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
#define REG_PIOA_IFSCSR                        (0xFFFFF288U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
#define REG_PIOA_SCDR                          (0xFFFFF28CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
#define REG_PIOA_PPDDR                         (0xFFFFF290U) /**< \brief (PIOA) Pad Pull-down Disable Register */
#define REG_PIOA_PPDER                         (0xFFFFF294U) /**< \brief (PIOA) Pad Pull-down Enable Register */
#define REG_PIOA_PPDSR                         (0xFFFFF298U) /**< \brief (PIOA) Pad Pull-down Status Register */
#define REG_PIOA_OWER                          (0xFFFFF2A0U) /**< \brief (PIOA) Output Write Enable */
#define REG_PIOA_OWDR                          (0xFFFFF2A4U) /**< \brief (PIOA) Output Write Disable */
#define REG_PIOA_OWSR                          (0xFFFFF2A8U) /**< \brief (PIOA) Output Write Status Register */
#define REG_PIOA_AIMER                         (0xFFFFF2B0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
#define REG_PIOA_AIMDR                         (0xFFFFF2B4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
#define REG_PIOA_AIMMR                         (0xFFFFF2B8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
#define REG_PIOA_ESR                           (0xFFFFF2C0U) /**< \brief (PIOA) Edge Select Register */
#define REG_PIOA_LSR                           (0xFFFFF2C4U) /**< \brief (PIOA) Level Select Register */
#define REG_PIOA_ELSR                          (0xFFFFF2C8U) /**< \brief (PIOA) Edge/Level Status Register */
#define REG_PIOA_FELLSR                        (0xFFFFF2D0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
#define REG_PIOA_REHLSR                        (0xFFFFF2D4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
#define REG_PIOA_FRLHSR                        (0xFFFFF2D8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
#define REG_PIOA_LOCKSR                        (0xFFFFF2E0U) /**< \brief (PIOA) Lock Status */
#define REG_PIOA_WPMR                          (0xFFFFF2E4U) /**< \brief (PIOA) Write Protect Mode Register */
#define REG_PIOA_WPSR                          (0xFFFFF2E8U) /**< \brief (PIOA) Write Protect Status Register */
#define REG_PIOA_SCHMITT                       (0xFFFFF300U) /**< \brief (PIOA) Schmitt Trigger Register */
#define REG_PIOA_DRIVER1                       (0xFFFFF318U) /**< \brief (PIOA) I/O Drive Register 1 */
#define REG_PIOA_DRIVER2                       (0xFFFFF31CU) /**< \brief (PIOA) I/O Drive Register 2 */
#else
#define REG_PIOA_PER                  (*(WoReg*)0xFFFFF200U) /**< \brief (PIOA) PIO Enable Register */
#define REG_PIOA_PDR                  (*(WoReg*)0xFFFFF204U) /**< \brief (PIOA) PIO Disable Register */
#define REG_PIOA_PSR                  (*(RoReg*)0xFFFFF208U) /**< \brief (PIOA) PIO Status Register */
#define REG_PIOA_OER                  (*(WoReg*)0xFFFFF210U) /**< \brief (PIOA) Output Enable Register */
#define REG_PIOA_ODR                  (*(WoReg*)0xFFFFF214U) /**< \brief (PIOA) Output Disable Register */
#define REG_PIOA_OSR                  (*(RoReg*)0xFFFFF218U) /**< \brief (PIOA) Output Status Register */
#define REG_PIOA_IFER                 (*(WoReg*)0xFFFFF220U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
#define REG_PIOA_IFDR                 (*(WoReg*)0xFFFFF224U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
#define REG_PIOA_IFSR                 (*(RoReg*)0xFFFFF228U) /**< \brief (PIOA) Glitch Input Filter Status Register */
#define REG_PIOA_SODR                 (*(WoReg*)0xFFFFF230U) /**< \brief (PIOA) Set Output Data Register */
#define REG_PIOA_CODR                 (*(WoReg*)0xFFFFF234U) /**< \brief (PIOA) Clear Output Data Register */
#define REG_PIOA_ODSR                 (*(RwReg*)0xFFFFF238U) /**< \brief (PIOA) Output Data Status Register */
#define REG_PIOA_PDSR                 (*(RoReg*)0xFFFFF23CU) /**< \brief (PIOA) Pin Data Status Register */
#define REG_PIOA_IER                  (*(WoReg*)0xFFFFF240U) /**< \brief (PIOA) Interrupt Enable Register */
#define REG_PIOA_IDR                  (*(WoReg*)0xFFFFF244U) /**< \brief (PIOA) Interrupt Disable Register */
#define REG_PIOA_IMR                  (*(RoReg*)0xFFFFF248U) /**< \brief (PIOA) Interrupt Mask Register */
#define REG_PIOA_ISR                  (*(RoReg*)0xFFFFF24CU) /**< \brief (PIOA) Interrupt Status Register */
#define REG_PIOA_MDER                 (*(WoReg*)0xFFFFF250U) /**< \brief (PIOA) Multi-driver Enable Register */
#define REG_PIOA_MDDR                 (*(WoReg*)0xFFFFF254U) /**< \brief (PIOA) Multi-driver Disable Register */
#define REG_PIOA_MDSR                 (*(RoReg*)0xFFFFF258U) /**< \brief (PIOA) Multi-driver Status Register */
#define REG_PIOA_PUDR                 (*(WoReg*)0xFFFFF260U) /**< \brief (PIOA) Pull-up Disable Register */
#define REG_PIOA_PUER                 (*(WoReg*)0xFFFFF264U) /**< \brief (PIOA) Pull-up Enable Register */
#define REG_PIOA_PUSR                 (*(RoReg*)0xFFFFF268U) /**< \brief (PIOA) Pad Pull-up Status Register */
#define REG_PIOA_ABCDSR               (*(RwReg*)0xFFFFF270U) /**< \brief (PIOA) Peripheral Select Register */
#define REG_PIOA_IFSCDR               (*(WoReg*)0xFFFFF280U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
#define REG_PIOA_IFSCER               (*(WoReg*)0xFFFFF284U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
#define REG_PIOA_IFSCSR               (*(RoReg*)0xFFFFF288U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
#define REG_PIOA_SCDR                 (*(RwReg*)0xFFFFF28CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
#define REG_PIOA_PPDDR                (*(WoReg*)0xFFFFF290U) /**< \brief (PIOA) Pad Pull-down Disable Register */
#define REG_PIOA_PPDER                (*(WoReg*)0xFFFFF294U) /**< \brief (PIOA) Pad Pull-down Enable Register */
#define REG_PIOA_PPDSR                (*(RoReg*)0xFFFFF298U) /**< \brief (PIOA) Pad Pull-down Status Register */
#define REG_PIOA_OWER                 (*(WoReg*)0xFFFFF2A0U) /**< \brief (PIOA) Output Write Enable */
#define REG_PIOA_OWDR                 (*(WoReg*)0xFFFFF2A4U) /**< \brief (PIOA) Output Write Disable */
#define REG_PIOA_OWSR                 (*(RoReg*)0xFFFFF2A8U) /**< \brief (PIOA) Output Write Status Register */
#define REG_PIOA_AIMER                (*(WoReg*)0xFFFFF2B0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
#define REG_PIOA_AIMDR                (*(WoReg*)0xFFFFF2B4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
#define REG_PIOA_AIMMR                (*(RoReg*)0xFFFFF2B8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
#define REG_PIOA_ESR                  (*(WoReg*)0xFFFFF2C0U) /**< \brief (PIOA) Edge Select Register */
#define REG_PIOA_LSR                  (*(WoReg*)0xFFFFF2C4U) /**< \brief (PIOA) Level Select Register */
#define REG_PIOA_ELSR                 (*(RoReg*)0xFFFFF2C8U) /**< \brief (PIOA) Edge/Level Status Register */
#define REG_PIOA_FELLSR               (*(WoReg*)0xFFFFF2D0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
#define REG_PIOA_REHLSR               (*(WoReg*)0xFFFFF2D4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
#define REG_PIOA_FRLHSR               (*(RoReg*)0xFFFFF2D8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
#define REG_PIOA_LOCKSR               (*(RoReg*)0xFFFFF2E0U) /**< \brief (PIOA) Lock Status */
#define REG_PIOA_WPMR                 (*(RwReg*)0xFFFFF2E4U) /**< \brief (PIOA) Write Protect Mode Register */
#define REG_PIOA_WPSR                 (*(RoReg*)0xFFFFF2E8U) /**< \brief (PIOA) Write Protect Status Register */
#define REG_PIOA_SCHMITT              (*(RwReg*)0xFFFFF300U) /**< \brief (PIOA) Schmitt Trigger Register */
#define REG_PIOA_DRIVER1              (*(RwReg*)0xFFFFF318U) /**< \brief (PIOA) I/O Drive Register 1 */
#define REG_PIOA_DRIVER2              (*(RwReg*)0xFFFFF31CU) /**< \brief (PIOA) I/O Drive Register 2 */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for PIOB peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_PIOB_PER                           (0xFFFFF400U) /**< \brief (PIOB) PIO Enable Register */
#define REG_PIOB_PDR                           (0xFFFFF404U) /**< \brief (PIOB) PIO Disable Register */
#define REG_PIOB_PSR                           (0xFFFFF408U) /**< \brief (PIOB) PIO Status Register */
#define REG_PIOB_OER                           (0xFFFFF410U) /**< \brief (PIOB) Output Enable Register */
#define REG_PIOB_ODR                           (0xFFFFF414U) /**< \brief (PIOB) Output Disable Register */
#define REG_PIOB_OSR                           (0xFFFFF418U) /**< \brief (PIOB) Output Status Register */
#define REG_PIOB_IFER                          (0xFFFFF420U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
#define REG_PIOB_IFDR                          (0xFFFFF424U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
#define REG_PIOB_IFSR                          (0xFFFFF428U) /**< \brief (PIOB) Glitch Input Filter Status Register */
#define REG_PIOB_SODR                          (0xFFFFF430U) /**< \brief (PIOB) Set Output Data Register */
#define REG_PIOB_CODR                          (0xFFFFF434U) /**< \brief (PIOB) Clear Output Data Register */
#define REG_PIOB_ODSR                          (0xFFFFF438U) /**< \brief (PIOB) Output Data Status Register */
#define REG_PIOB_PDSR                          (0xFFFFF43CU) /**< \brief (PIOB) Pin Data Status Register */
#define REG_PIOB_IER                           (0xFFFFF440U) /**< \brief (PIOB) Interrupt Enable Register */
#define REG_PIOB_IDR                           (0xFFFFF444U) /**< \brief (PIOB) Interrupt Disable Register */
#define REG_PIOB_IMR                           (0xFFFFF448U) /**< \brief (PIOB) Interrupt Mask Register */
#define REG_PIOB_ISR                           (0xFFFFF44CU) /**< \brief (PIOB) Interrupt Status Register */
#define REG_PIOB_MDER                          (0xFFFFF450U) /**< \brief (PIOB) Multi-driver Enable Register */
#define REG_PIOB_MDDR                          (0xFFFFF454U) /**< \brief (PIOB) Multi-driver Disable Register */
#define REG_PIOB_MDSR                          (0xFFFFF458U) /**< \brief (PIOB) Multi-driver Status Register */
#define REG_PIOB_PUDR                          (0xFFFFF460U) /**< \brief (PIOB) Pull-up Disable Register */
#define REG_PIOB_PUER                          (0xFFFFF464U) /**< \brief (PIOB) Pull-up Enable Register */
#define REG_PIOB_PUSR                          (0xFFFFF468U) /**< \brief (PIOB) Pad Pull-up Status Register */
#define REG_PIOB_ABCDSR                        (0xFFFFF470U) /**< \brief (PIOB) Peripheral Select Register */
#define REG_PIOB_IFSCDR                        (0xFFFFF480U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
#define REG_PIOB_IFSCER                        (0xFFFFF484U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
#define REG_PIOB_IFSCSR                        (0xFFFFF488U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
#define REG_PIOB_SCDR                          (0xFFFFF48CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
#define REG_PIOB_PPDDR                         (0xFFFFF490U) /**< \brief (PIOB) Pad Pull-down Disable Register */
#define REG_PIOB_PPDER                         (0xFFFFF494U) /**< \brief (PIOB) Pad Pull-down Enable Register */
#define REG_PIOB_PPDSR                         (0xFFFFF498U) /**< \brief (PIOB) Pad Pull-down Status Register */
#define REG_PIOB_OWER                          (0xFFFFF4A0U) /**< \brief (PIOB) Output Write Enable */
#define REG_PIOB_OWDR                          (0xFFFFF4A4U) /**< \brief (PIOB) Output Write Disable */
#define REG_PIOB_OWSR                          (0xFFFFF4A8U) /**< \brief (PIOB) Output Write Status Register */
#define REG_PIOB_AIMER                         (0xFFFFF4B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
#define REG_PIOB_AIMDR                         (0xFFFFF4B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
#define REG_PIOB_AIMMR                         (0xFFFFF4B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
#define REG_PIOB_ESR                           (0xFFFFF4C0U) /**< \brief (PIOB) Edge Select Register */
#define REG_PIOB_LSR                           (0xFFFFF4C4U) /**< \brief (PIOB) Level Select Register */
#define REG_PIOB_ELSR                          (0xFFFFF4C8U) /**< \brief (PIOB) Edge/Level Status Register */
#define REG_PIOB_FELLSR                        (0xFFFFF4D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
#define REG_PIOB_REHLSR                        (0xFFFFF4D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
#define REG_PIOB_FRLHSR                        (0xFFFFF4D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
#define REG_PIOB_LOCKSR                        (0xFFFFF4E0U) /**< \brief (PIOB) Lock Status */
#define REG_PIOB_WPMR                          (0xFFFFF4E4U) /**< \brief (PIOB) Write Protect Mode Register */
#define REG_PIOB_WPSR                          (0xFFFFF4E8U) /**< \brief (PIOB) Write Protect Status Register */
#define REG_PIOB_SCHMITT                       (0xFFFFF500U) /**< \brief (PIOB) Schmitt Trigger Register */
#define REG_PIOB_DRIVER1                       (0xFFFFF518U) /**< \brief (PIOB) I/O Drive Register 1 */
#define REG_PIOB_DRIVER2                       (0xFFFFF51CU) /**< \brief (PIOB) I/O Drive Register 2 */
#else
#define REG_PIOB_PER                  (*(WoReg*)0xFFFFF400U) /**< \brief (PIOB) PIO Enable Register */
#define REG_PIOB_PDR                  (*(WoReg*)0xFFFFF404U) /**< \brief (PIOB) PIO Disable Register */
#define REG_PIOB_PSR                  (*(RoReg*)0xFFFFF408U) /**< \brief (PIOB) PIO Status Register */
#define REG_PIOB_OER                  (*(WoReg*)0xFFFFF410U) /**< \brief (PIOB) Output Enable Register */
#define REG_PIOB_ODR                  (*(WoReg*)0xFFFFF414U) /**< \brief (PIOB) Output Disable Register */
#define REG_PIOB_OSR                  (*(RoReg*)0xFFFFF418U) /**< \brief (PIOB) Output Status Register */
#define REG_PIOB_IFER                 (*(WoReg*)0xFFFFF420U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
#define REG_PIOB_IFDR                 (*(WoReg*)0xFFFFF424U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
#define REG_PIOB_IFSR                 (*(RoReg*)0xFFFFF428U) /**< \brief (PIOB) Glitch Input Filter Status Register */
#define REG_PIOB_SODR                 (*(WoReg*)0xFFFFF430U) /**< \brief (PIOB) Set Output Data Register */
#define REG_PIOB_CODR                 (*(WoReg*)0xFFFFF434U) /**< \brief (PIOB) Clear Output Data Register */
#define REG_PIOB_ODSR                 (*(RwReg*)0xFFFFF438U) /**< \brief (PIOB) Output Data Status Register */
#define REG_PIOB_PDSR                 (*(RoReg*)0xFFFFF43CU) /**< \brief (PIOB) Pin Data Status Register */
#define REG_PIOB_IER                  (*(WoReg*)0xFFFFF440U) /**< \brief (PIOB) Interrupt Enable Register */
#define REG_PIOB_IDR                  (*(WoReg*)0xFFFFF444U) /**< \brief (PIOB) Interrupt Disable Register */
#define REG_PIOB_IMR                  (*(RoReg*)0xFFFFF448U) /**< \brief (PIOB) Interrupt Mask Register */
#define REG_PIOB_ISR                  (*(RoReg*)0xFFFFF44CU) /**< \brief (PIOB) Interrupt Status Register */
#define REG_PIOB_MDER                 (*(WoReg*)0xFFFFF450U) /**< \brief (PIOB) Multi-driver Enable Register */
#define REG_PIOB_MDDR                 (*(WoReg*)0xFFFFF454U) /**< \brief (PIOB) Multi-driver Disable Register */
#define REG_PIOB_MDSR                 (*(RoReg*)0xFFFFF458U) /**< \brief (PIOB) Multi-driver Status Register */
#define REG_PIOB_PUDR                 (*(WoReg*)0xFFFFF460U) /**< \brief (PIOB) Pull-up Disable Register */
#define REG_PIOB_PUER                 (*(WoReg*)0xFFFFF464U) /**< \brief (PIOB) Pull-up Enable Register */
#define REG_PIOB_PUSR                 (*(RoReg*)0xFFFFF468U) /**< \brief (PIOB) Pad Pull-up Status Register */
#define REG_PIOB_ABCDSR               (*(RwReg*)0xFFFFF470U) /**< \brief (PIOB) Peripheral Select Register */
#define REG_PIOB_IFSCDR               (*(WoReg*)0xFFFFF480U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
#define REG_PIOB_IFSCER               (*(WoReg*)0xFFFFF484U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
#define REG_PIOB_IFSCSR               (*(RoReg*)0xFFFFF488U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
#define REG_PIOB_SCDR                 (*(RwReg*)0xFFFFF48CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
#define REG_PIOB_PPDDR                (*(WoReg*)0xFFFFF490U) /**< \brief (PIOB) Pad Pull-down Disable Register */
#define REG_PIOB_PPDER                (*(WoReg*)0xFFFFF494U) /**< \brief (PIOB) Pad Pull-down Enable Register */
#define REG_PIOB_PPDSR                (*(RoReg*)0xFFFFF498U) /**< \brief (PIOB) Pad Pull-down Status Register */
#define REG_PIOB_OWER                 (*(WoReg*)0xFFFFF4A0U) /**< \brief (PIOB) Output Write Enable */
#define REG_PIOB_OWDR                 (*(WoReg*)0xFFFFF4A4U) /**< \brief (PIOB) Output Write Disable */
#define REG_PIOB_OWSR                 (*(RoReg*)0xFFFFF4A8U) /**< \brief (PIOB) Output Write Status Register */
#define REG_PIOB_AIMER                (*(WoReg*)0xFFFFF4B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
#define REG_PIOB_AIMDR                (*(WoReg*)0xFFFFF4B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
#define REG_PIOB_AIMMR                (*(RoReg*)0xFFFFF4B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
#define REG_PIOB_ESR                  (*(WoReg*)0xFFFFF4C0U) /**< \brief (PIOB) Edge Select Register */
#define REG_PIOB_LSR                  (*(WoReg*)0xFFFFF4C4U) /**< \brief (PIOB) Level Select Register */
#define REG_PIOB_ELSR                 (*(RoReg*)0xFFFFF4C8U) /**< \brief (PIOB) Edge/Level Status Register */
#define REG_PIOB_FELLSR               (*(WoReg*)0xFFFFF4D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
#define REG_PIOB_REHLSR               (*(WoReg*)0xFFFFF4D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
#define REG_PIOB_FRLHSR               (*(RoReg*)0xFFFFF4D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
#define REG_PIOB_LOCKSR               (*(RoReg*)0xFFFFF4E0U) /**< \brief (PIOB) Lock Status */
#define REG_PIOB_WPMR                 (*(RwReg*)0xFFFFF4E4U) /**< \brief (PIOB) Write Protect Mode Register */
#define REG_PIOB_WPSR                 (*(RoReg*)0xFFFFF4E8U) /**< \brief (PIOB) Write Protect Status Register */
#define REG_PIOB_SCHMITT              (*(RwReg*)0xFFFFF500U) /**< \brief (PIOB) Schmitt Trigger Register */
#define REG_PIOB_DRIVER1              (*(RwReg*)0xFFFFF518U) /**< \brief (PIOB) I/O Drive Register 1 */
#define REG_PIOB_DRIVER2              (*(RwReg*)0xFFFFF51CU) /**< \brief (PIOB) I/O Drive Register 2 */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for PIOC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_PIOC_PER                           (0xFFFFF600U) /**< \brief (PIOC) PIO Enable Register */
#define REG_PIOC_PDR                           (0xFFFFF604U) /**< \brief (PIOC) PIO Disable Register */
#define REG_PIOC_PSR                           (0xFFFFF608U) /**< \brief (PIOC) PIO Status Register */
#define REG_PIOC_OER                           (0xFFFFF610U) /**< \brief (PIOC) Output Enable Register */
#define REG_PIOC_ODR                           (0xFFFFF614U) /**< \brief (PIOC) Output Disable Register */
#define REG_PIOC_OSR                           (0xFFFFF618U) /**< \brief (PIOC) Output Status Register */
#define REG_PIOC_IFER                          (0xFFFFF620U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
#define REG_PIOC_IFDR                          (0xFFFFF624U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
#define REG_PIOC_IFSR                          (0xFFFFF628U) /**< \brief (PIOC) Glitch Input Filter Status Register */
#define REG_PIOC_SODR                          (0xFFFFF630U) /**< \brief (PIOC) Set Output Data Register */
#define REG_PIOC_CODR                          (0xFFFFF634U) /**< \brief (PIOC) Clear Output Data Register */
#define REG_PIOC_ODSR                          (0xFFFFF638U) /**< \brief (PIOC) Output Data Status Register */
#define REG_PIOC_PDSR                          (0xFFFFF63CU) /**< \brief (PIOC) Pin Data Status Register */
#define REG_PIOC_IER                           (0xFFFFF640U) /**< \brief (PIOC) Interrupt Enable Register */
#define REG_PIOC_IDR                           (0xFFFFF644U) /**< \brief (PIOC) Interrupt Disable Register */
#define REG_PIOC_IMR                           (0xFFFFF648U) /**< \brief (PIOC) Interrupt Mask Register */
#define REG_PIOC_ISR                           (0xFFFFF64CU) /**< \brief (PIOC) Interrupt Status Register */
#define REG_PIOC_MDER                          (0xFFFFF650U) /**< \brief (PIOC) Multi-driver Enable Register */
#define REG_PIOC_MDDR                          (0xFFFFF654U) /**< \brief (PIOC) Multi-driver Disable Register */
#define REG_PIOC_MDSR                          (0xFFFFF658U) /**< \brief (PIOC) Multi-driver Status Register */
#define REG_PIOC_PUDR                          (0xFFFFF660U) /**< \brief (PIOC) Pull-up Disable Register */
#define REG_PIOC_PUER                          (0xFFFFF664U) /**< \brief (PIOC) Pull-up Enable Register */
#define REG_PIOC_PUSR                          (0xFFFFF668U) /**< \brief (PIOC) Pad Pull-up Status Register */
#define REG_PIOC_ABCDSR                        (0xFFFFF670U) /**< \brief (PIOC) Peripheral Select Register */
#define REG_PIOC_IFSCDR                        (0xFFFFF680U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
#define REG_PIOC_IFSCER                        (0xFFFFF684U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
#define REG_PIOC_IFSCSR                        (0xFFFFF688U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
#define REG_PIOC_SCDR                          (0xFFFFF68CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
#define REG_PIOC_PPDDR                         (0xFFFFF690U) /**< \brief (PIOC) Pad Pull-down Disable Register */
#define REG_PIOC_PPDER                         (0xFFFFF694U) /**< \brief (PIOC) Pad Pull-down Enable Register */
#define REG_PIOC_PPDSR                         (0xFFFFF698U) /**< \brief (PIOC) Pad Pull-down Status Register */
#define REG_PIOC_OWER                          (0xFFFFF6A0U) /**< \brief (PIOC) Output Write Enable */
#define REG_PIOC_OWDR                          (0xFFFFF6A4U) /**< \brief (PIOC) Output Write Disable */
#define REG_PIOC_OWSR                          (0xFFFFF6A8U) /**< \brief (PIOC) Output Write Status Register */
#define REG_PIOC_AIMER                         (0xFFFFF6B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
#define REG_PIOC_AIMDR                         (0xFFFFF6B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
#define REG_PIOC_AIMMR                         (0xFFFFF6B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
#define REG_PIOC_ESR                           (0xFFFFF6C0U) /**< \brief (PIOC) Edge Select Register */
#define REG_PIOC_LSR                           (0xFFFFF6C4U) /**< \brief (PIOC) Level Select Register */
#define REG_PIOC_ELSR                          (0xFFFFF6C8U) /**< \brief (PIOC) Edge/Level Status Register */
#define REG_PIOC_FELLSR                        (0xFFFFF6D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
#define REG_PIOC_REHLSR                        (0xFFFFF6D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
#define REG_PIOC_FRLHSR                        (0xFFFFF6D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
#define REG_PIOC_LOCKSR                        (0xFFFFF6E0U) /**< \brief (PIOC) Lock Status */
#define REG_PIOC_WPMR                          (0xFFFFF6E4U) /**< \brief (PIOC) Write Protect Mode Register */
#define REG_PIOC_WPSR                          (0xFFFFF6E8U) /**< \brief (PIOC) Write Protect Status Register */
#define REG_PIOC_SCHMITT                       (0xFFFFF700U) /**< \brief (PIOC) Schmitt Trigger Register */
#define REG_PIOC_DRIVER1                       (0xFFFFF718U) /**< \brief (PIOC) I/O Drive Register 1 */
#define REG_PIOC_DRIVER2                       (0xFFFFF71CU) /**< \brief (PIOC) I/O Drive Register 2 */
#else
#define REG_PIOC_PER                  (*(WoReg*)0xFFFFF600U) /**< \brief (PIOC) PIO Enable Register */
#define REG_PIOC_PDR                  (*(WoReg*)0xFFFFF604U) /**< \brief (PIOC) PIO Disable Register */
#define REG_PIOC_PSR                  (*(RoReg*)0xFFFFF608U) /**< \brief (PIOC) PIO Status Register */
#define REG_PIOC_OER                  (*(WoReg*)0xFFFFF610U) /**< \brief (PIOC) Output Enable Register */
#define REG_PIOC_ODR                  (*(WoReg*)0xFFFFF614U) /**< \brief (PIOC) Output Disable Register */
#define REG_PIOC_OSR                  (*(RoReg*)0xFFFFF618U) /**< \brief (PIOC) Output Status Register */
#define REG_PIOC_IFER                 (*(WoReg*)0xFFFFF620U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
#define REG_PIOC_IFDR                 (*(WoReg*)0xFFFFF624U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
#define REG_PIOC_IFSR                 (*(RoReg*)0xFFFFF628U) /**< \brief (PIOC) Glitch Input Filter Status Register */
#define REG_PIOC_SODR                 (*(WoReg*)0xFFFFF630U) /**< \brief (PIOC) Set Output Data Register */
#define REG_PIOC_CODR                 (*(WoReg*)0xFFFFF634U) /**< \brief (PIOC) Clear Output Data Register */
#define REG_PIOC_ODSR                 (*(RwReg*)0xFFFFF638U) /**< \brief (PIOC) Output Data Status Register */
#define REG_PIOC_PDSR                 (*(RoReg*)0xFFFFF63CU) /**< \brief (PIOC) Pin Data Status Register */
#define REG_PIOC_IER                  (*(WoReg*)0xFFFFF640U) /**< \brief (PIOC) Interrupt Enable Register */
#define REG_PIOC_IDR                  (*(WoReg*)0xFFFFF644U) /**< \brief (PIOC) Interrupt Disable Register */
#define REG_PIOC_IMR                  (*(RoReg*)0xFFFFF648U) /**< \brief (PIOC) Interrupt Mask Register */
#define REG_PIOC_ISR                  (*(RoReg*)0xFFFFF64CU) /**< \brief (PIOC) Interrupt Status Register */
#define REG_PIOC_MDER                 (*(WoReg*)0xFFFFF650U) /**< \brief (PIOC) Multi-driver Enable Register */
#define REG_PIOC_MDDR                 (*(WoReg*)0xFFFFF654U) /**< \brief (PIOC) Multi-driver Disable Register */
#define REG_PIOC_MDSR                 (*(RoReg*)0xFFFFF658U) /**< \brief (PIOC) Multi-driver Status Register */
#define REG_PIOC_PUDR                 (*(WoReg*)0xFFFFF660U) /**< \brief (PIOC) Pull-up Disable Register */
#define REG_PIOC_PUER                 (*(WoReg*)0xFFFFF664U) /**< \brief (PIOC) Pull-up Enable Register */
#define REG_PIOC_PUSR                 (*(RoReg*)0xFFFFF668U) /**< \brief (PIOC) Pad Pull-up Status Register */
#define REG_PIOC_ABCDSR               (*(RwReg*)0xFFFFF670U) /**< \brief (PIOC) Peripheral Select Register */
#define REG_PIOC_IFSCDR               (*(WoReg*)0xFFFFF680U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
#define REG_PIOC_IFSCER               (*(WoReg*)0xFFFFF684U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
#define REG_PIOC_IFSCSR               (*(RoReg*)0xFFFFF688U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
#define REG_PIOC_SCDR                 (*(RwReg*)0xFFFFF68CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
#define REG_PIOC_PPDDR                (*(WoReg*)0xFFFFF690U) /**< \brief (PIOC) Pad Pull-down Disable Register */
#define REG_PIOC_PPDER                (*(WoReg*)0xFFFFF694U) /**< \brief (PIOC) Pad Pull-down Enable Register */
#define REG_PIOC_PPDSR                (*(RoReg*)0xFFFFF698U) /**< \brief (PIOC) Pad Pull-down Status Register */
#define REG_PIOC_OWER                 (*(WoReg*)0xFFFFF6A0U) /**< \brief (PIOC) Output Write Enable */
#define REG_PIOC_OWDR                 (*(WoReg*)0xFFFFF6A4U) /**< \brief (PIOC) Output Write Disable */
#define REG_PIOC_OWSR                 (*(RoReg*)0xFFFFF6A8U) /**< \brief (PIOC) Output Write Status Register */
#define REG_PIOC_AIMER                (*(WoReg*)0xFFFFF6B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
#define REG_PIOC_AIMDR                (*(WoReg*)0xFFFFF6B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
#define REG_PIOC_AIMMR                (*(RoReg*)0xFFFFF6B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
#define REG_PIOC_ESR                  (*(WoReg*)0xFFFFF6C0U) /**< \brief (PIOC) Edge Select Register */
#define REG_PIOC_LSR                  (*(WoReg*)0xFFFFF6C4U) /**< \brief (PIOC) Level Select Register */
#define REG_PIOC_ELSR                 (*(RoReg*)0xFFFFF6C8U) /**< \brief (PIOC) Edge/Level Status Register */
#define REG_PIOC_FELLSR               (*(WoReg*)0xFFFFF6D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
#define REG_PIOC_REHLSR               (*(WoReg*)0xFFFFF6D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
#define REG_PIOC_FRLHSR               (*(RoReg*)0xFFFFF6D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
#define REG_PIOC_LOCKSR               (*(RoReg*)0xFFFFF6E0U) /**< \brief (PIOC) Lock Status */
#define REG_PIOC_WPMR                 (*(RwReg*)0xFFFFF6E4U) /**< \brief (PIOC) Write Protect Mode Register */
#define REG_PIOC_WPSR                 (*(RoReg*)0xFFFFF6E8U) /**< \brief (PIOC) Write Protect Status Register */
#define REG_PIOC_SCHMITT              (*(RwReg*)0xFFFFF700U) /**< \brief (PIOC) Schmitt Trigger Register */
#define REG_PIOC_DRIVER1              (*(RwReg*)0xFFFFF718U) /**< \brief (PIOC) I/O Drive Register 1 */
#define REG_PIOC_DRIVER2              (*(RwReg*)0xFFFFF71CU) /**< \brief (PIOC) I/O Drive Register 2 */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for PIOD peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_PIOD_PER                           (0xFFFFF800U) /**< \brief (PIOD) PIO Enable Register */
#define REG_PIOD_PDR                           (0xFFFFF804U) /**< \brief (PIOD) PIO Disable Register */
#define REG_PIOD_PSR                           (0xFFFFF808U) /**< \brief (PIOD) PIO Status Register */
#define REG_PIOD_OER                           (0xFFFFF810U) /**< \brief (PIOD) Output Enable Register */
#define REG_PIOD_ODR                           (0xFFFFF814U) /**< \brief (PIOD) Output Disable Register */
#define REG_PIOD_OSR                           (0xFFFFF818U) /**< \brief (PIOD) Output Status Register */
#define REG_PIOD_IFER                          (0xFFFFF820U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
#define REG_PIOD_IFDR                          (0xFFFFF824U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
#define REG_PIOD_IFSR                          (0xFFFFF828U) /**< \brief (PIOD) Glitch Input Filter Status Register */
#define REG_PIOD_SODR                          (0xFFFFF830U) /**< \brief (PIOD) Set Output Data Register */
#define REG_PIOD_CODR                          (0xFFFFF834U) /**< \brief (PIOD) Clear Output Data Register */
#define REG_PIOD_ODSR                          (0xFFFFF838U) /**< \brief (PIOD) Output Data Status Register */
#define REG_PIOD_PDSR                          (0xFFFFF83CU) /**< \brief (PIOD) Pin Data Status Register */
#define REG_PIOD_IER                           (0xFFFFF840U) /**< \brief (PIOD) Interrupt Enable Register */
#define REG_PIOD_IDR                           (0xFFFFF844U) /**< \brief (PIOD) Interrupt Disable Register */
#define REG_PIOD_IMR                           (0xFFFFF848U) /**< \brief (PIOD) Interrupt Mask Register */
#define REG_PIOD_ISR                           (0xFFFFF84CU) /**< \brief (PIOD) Interrupt Status Register */
#define REG_PIOD_MDER                          (0xFFFFF850U) /**< \brief (PIOD) Multi-driver Enable Register */
#define REG_PIOD_MDDR                          (0xFFFFF854U) /**< \brief (PIOD) Multi-driver Disable Register */
#define REG_PIOD_MDSR                          (0xFFFFF858U) /**< \brief (PIOD) Multi-driver Status Register */
#define REG_PIOD_PUDR                          (0xFFFFF860U) /**< \brief (PIOD) Pull-up Disable Register */
#define REG_PIOD_PUER                          (0xFFFFF864U) /**< \brief (PIOD) Pull-up Enable Register */
#define REG_PIOD_PUSR                          (0xFFFFF868U) /**< \brief (PIOD) Pad Pull-up Status Register */
#define REG_PIOD_ABCDSR                        (0xFFFFF870U) /**< \brief (PIOD) Peripheral Select Register */
#define REG_PIOD_IFSCDR                        (0xFFFFF880U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */
#define REG_PIOD_IFSCER                        (0xFFFFF884U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */
#define REG_PIOD_IFSCSR                        (0xFFFFF888U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */
#define REG_PIOD_SCDR                          (0xFFFFF88CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
#define REG_PIOD_PPDDR                         (0xFFFFF890U) /**< \brief (PIOD) Pad Pull-down Disable Register */
#define REG_PIOD_PPDER                         (0xFFFFF894U) /**< \brief (PIOD) Pad Pull-down Enable Register */
#define REG_PIOD_PPDSR                         (0xFFFFF898U) /**< \brief (PIOD) Pad Pull-down Status Register */
#define REG_PIOD_OWER                          (0xFFFFF8A0U) /**< \brief (PIOD) Output Write Enable */
#define REG_PIOD_OWDR                          (0xFFFFF8A4U) /**< \brief (PIOD) Output Write Disable */
#define REG_PIOD_OWSR                          (0xFFFFF8A8U) /**< \brief (PIOD) Output Write Status Register */
#define REG_PIOD_AIMER                         (0xFFFFF8B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
#define REG_PIOD_AIMDR                         (0xFFFFF8B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
#define REG_PIOD_AIMMR                         (0xFFFFF8B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
#define REG_PIOD_ESR                           (0xFFFFF8C0U) /**< \brief (PIOD) Edge Select Register */
#define REG_PIOD_LSR                           (0xFFFFF8C4U) /**< \brief (PIOD) Level Select Register */
#define REG_PIOD_ELSR                          (0xFFFFF8C8U) /**< \brief (PIOD) Edge/Level Status Register */
#define REG_PIOD_FELLSR                        (0xFFFFF8D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
#define REG_PIOD_REHLSR                        (0xFFFFF8D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
#define REG_PIOD_FRLHSR                        (0xFFFFF8D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
#define REG_PIOD_LOCKSR                        (0xFFFFF8E0U) /**< \brief (PIOD) Lock Status */
#define REG_PIOD_WPMR                          (0xFFFFF8E4U) /**< \brief (PIOD) Write Protect Mode Register */
#define REG_PIOD_WPSR                          (0xFFFFF8E8U) /**< \brief (PIOD) Write Protect Status Register */
#define REG_PIOD_SCHMITT                       (0xFFFFF900U) /**< \brief (PIOD) Schmitt Trigger Register */
#define REG_PIOD_DRIVER1                       (0xFFFFF918U) /**< \brief (PIOD) I/O Drive Register 1 */
#define REG_PIOD_DRIVER2                       (0xFFFFF91CU) /**< \brief (PIOD) I/O Drive Register 2 */
#else
#define REG_PIOD_PER                  (*(WoReg*)0xFFFFF800U) /**< \brief (PIOD) PIO Enable Register */
#define REG_PIOD_PDR                  (*(WoReg*)0xFFFFF804U) /**< \brief (PIOD) PIO Disable Register */
#define REG_PIOD_PSR                  (*(RoReg*)0xFFFFF808U) /**< \brief (PIOD) PIO Status Register */
#define REG_PIOD_OER                  (*(WoReg*)0xFFFFF810U) /**< \brief (PIOD) Output Enable Register */
#define REG_PIOD_ODR                  (*(WoReg*)0xFFFFF814U) /**< \brief (PIOD) Output Disable Register */
#define REG_PIOD_OSR                  (*(RoReg*)0xFFFFF818U) /**< \brief (PIOD) Output Status Register */
#define REG_PIOD_IFER                 (*(WoReg*)0xFFFFF820U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
#define REG_PIOD_IFDR                 (*(WoReg*)0xFFFFF824U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
#define REG_PIOD_IFSR                 (*(RoReg*)0xFFFFF828U) /**< \brief (PIOD) Glitch Input Filter Status Register */
#define REG_PIOD_SODR                 (*(WoReg*)0xFFFFF830U) /**< \brief (PIOD) Set Output Data Register */
#define REG_PIOD_CODR                 (*(WoReg*)0xFFFFF834U) /**< \brief (PIOD) Clear Output Data Register */
#define REG_PIOD_ODSR                 (*(RwReg*)0xFFFFF838U) /**< \brief (PIOD) Output Data Status Register */
#define REG_PIOD_PDSR                 (*(RoReg*)0xFFFFF83CU) /**< \brief (PIOD) Pin Data Status Register */
#define REG_PIOD_IER                  (*(WoReg*)0xFFFFF840U) /**< \brief (PIOD) Interrupt Enable Register */
#define REG_PIOD_IDR                  (*(WoReg*)0xFFFFF844U) /**< \brief (PIOD) Interrupt Disable Register */
#define REG_PIOD_IMR                  (*(RoReg*)0xFFFFF848U) /**< \brief (PIOD) Interrupt Mask Register */
#define REG_PIOD_ISR                  (*(RoReg*)0xFFFFF84CU) /**< \brief (PIOD) Interrupt Status Register */
#define REG_PIOD_MDER                 (*(WoReg*)0xFFFFF850U) /**< \brief (PIOD) Multi-driver Enable Register */
#define REG_PIOD_MDDR                 (*(WoReg*)0xFFFFF854U) /**< \brief (PIOD) Multi-driver Disable Register */
#define REG_PIOD_MDSR                 (*(RoReg*)0xFFFFF858U) /**< \brief (PIOD) Multi-driver Status Register */
#define REG_PIOD_PUDR                 (*(WoReg*)0xFFFFF860U) /**< \brief (PIOD) Pull-up Disable Register */
#define REG_PIOD_PUER                 (*(WoReg*)0xFFFFF864U) /**< \brief (PIOD) Pull-up Enable Register */
#define REG_PIOD_PUSR                 (*(RoReg*)0xFFFFF868U) /**< \brief (PIOD) Pad Pull-up Status Register */
#define REG_PIOD_ABCDSR               (*(RwReg*)0xFFFFF870U) /**< \brief (PIOD) Peripheral Select Register */
#define REG_PIOD_IFSCDR               (*(WoReg*)0xFFFFF880U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */
#define REG_PIOD_IFSCER               (*(WoReg*)0xFFFFF884U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */
#define REG_PIOD_IFSCSR               (*(RoReg*)0xFFFFF888U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */
#define REG_PIOD_SCDR                 (*(RwReg*)0xFFFFF88CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
#define REG_PIOD_PPDDR                (*(WoReg*)0xFFFFF890U) /**< \brief (PIOD) Pad Pull-down Disable Register */
#define REG_PIOD_PPDER                (*(WoReg*)0xFFFFF894U) /**< \brief (PIOD) Pad Pull-down Enable Register */
#define REG_PIOD_PPDSR                (*(RoReg*)0xFFFFF898U) /**< \brief (PIOD) Pad Pull-down Status Register */
#define REG_PIOD_OWER                 (*(WoReg*)0xFFFFF8A0U) /**< \brief (PIOD) Output Write Enable */
#define REG_PIOD_OWDR                 (*(WoReg*)0xFFFFF8A4U) /**< \brief (PIOD) Output Write Disable */
#define REG_PIOD_OWSR                 (*(RoReg*)0xFFFFF8A8U) /**< \brief (PIOD) Output Write Status Register */
#define REG_PIOD_AIMER                (*(WoReg*)0xFFFFF8B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
#define REG_PIOD_AIMDR                (*(WoReg*)0xFFFFF8B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
#define REG_PIOD_AIMMR                (*(RoReg*)0xFFFFF8B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
#define REG_PIOD_ESR                  (*(WoReg*)0xFFFFF8C0U) /**< \brief (PIOD) Edge Select Register */
#define REG_PIOD_LSR                  (*(WoReg*)0xFFFFF8C4U) /**< \brief (PIOD) Level Select Register */
#define REG_PIOD_ELSR                 (*(RoReg*)0xFFFFF8C8U) /**< \brief (PIOD) Edge/Level Status Register */
#define REG_PIOD_FELLSR               (*(WoReg*)0xFFFFF8D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
#define REG_PIOD_REHLSR               (*(WoReg*)0xFFFFF8D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
#define REG_PIOD_FRLHSR               (*(RoReg*)0xFFFFF8D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
#define REG_PIOD_LOCKSR               (*(RoReg*)0xFFFFF8E0U) /**< \brief (PIOD) Lock Status */
#define REG_PIOD_WPMR                 (*(RwReg*)0xFFFFF8E4U) /**< \brief (PIOD) Write Protect Mode Register */
#define REG_PIOD_WPSR                 (*(RoReg*)0xFFFFF8E8U) /**< \brief (PIOD) Write Protect Status Register */
#define REG_PIOD_SCHMITT              (*(RwReg*)0xFFFFF900U) /**< \brief (PIOD) Schmitt Trigger Register */
#define REG_PIOD_DRIVER1              (*(RwReg*)0xFFFFF918U) /**< \brief (PIOD) I/O Drive Register 1 */
#define REG_PIOD_DRIVER2              (*(RwReg*)0xFFFFF91CU) /**< \brief (PIOD) I/O Drive Register 2 */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for PIOE peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_PIOE_PER                           (0xFFFFFA00U) /**< \brief (PIOE) PIO Enable Register */
#define REG_PIOE_PDR                           (0xFFFFFA04U) /**< \brief (PIOE) PIO Disable Register */
#define REG_PIOE_PSR                           (0xFFFFFA08U) /**< \brief (PIOE) PIO Status Register */
#define REG_PIOE_OER                           (0xFFFFFA10U) /**< \brief (PIOE) Output Enable Register */
#define REG_PIOE_ODR                           (0xFFFFFA14U) /**< \brief (PIOE) Output Disable Register */
#define REG_PIOE_OSR                           (0xFFFFFA18U) /**< \brief (PIOE) Output Status Register */
#define REG_PIOE_IFER                          (0xFFFFFA20U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
#define REG_PIOE_IFDR                          (0xFFFFFA24U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
#define REG_PIOE_IFSR                          (0xFFFFFA28U) /**< \brief (PIOE) Glitch Input Filter Status Register */
#define REG_PIOE_SODR                          (0xFFFFFA30U) /**< \brief (PIOE) Set Output Data Register */
#define REG_PIOE_CODR                          (0xFFFFFA34U) /**< \brief (PIOE) Clear Output Data Register */
#define REG_PIOE_ODSR                          (0xFFFFFA38U) /**< \brief (PIOE) Output Data Status Register */
#define REG_PIOE_PDSR                          (0xFFFFFA3CU) /**< \brief (PIOE) Pin Data Status Register */
#define REG_PIOE_IER                           (0xFFFFFA40U) /**< \brief (PIOE) Interrupt Enable Register */
#define REG_PIOE_IDR                           (0xFFFFFA44U) /**< \brief (PIOE) Interrupt Disable Register */
#define REG_PIOE_IMR                           (0xFFFFFA48U) /**< \brief (PIOE) Interrupt Mask Register */
#define REG_PIOE_ISR                           (0xFFFFFA4CU) /**< \brief (PIOE) Interrupt Status Register */
#define REG_PIOE_MDER                          (0xFFFFFA50U) /**< \brief (PIOE) Multi-driver Enable Register */
#define REG_PIOE_MDDR                          (0xFFFFFA54U) /**< \brief (PIOE) Multi-driver Disable Register */
#define REG_PIOE_MDSR                          (0xFFFFFA58U) /**< \brief (PIOE) Multi-driver Status Register */
#define REG_PIOE_PUDR                          (0xFFFFFA60U) /**< \brief (PIOE) Pull-up Disable Register */
#define REG_PIOE_PUER                          (0xFFFFFA64U) /**< \brief (PIOE) Pull-up Enable Register */
#define REG_PIOE_PUSR                          (0xFFFFFA68U) /**< \brief (PIOE) Pad Pull-up Status Register */
#define REG_PIOE_ABCDSR                        (0xFFFFFA70U) /**< \brief (PIOE) Peripheral Select Register */
#define REG_PIOE_IFSCDR                        (0xFFFFFA80U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */
#define REG_PIOE_IFSCER                        (0xFFFFFA84U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */
#define REG_PIOE_IFSCSR                        (0xFFFFFA88U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */
#define REG_PIOE_SCDR                          (0xFFFFFA8CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
#define REG_PIOE_PPDDR                         (0xFFFFFA90U) /**< \brief (PIOE) Pad Pull-down Disable Register */
#define REG_PIOE_PPDER                         (0xFFFFFA94U) /**< \brief (PIOE) Pad Pull-down Enable Register */
#define REG_PIOE_PPDSR                         (0xFFFFFA98U) /**< \brief (PIOE) Pad Pull-down Status Register */
#define REG_PIOE_OWER                          (0xFFFFFAA0U) /**< \brief (PIOE) Output Write Enable */
#define REG_PIOE_OWDR                          (0xFFFFFAA4U) /**< \brief (PIOE) Output Write Disable */
#define REG_PIOE_OWSR                          (0xFFFFFAA8U) /**< \brief (PIOE) Output Write Status Register */
#define REG_PIOE_AIMER                         (0xFFFFFAB0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
#define REG_PIOE_AIMDR                         (0xFFFFFAB4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
#define REG_PIOE_AIMMR                         (0xFFFFFAB8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
#define REG_PIOE_ESR                           (0xFFFFFAC0U) /**< \brief (PIOE) Edge Select Register */
#define REG_PIOE_LSR                           (0xFFFFFAC4U) /**< \brief (PIOE) Level Select Register */
#define REG_PIOE_ELSR                          (0xFFFFFAC8U) /**< \brief (PIOE) Edge/Level Status Register */
#define REG_PIOE_FELLSR                        (0xFFFFFAD0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
#define REG_PIOE_REHLSR                        (0xFFFFFAD4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
#define REG_PIOE_FRLHSR                        (0xFFFFFAD8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
#define REG_PIOE_LOCKSR                        (0xFFFFFAE0U) /**< \brief (PIOE) Lock Status */
#define REG_PIOE_WPMR                          (0xFFFFFAE4U) /**< \brief (PIOE) Write Protect Mode Register */
#define REG_PIOE_WPSR                          (0xFFFFFAE8U) /**< \brief (PIOE) Write Protect Status Register */
#define REG_PIOE_SCHMITT                       (0xFFFFFB00U) /**< \brief (PIOE) Schmitt Trigger Register */
#define REG_PIOE_DRIVER1                       (0xFFFFFB18U) /**< \brief (PIOE) I/O Drive Register 1 */
#define REG_PIOE_DRIVER2                       (0xFFFFFB1CU) /**< \brief (PIOE) I/O Drive Register 2 */
#else
#define REG_PIOE_PER                  (*(WoReg*)0xFFFFFA00U) /**< \brief (PIOE) PIO Enable Register */
#define REG_PIOE_PDR                  (*(WoReg*)0xFFFFFA04U) /**< \brief (PIOE) PIO Disable Register */
#define REG_PIOE_PSR                  (*(RoReg*)0xFFFFFA08U) /**< \brief (PIOE) PIO Status Register */
#define REG_PIOE_OER                  (*(WoReg*)0xFFFFFA10U) /**< \brief (PIOE) Output Enable Register */
#define REG_PIOE_ODR                  (*(WoReg*)0xFFFFFA14U) /**< \brief (PIOE) Output Disable Register */
#define REG_PIOE_OSR                  (*(RoReg*)0xFFFFFA18U) /**< \brief (PIOE) Output Status Register */
#define REG_PIOE_IFER                 (*(WoReg*)0xFFFFFA20U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
#define REG_PIOE_IFDR                 (*(WoReg*)0xFFFFFA24U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
#define REG_PIOE_IFSR                 (*(RoReg*)0xFFFFFA28U) /**< \brief (PIOE) Glitch Input Filter Status Register */
#define REG_PIOE_SODR                 (*(WoReg*)0xFFFFFA30U) /**< \brief (PIOE) Set Output Data Register */
#define REG_PIOE_CODR                 (*(WoReg*)0xFFFFFA34U) /**< \brief (PIOE) Clear Output Data Register */
#define REG_PIOE_ODSR                 (*(RwReg*)0xFFFFFA38U) /**< \brief (PIOE) Output Data Status Register */
#define REG_PIOE_PDSR                 (*(RoReg*)0xFFFFFA3CU) /**< \brief (PIOE) Pin Data Status Register */
#define REG_PIOE_IER                  (*(WoReg*)0xFFFFFA40U) /**< \brief (PIOE) Interrupt Enable Register */
#define REG_PIOE_IDR                  (*(WoReg*)0xFFFFFA44U) /**< \brief (PIOE) Interrupt Disable Register */
#define REG_PIOE_IMR                  (*(RoReg*)0xFFFFFA48U) /**< \brief (PIOE) Interrupt Mask Register */
#define REG_PIOE_ISR                  (*(RoReg*)0xFFFFFA4CU) /**< \brief (PIOE) Interrupt Status Register */
#define REG_PIOE_MDER                 (*(WoReg*)0xFFFFFA50U) /**< \brief (PIOE) Multi-driver Enable Register */
#define REG_PIOE_MDDR                 (*(WoReg*)0xFFFFFA54U) /**< \brief (PIOE) Multi-driver Disable Register */
#define REG_PIOE_MDSR                 (*(RoReg*)0xFFFFFA58U) /**< \brief (PIOE) Multi-driver Status Register */
#define REG_PIOE_PUDR                 (*(WoReg*)0xFFFFFA60U) /**< \brief (PIOE) Pull-up Disable Register */
#define REG_PIOE_PUER                 (*(WoReg*)0xFFFFFA64U) /**< \brief (PIOE) Pull-up Enable Register */
#define REG_PIOE_PUSR                 (*(RoReg*)0xFFFFFA68U) /**< \brief (PIOE) Pad Pull-up Status Register */
#define REG_PIOE_ABCDSR               (*(RwReg*)0xFFFFFA70U) /**< \brief (PIOE) Peripheral Select Register */
#define REG_PIOE_IFSCDR               (*(WoReg*)0xFFFFFA80U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */
#define REG_PIOE_IFSCER               (*(WoReg*)0xFFFFFA84U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */
#define REG_PIOE_IFSCSR               (*(RoReg*)0xFFFFFA88U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */
#define REG_PIOE_SCDR                 (*(RwReg*)0xFFFFFA8CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
#define REG_PIOE_PPDDR                (*(WoReg*)0xFFFFFA90U) /**< \brief (PIOE) Pad Pull-down Disable Register */
#define REG_PIOE_PPDER                (*(WoReg*)0xFFFFFA94U) /**< \brief (PIOE) Pad Pull-down Enable Register */
#define REG_PIOE_PPDSR                (*(RoReg*)0xFFFFFA98U) /**< \brief (PIOE) Pad Pull-down Status Register */
#define REG_PIOE_OWER                 (*(WoReg*)0xFFFFFAA0U) /**< \brief (PIOE) Output Write Enable */
#define REG_PIOE_OWDR                 (*(WoReg*)0xFFFFFAA4U) /**< \brief (PIOE) Output Write Disable */
#define REG_PIOE_OWSR                 (*(RoReg*)0xFFFFFAA8U) /**< \brief (PIOE) Output Write Status Register */
#define REG_PIOE_AIMER                (*(WoReg*)0xFFFFFAB0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
#define REG_PIOE_AIMDR                (*(WoReg*)0xFFFFFAB4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
#define REG_PIOE_AIMMR                (*(RoReg*)0xFFFFFAB8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
#define REG_PIOE_ESR                  (*(WoReg*)0xFFFFFAC0U) /**< \brief (PIOE) Edge Select Register */
#define REG_PIOE_LSR                  (*(WoReg*)0xFFFFFAC4U) /**< \brief (PIOE) Level Select Register */
#define REG_PIOE_ELSR                 (*(RoReg*)0xFFFFFAC8U) /**< \brief (PIOE) Edge/Level Status Register */
#define REG_PIOE_FELLSR               (*(WoReg*)0xFFFFFAD0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
#define REG_PIOE_REHLSR               (*(WoReg*)0xFFFFFAD4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
#define REG_PIOE_FRLHSR               (*(RoReg*)0xFFFFFAD8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
#define REG_PIOE_LOCKSR               (*(RoReg*)0xFFFFFAE0U) /**< \brief (PIOE) Lock Status */
#define REG_PIOE_WPMR                 (*(RwReg*)0xFFFFFAE4U) /**< \brief (PIOE) Write Protect Mode Register */
#define REG_PIOE_WPSR                 (*(RoReg*)0xFFFFFAE8U) /**< \brief (PIOE) Write Protect Status Register */
#define REG_PIOE_SCHMITT              (*(RwReg*)0xFFFFFB00U) /**< \brief (PIOE) Schmitt Trigger Register */
#define REG_PIOE_DRIVER1              (*(RwReg*)0xFFFFFB18U) /**< \brief (PIOE) I/O Drive Register 1 */
#define REG_PIOE_DRIVER2              (*(RwReg*)0xFFFFFB1CU) /**< \brief (PIOE) I/O Drive Register 2 */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for PMC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_PMC_SCER                           (0xFFFFFC00U) /**< \brief (PMC) System Clock Enable Register */
#define REG_PMC_SCDR                           (0xFFFFFC04U) /**< \brief (PMC) System Clock Disable Register */
#define REG_PMC_SCSR                           (0xFFFFFC08U) /**< \brief (PMC) System Clock Status Register */
#define REG_PMC_PCER0                          (0xFFFFFC10U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
#define REG_PMC_PCDR0                          (0xFFFFFC14U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
#define REG_PMC_PCSR0                          (0xFFFFFC18U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
#define REG_CKGR_UCKR                          (0xFFFFFC1CU) /**< \brief (PMC) UTMI Clock Register */
#define REG_CKGR_MOR                           (0xFFFFFC20U) /**< \brief (PMC) Main Oscillator Register */
#define REG_CKGR_MCFR                          (0xFFFFFC24U) /**< \brief (PMC) Main Clock Frequency Register */
#define REG_CKGR_PLLAR                         (0xFFFFFC28U) /**< \brief (PMC) PLLA Register */
#define REG_PMC_MCKR                           (0xFFFFFC30U) /**< \brief (PMC) Master Clock Register */
#define REG_PMC_USB                            (0xFFFFFC38U) /**< \brief (PMC) USB Clock Register */
#define REG_PMC_SMD                            (0xFFFFFC3CU) /**< \brief (PMC) Soft Modem Clock Register */
#define REG_PMC_PCK                            (0xFFFFFC40U) /**< \brief (PMC) Programmable Clock 0 Register */
#define REG_PMC_IER                            (0xFFFFFC60U) /**< \brief (PMC) Interrupt Enable Register */
#define REG_PMC_IDR                            (0xFFFFFC64U) /**< \brief (PMC) Interrupt Disable Register */
#define REG_PMC_SR                             (0xFFFFFC68U) /**< \brief (PMC) Status Register */
#define REG_PMC_IMR                            (0xFFFFFC6CU) /**< \brief (PMC) Interrupt Mask Register */
#define REG_PMC_PLLICPR                        (0xFFFFFC80U) /**< \brief (PMC) PLL Charge Pump Current Register */
#define REG_PMC_WPMR                           (0xFFFFFCE4U) /**< \brief (PMC) Write Protect Mode Register */
#define REG_PMC_WPSR                           (0xFFFFFCE8U) /**< \brief (PMC) Write Protect Status Register */
#define REG_PMC_PCER1                          (0xFFFFFD00U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
#define REG_PMC_PCDR1                          (0xFFFFFD04U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
#define REG_PMC_PCSR1                          (0xFFFFFD08U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
#define REG_PMC_PCR                            (0xFFFFFD0CU) /**< \brief (PMC) Peripheral Control Register */
#else
#define REG_PMC_SCER                  (*(WoReg*)0xFFFFFC00U) /**< \brief (PMC) System Clock Enable Register */
#define REG_PMC_SCDR                  (*(WoReg*)0xFFFFFC04U) /**< \brief (PMC) System Clock Disable Register */
#define REG_PMC_SCSR                  (*(RoReg*)0xFFFFFC08U) /**< \brief (PMC) System Clock Status Register */
#define REG_PMC_PCER0                 (*(WoReg*)0xFFFFFC10U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
#define REG_PMC_PCDR0                 (*(WoReg*)0xFFFFFC14U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
#define REG_PMC_PCSR0                 (*(RoReg*)0xFFFFFC18U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
#define REG_CKGR_UCKR                 (*(RwReg*)0xFFFFFC1CU) /**< \brief (PMC) UTMI Clock Register */
#define REG_CKGR_MOR                  (*(RwReg*)0xFFFFFC20U) /**< \brief (PMC) Main Oscillator Register */
#define REG_CKGR_MCFR                 (*(RoReg*)0xFFFFFC24U) /**< \brief (PMC) Main Clock Frequency Register */
#define REG_CKGR_PLLAR                (*(RwReg*)0xFFFFFC28U) /**< \brief (PMC) PLLA Register */
#define REG_PMC_MCKR                  (*(RwReg*)0xFFFFFC30U) /**< \brief (PMC) Master Clock Register */
#define REG_PMC_USB                   (*(RwReg*)0xFFFFFC38U) /**< \brief (PMC) USB Clock Register */
#define REG_PMC_SMD                   (*(RwReg*)0xFFFFFC3CU) /**< \brief (PMC) Soft Modem Clock Register */
#define REG_PMC_PCK                   (*(RwReg*)0xFFFFFC40U) /**< \brief (PMC) Programmable Clock 0 Register */
#define REG_PMC_IER                   (*(WoReg*)0xFFFFFC60U) /**< \brief (PMC) Interrupt Enable Register */
#define REG_PMC_IDR                   (*(WoReg*)0xFFFFFC64U) /**< \brief (PMC) Interrupt Disable Register */
#define REG_PMC_SR                    (*(RoReg*)0xFFFFFC68U) /**< \brief (PMC) Status Register */
#define REG_PMC_IMR                   (*(RoReg*)0xFFFFFC6CU) /**< \brief (PMC) Interrupt Mask Register */
#define REG_PMC_PLLICPR               (*(WoReg*)0xFFFFFC80U) /**< \brief (PMC) PLL Charge Pump Current Register */
#define REG_PMC_WPMR                  (*(RwReg*)0xFFFFFCE4U) /**< \brief (PMC) Write Protect Mode Register */
#define REG_PMC_WPSR                  (*(RoReg*)0xFFFFFCE8U) /**< \brief (PMC) Write Protect Status Register */
#define REG_PMC_PCER1                 (*(WoReg*)0xFFFFFD00U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
#define REG_PMC_PCDR1                 (*(WoReg*)0xFFFFFD04U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
#define REG_PMC_PCSR1                 (*(RoReg*)0xFFFFFD08U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
#define REG_PMC_PCR                   (*(RwReg*)0xFFFFFD0CU) /**< \brief (PMC) Peripheral Control Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for RSTC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_RSTC_CR                            (0xFFFFFE00U) /**< \brief (RSTC) Control Register */
#define REG_RSTC_SR                            (0xFFFFFE04U) /**< \brief (RSTC) Status Register */
#define REG_RSTC_MR                            (0xFFFFFE08U) /**< \brief (RSTC) Mode Register */
#else
#define REG_RSTC_CR                   (*(WoReg*)0xFFFFFE00U) /**< \brief (RSTC) Control Register */
#define REG_RSTC_SR                   (*(RoReg*)0xFFFFFE04U) /**< \brief (RSTC) Status Register */
#define REG_RSTC_MR                   (*(RwReg*)0xFFFFFE08U) /**< \brief (RSTC) Mode Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for SHDWC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_SHDWC_CR                           (0xFFFFFE10U) /**< \brief (SHDWC) Shutdown Control Register */
#define REG_SHDWC_MR                           (0xFFFFFE14U) /**< \brief (SHDWC) Shutdown Mode Register */
#define REG_SHDWC_SR                           (0xFFFFFE18U) /**< \brief (SHDWC) Shutdown Status Register */
#else
#define REG_SHDWC_CR                  (*(WoReg*)0xFFFFFE10U) /**< \brief (SHDWC) Shutdown Control Register */
#define REG_SHDWC_MR                  (*(RwReg*)0xFFFFFE14U) /**< \brief (SHDWC) Shutdown Mode Register */
#define REG_SHDWC_SR                  (*(RoReg*)0xFFFFFE18U) /**< \brief (SHDWC) Shutdown Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for PIT peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_PIT_MR                             (0xFFFFFE30U) /**< \brief (PIT) Mode Register */
#define REG_PIT_SR                             (0xFFFFFE34U) /**< \brief (PIT) Status Register */
#define REG_PIT_PIVR                           (0xFFFFFE38U) /**< \brief (PIT) Periodic Interval Value Register */
#define REG_PIT_PIIR                           (0xFFFFFE3CU) /**< \brief (PIT) Periodic Interval Image Register */
#else
#define REG_PIT_MR                    (*(RwReg*)0xFFFFFE30U) /**< \brief (PIT) Mode Register */
#define REG_PIT_SR                    (*(RoReg*)0xFFFFFE34U) /**< \brief (PIT) Status Register */
#define REG_PIT_PIVR                  (*(RoReg*)0xFFFFFE38U) /**< \brief (PIT) Periodic Interval Value Register */
#define REG_PIT_PIIR                  (*(RoReg*)0xFFFFFE3CU) /**< \brief (PIT) Periodic Interval Image Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for WDT peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_WDT_CR                             (0xFFFFFE40U) /**< \brief (WDT) Control Register */
#define REG_WDT_MR                             (0xFFFFFE44U) /**< \brief (WDT) Mode Register */
#define REG_WDT_SR                             (0xFFFFFE48U) /**< \brief (WDT) Status Register */
#else
#define REG_WDT_CR                    (*(WoReg*)0xFFFFFE40U) /**< \brief (WDT) Control Register */
#define REG_WDT_MR                    (*(RwReg*)0xFFFFFE44U) /**< \brief (WDT) Mode Register */
#define REG_WDT_SR                    (*(RoReg*)0xFFFFFE48U) /**< \brief (WDT) Status Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for SCKC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_SCKC_CR                            (0xFFFFFE50U) /**< \brief (SCKC) Slow Clock Configuration Register */
#else
#define REG_SCKC_CR                   (*(RwReg*)0xFFFFFE50U) /**< \brief (SCKC) Slow Clock Configuration Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for BSC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_BSC_CR                             (0xFFFFFE54U) /**< \brief (BSC) Boot Sequence Configuration Register */
#else
#define REG_BSC_CR                    (*(RwReg*)0xFFFFFE54U) /**< \brief (BSC) Boot Sequence Configuration Register */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for GPBR peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_GPBR_GPBR0                         (0xFFFFFE60U) /**< \brief (GPBR) General Purpose Backup Register 0 */
#define REG_GPBR_GPBR1                         (0xFFFFFE64U) /**< \brief (GPBR) General Purpose Backup Register 1 */
#define REG_GPBR_GPBR2                         (0xFFFFFE68U) /**< \brief (GPBR) General Purpose Backup Register 2 */
#define REG_GPBR_GPBR3                         (0xFFFFFE6CU) /**< \brief (GPBR) General Purpose Backup Register 3 */
#else
#define REG_GPBR_GPBR0                (*(RwReg*)0xFFFFFE60U) /**< \brief (GPBR) General Purpose Backup Register 0 */
#define REG_GPBR_GPBR1                (*(RwReg*)0xFFFFFE64U) /**< \brief (GPBR) General Purpose Backup Register 1 */
#define REG_GPBR_GPBR2                (*(RwReg*)0xFFFFFE68U) /**< \brief (GPBR) General Purpose Backup Register 2 */
#define REG_GPBR_GPBR3                (*(RwReg*)0xFFFFFE6CU) /**< \brief (GPBR) General Purpose Backup Register 3 */
#endif /* __ASSEMBLY__ */
/* ========== Register definition for RTC peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_RTC_CR                             (0xFFFFFEB0U) /**< \brief (RTC) Control Register */
#define REG_RTC_MR                             (0xFFFFFEB4U) /**< \brief (RTC) Mode Register */
#define REG_RTC_TIMR                           (0xFFFFFEB8U) /**< \brief (RTC) Time Register */
#define REG_RTC_CALR                           (0xFFFFFEBCU) /**< \brief (RTC) Calendar Register */
#define REG_RTC_TIMALR                         (0xFFFFFEC0U) /**< \brief (RTC) Time Alarm Register */
#define REG_RTC_CALALR                         (0xFFFFFEC4U) /**< \brief (RTC) Calendar Alarm Register */
#define REG_RTC_SR                             (0xFFFFFEC8U) /**< \brief (RTC) Status Register */
#define REG_RTC_SCCR                           (0xFFFFFECCU) /**< \brief (RTC) Status Clear Command Register */
#define REG_RTC_IER                            (0xFFFFFED0U) /**< \brief (RTC) Interrupt Enable Register */
#define REG_RTC_IDR                            (0xFFFFFED4U) /**< \brief (RTC) Interrupt Disable Register */
#define REG_RTC_IMR                            (0xFFFFFED8U) /**< \brief (RTC) Interrupt Mask Register */
#define REG_RTC_VER                            (0xFFFFFEDCU) /**< \brief (RTC) Valid Entry Register */
#else
#define REG_RTC_CR                    (*(RwReg*)0xFFFFFEB0U) /**< \brief (RTC) Control Register */
#define REG_RTC_MR                    (*(RwReg*)0xFFFFFEB4U) /**< \brief (RTC) Mode Register */
#define REG_RTC_TIMR                  (*(RwReg*)0xFFFFFEB8U) /**< \brief (RTC) Time Register */
#define REG_RTC_CALR                  (*(RwReg*)0xFFFFFEBCU) /**< \brief (RTC) Calendar Register */
#define REG_RTC_TIMALR                (*(RwReg*)0xFFFFFEC0U) /**< \brief (RTC) Time Alarm Register */
#define REG_RTC_CALALR                (*(RwReg*)0xFFFFFEC4U) /**< \brief (RTC) Calendar Alarm Register */
#define REG_RTC_SR                    (*(RoReg*)0xFFFFFEC8U) /**< \brief (RTC) Status Register */
#define REG_RTC_SCCR                  (*(WoReg*)0xFFFFFECCU) /**< \brief (RTC) Status Clear Command Register */
#define REG_RTC_IER                   (*(WoReg*)0xFFFFFED0U) /**< \brief (RTC) Interrupt Enable Register */
#define REG_RTC_IDR                   (*(WoReg*)0xFFFFFED4U) /**< \brief (RTC) Interrupt Disable Register */
#define REG_RTC_IMR                   (*(RoReg*)0xFFFFFED8U) /**< \brief (RTC) Interrupt Mask Register */
#define REG_RTC_VER                   (*(RoReg*)0xFFFFFEDCU) /**< \brief (RTC) Valid Entry Register */
#endif /* __ASSEMBLY__ */


/* ========== Register definition for RTT peripheral ========== */
#ifdef __ASSEMBLY__
#define REG_RTT_MR                             (0xFFFFFE20U) /**< \brief (RTT) Mode Register */
#define REG_RTT_AR                             (0xFFFFFE24U) /**< \brief (RTT) Alarm Register */
#define REG_RTT_VR                             (0xFFFFFE28U) /**< \brief (RTT) Value Register */
#define REG_RTT_SR                             (0xFFFFFE2CU) /**< \brief (RTT) Status Register */
#else
#define REG_RTT_MR                             (RwReg, 0xFFFFFE20U) /**< \brief (RTT) Mode Register */
#define REG_RTT_AR                             (RwReg, 0xFFFFFE24U) /**< \brief (RTT) Alarm Register */
#define REG_RTT_VR                             (RoReg, 0xFFFFFE28U) /**< \brief (RTT) Value Register */
#define REG_RTT_SR                             (RoReg, 0xFFFFFE2CU) /**< \brief (RTT) Status Register */
#endif /* __ASSEMBLY__ */

/*@}*/

/* ************************************************************************** */
/*   PERIPHERAL ID DEFINITIONS FOR AT91SAMA5 */
/* ************************************************************************** */
/** \addtogroup AT91SAMA5_id Peripheral Ids Definitions */
/*@{*/

#define ID_FIQ    ( 0) /**< \brief Advanced Interrupt Controller (FIQ) */
#define ID_SYS    ( 1) /**< \brief System Controller Interrupt (SYS) */
#define ID_DBGU   ( 2) /**< \brief Debug Unit Interrupt (DBGU) */
#define ID_PIT    ( 3) /**< \brief Periodic Interval Timer Interrupt (PIT) */
#define ID_WDT    ( 4) /**< \brief Watchdog timer Interrupt (WDT) */
#define ID_SMC    ( 5) /**< \brief Multi-bit ECC Interrupt (SMC) */
#define ID_PIOA   ( 6) /**< \brief Parallel I/O Controller A (PIOA) */
#define ID_PIOB   ( 7) /**< \brief Parallel I/O Controller B (PIOB) */
#define ID_PIOC   ( 8) /**< \brief Parallel I/O Controller C (PIOC) */
#define ID_PIOD   ( 9) /**< \brief Parallel I/O Controller D (PIOD) */
#define ID_PIOE   (10) /**< \brief Parallel I/O Controller E (PIOE) */
#define ID_SMD    (11) /**< \brief SMD Soft Modem (SMD) */
#define ID_USART0 (12) /**< \brief USART 0 (USART0) */
#define ID_USART1 (13) /**< \brief USART 1 (USART1) */
#define ID_USART2 (14) /**< \brief USART 2 (USART2) */
#define ID_USART3 (15) /**< \brief USART 3 (USART3) */
#define ID_UART0  (16) /**< \brief UART 0 (UART0) */
#define ID_UART1  (17) /**< \brief UART 1 (UART1) */
#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
#define ID_TWI2   (20) /**< \brief Two-Wire Interface 2 (TWI2) */
#define ID_HSMCI0 (21) /**< \brief High Speed Multimedia Card Interface 0 (HSMCI0) */
#define ID_HSMCI1 (22) /**< \brief High Speed Multimedia Card Interface 1 (HSMCI1) */
#define ID_HSMCI2 (23) /**< \brief High Speed Multimedia Card Interface 2 (HSMCI2) */
#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface 0 (SPI0) */
#define ID_SPI1   (25) /**< \brief Serial Peripheral Interface 1 (SPI1) */
#define ID_TC0    (26) /**< \brief Timer Counter 0 (ch. 0, 1, 2) (TC0) */
#define ID_TC1    (27) /**< \brief Timer Counter 1 (ch. 3, 4, 5) (TC1) */
#define ID_PWM    (28) /**< \brief Pulse Width Modulation Controller (PWM) */
#define ID_ADC    (29) /**< \brief Touch Screen ADC Controller (ADC) */
#define ID_DMAC0  (30) /**< \brief DMA Controller 0 (DMAC0) */
#define ID_DMAC1  (31) /**< \brief DMA Controller 1 (DMAC1) */
#define ID_UHPHS  (32) /**< \brief USB Host High Speed (UHPHS) */
#define ID_UDPHS  (33) /**< \brief USB Device High Speed (UDPHS) */
#define ID_GMAC   (34) /**< \brief Gigabit Ethernet MAC (GMAC) */
#define ID_EMAC   (35) /**< \brief Ethernet MAC (EMAC) */
#define ID_LCDC   (36) /**< \brief LCD Controller (LCDC) */
#define ID_ISI    (37) /**< \brief Image Sensor Interface (ISI) */
#define ID_SSC0   (38) /**< \brief Synchronous Serial Controller 0 (SSC0) */
#define ID_SSC1   (39) /**< \brief Synchronous Serial Controller 1 (SSC1) */
#define ID_CAN0   (40) /**< \brief CAN controller 0 (CAN0) */
#define ID_CAN1   (41) /**< \brief CAN controller 1 (CAN1) */
#define ID_SHA    (42) /**< \brief Secure Hash Algorithm (SHA) */
#define ID_AES    (43) /**< \brief Advanced Encryption Standard (AES) */
#define ID_TDES   (44) /**< \brief Triple Data EncryptionStandard (TDES) */
#define ID_TRNG   (45) /**< \brief True Random Number Generator (TRNG) */
#define ID_ARM    (46) /**< \brief Performance Monitor Unit (ARM) */
#define ID_IRQ    (47) /**< \brief Advanced Interrupt Controller (IRQ) */
#define ID_FUSE   (48) /**< \brief Fuse Controller (FUSE) */
#define ID_MPDDRC (49) /**< \brief MPDDR controller (MPDDRC) */
/*@}*/

/* ************************************************************************** */
/*   BASE ADDRESS DEFINITIONS FOR AT91SAMA5 */
/* ************************************************************************** */
/** \addtogroup AT91SAMA5_base Peripheral Base Address Definitions */
/*@{*/

#ifdef __ASSEMBLY__
#define SMD    (0x00400000U) /**< \brief (SMD   ) Base Address */
#define AXIMX  (0x00800000U) /**< \brief (AXIMX ) Base Address */
#define HSMCI0 (0xF0000000U) /**< \brief (HSMCI0) Base Address */
#define SPI0   (0xF0004000U) /**< \brief (SPI0  ) Base Address */
#define SSC0   (0xF0008000U) /**< \brief (SSC0  ) Base Address */
#define CAN0   (0xF000C000U) /**< \brief (CAN0  ) Base Address */
#define TC0    (0xF0010000U) /**< \brief (TC0   ) Base Address */
#define TWI0   (0xF0014000U) /**< \brief (TWI0  ) Base Address */
#define TWI1   (0xF0018000U) /**< \brief (TWI1  ) Base Address */
#define USART0 (0xF001C000U) /**< \brief (USART0) Base Address */
#define USART1 (0xF0020000U) /**< \brief (USART1) Base Address */
#define UART0  (0xF0024000U) /**< \brief (UART0 ) Base Address */
#define GMAC   (0xF0028000U) /**< \brief (GMAC  ) Base Address */
#define PWM    (0xF002C000U) /**< \brief (PWM   ) Base Address */
#define LCDC   (0xF0030000U) /**< \brief (LCDC  ) Base Address */
#define ISI    (0xF0034000U) /**< \brief (ISI   ) Base Address */
#define SFR    (0xF0038000U) /**< \brief (SFR   ) Base Address */
#define HSMCI1 (0xF8000000U) /**< \brief (HSMCI1) Base Address */
#define HSMCI2 (0xF8004000U) /**< \brief (HSMCI2) Base Address */
#define SPI1   (0xF8008000U) /**< \brief (SPI1  ) Base Address */
#define SSC1   (0xF800C000U) /**< \brief (SSC1  ) Base Address */
#define CAN1   (0xF8010000U) /**< \brief (CAN1  ) Base Address */
#define TC1    (0xF8014000U) /**< \brief (TC1   ) Base Address */
#define ADC    (0xF8018000U) /**< \brief (ADC   ) Base Address */
#define TWI2   (0xF801C000U) /**< \brief (TWI2  ) Base Address */
#define USART2 (0xF8020000U) /**< \brief (USART2) Base Address */
#define USART3 (0xF8024000U) /**< \brief (USART3) Base Address */
#define UART1  (0xF8028000U) /**< \brief (UART1 ) Base Address */
#define EMAC   (0xF802C000U) /**< \brief (EMAC  ) Base Address */
#define UDPHS  (0xF8030000U) /**< \brief (UDPHS ) Base Address */
#define SHA    (0xF8034000U) /**< \brief (SHA   ) Base Address */
#define AES    (0xF8038000U) /**< \brief (AES   ) Base Address */
#define TDES   (0xF803C000U) /**< \brief (TDES  ) Base Address */
#define TRNG   (0xF8040000U) /**< \brief (TRNG  ) Base Address */
#define SMC    (0xFFFFC000U) /**< \brief (SMC   ) Base Address */
#define FUSE   (0xFFFFE400U) /**< \brief (FUSE  ) Base Address */
#define DMAC0  (0xFFFFE600U) /**< \brief (DMAC0 ) Base Address */
#define DMAC1  (0xFFFFE800U) /**< \brief (DMAC1 ) Base Address */
#define MPDDRC (0xFFFFEA00U) /**< \brief (MPDDRC) Base Address */
#define MATRIX (0xFFFFEC00U) /**< \brief (MATRIX) Base Address */
#define DBGU   (0xFFFFEE00U) /**< \brief (DBGU  ) Base Address */
#define AIC    (0xFFFFF000U) /**< \brief (AIC   ) Base Address */
#define PIOA   (0xFFFFF200U) /**< \brief (PIOA  ) Base Address */
#define PIOB   (0xFFFFF400U) /**< \brief (PIOB  ) Base Address */
#define PIOC   (0xFFFFF600U) /**< \brief (PIOC  ) Base Address */
#define PIOD   (0xFFFFF800U) /**< \brief (PIOD  ) Base Address */
#define PIOE   (0xFFFFFA00U) /**< \brief (PIOE  ) Base Address */
#define PMC    (0xFFFFFC00U) /**< \brief (PMC   ) Base Address */
#define RSTC   (0xFFFFFE00U) /**< \brief (RSTC  ) Base Address */
#define SHDWC  (0xFFFFFE10U) /**< \brief (SHDWC ) Base Address */
//kzhang add RTT definition
#define RTT    (0xFFFFFE20U) /**< \brief (RTT   ) Base Address */
#define PIT    (0xFFFFFE30U) /**< \brief (PIT   ) Base Address */
#define WDT    (0xFFFFFE40U) /**< \brief (WDT   ) Base Address */
#define SCKC   (0xFFFFFE50U) /**< \brief (SCKC  ) Base Address */
#define BSC    (0xFFFFFE54U) /**< \brief (BSC   ) Base Address */
#define GPBR   (0xFFFFFE60U) /**< \brief (GPBR  ) Base Address */
#define RTC    (0xFFFFFEB0U) /**< \brief (RTC   ) Base Address */
#else
#define SMD    ((Smd    *)0x00400000U) /**< \brief (SMD   ) Base Address */
#define AXIMX  ((Aximx  *)0x00800000U) /**< \brief (AXIMX ) Base Address */
#define HSMCI0 ((Hsmci  *)0xF0000000U) /**< \brief (HSMCI0) Base Address */
#define SPI0   ((Spi    *)0xF0004000U) /**< \brief (SPI0  ) Base Address */
#define SSC0   ((Ssc    *)0xF0008000U) /**< \brief (SSC0  ) Base Address */
#define CAN0   ((Can    *)0xF000C000U) /**< \brief (CAN0  ) Base Address */
#define TC0    ((Tc     *)0xF0010000U) /**< \brief (TC0   ) Base Address */
#define TWI0   ((Twi    *)0xF0014000U) /**< \brief (TWI0  ) Base Address */
#define TWI1   ((Twi    *)0xF0018000U) /**< \brief (TWI1  ) Base Address */
#define USART0 ((Usart  *)0xF001C000U) /**< \brief (USART0) Base Address */
#define USART1 ((Usart  *)0xF0020000U) /**< \brief (USART1) Base Address */
#define UART0  ((Uart   *)0xF0024000U) /**< \brief (UART0 ) Base Address */
#define GMAC   ((Gmac   *)0xF0028000U) /**< \brief (GMAC  ) Base Address */
#define PWM    ((Pwm    *)0xF002C000U) /**< \brief (PWM   ) Base Address */
#define LCDC   ((Lcdc   *)0xF0030000U) /**< \brief (LCDC  ) Base Address */
#define ISI    ((Isi    *)0xF0034000U) /**< \brief (ISI   ) Base Address */
#define SFR    ((Sfr    *)0xF0038000U) /**< \brief (SFR   ) Base Address */
#define HSMCI1 ((Hsmci  *)0xF8000000U) /**< \brief (HSMCI1) Base Address */
#define HSMCI2 ((Hsmci  *)0xF8004000U) /**< \brief (HSMCI2) Base Address */
#define SPI1   ((Spi    *)0xF8008000U) /**< \brief (SPI1  ) Base Address */
#define SSC1   ((Ssc    *)0xF800C000U) /**< \brief (SSC1  ) Base Address */
#define CAN1   ((Can    *)0xF8010000U) /**< \brief (CAN1  ) Base Address */
#define TC1    ((Tc     *)0xF8014000U) /**< \brief (TC1   ) Base Address */
#define ADC    ((Adc    *)0xF8018000U) /**< \brief (ADC   ) Base Address */
#define TWI2   ((Twi    *)0xF801C000U) /**< \brief (TWI2  ) Base Address */
#define USART2 ((Usart  *)0xF8020000U) /**< \brief (USART2) Base Address */
#define USART3 ((Usart  *)0xF8024000U) /**< \brief (USART3) Base Address */
#define UART1  ((Uart   *)0xF8028000U) /**< \brief (UART1 ) Base Address */
#define EMAC   ((Emac   *)0xF802C000U) /**< \brief (EMAC  ) Base Address */
#define UDPHS  ((Udphs  *)0xF8030000U) /**< \brief (UDPHS ) Base Address */
#define SHA    ((Sha    *)0xF8034000U) /**< \brief (SHA   ) Base Address */
#define AES    ((Aes    *)0xF8038000U) /**< \brief (AES   ) Base Address */
#define TDES   ((Tdes   *)0xF803C000U) /**< \brief (TDES  ) Base Address */
#define TRNG   ((Trng   *)0xF8040000U) /**< \brief (TRNG  ) Base Address */
#define SMC    ((Smc    *)0xFFFFC000U) /**< \brief (SMC   ) Base Address */
#define FUSE   ((Fuse   *)0xFFFFE400U) /**< \brief (FUSE  ) Base Address */
#define DMAC0  ((Dmac   *)0xFFFFE600U) /**< \brief (DMAC0 ) Base Address */
#define DMAC1  ((Dmac   *)0xFFFFE800U) /**< \brief (DMAC1 ) Base Address */
#define MPDDRC ((Mpddrc *)0xFFFFEA00U) /**< \brief (MPDDRC) Base Address */
#define MATRIX ((Matrix *)0xFFFFEC00U) /**< \brief (MATRIX) Base Address */
#define DBGU   ((Dbgu   *)0xFFFFEE00U) /**< \brief (DBGU  ) Base Address */
#define AIC    ((Aic    *)0xFFFFF000U) /**< \brief (AIC   ) Base Address */
#define PIOA   ((Pio    *)0xFFFFF200U) /**< \brief (PIOA  ) Base Address */
#define PIOB   ((Pio    *)0xFFFFF400U) /**< \brief (PIOB  ) Base Address */
#define PIOC   ((Pio    *)0xFFFFF600U) /**< \brief (PIOC  ) Base Address */
#define PIOD   ((Pio    *)0xFFFFF800U) /**< \brief (PIOD  ) Base Address */
#define PIOE   ((Pio    *)0xFFFFFA00U) /**< \brief (PIOE  ) Base Address */
#define PMC    ((Pmc    *)0xFFFFFC00U) /**< \brief (PMC   ) Base Address */
#define RSTC   ((Rstc   *)0xFFFFFE00U) /**< \brief (RSTC  ) Base Address */
#define SHDWC  ((Shdwc  *)0xFFFFFE10U) /**< \brief (SHDWC ) Base Address */
//kzhang add RTT definition
#define RTT    ((Rtt    *)0xFFFFFE20U) /**< \brief (rtt   ) Base Address */
#define PIT    ((Pit    *)0xFFFFFE30U) /**< \brief (PIT   ) Base Address */
#define WDT    ((Wdt    *)0xFFFFFE40U) /**< \brief (WDT   ) Base Address */
#define SCKC   ((Sckc   *)0xFFFFFE50U) /**< \brief (SCKC  ) Base Address */
#define BSC    ((Bsc    *)0xFFFFFE54U) /**< \brief (BSC   ) Base Address */
#define GPBR   ((Gpbr   *)0xFFFFFE60U) /**< \brief (GPBR  ) Base Address */
#define RTC    ((Rtc    *)0xFFFFFEB0U) /**< \brief (RTC   ) Base Address */
#endif /* __ASSEMBLY__ */
/*@}*/

/* ************************************************************************** */
/*   PIO DEFINITIONS FOR AT91SAMA5 */
/* ************************************************************************** */
/** \addtogroup AT91SAMA5_pio Peripheral Pio Definitions */
/*@{*/

/*@}*/

/* ************************************************************************** */
/*   MEMORY MAPPING DEFINITIONS FOR AT91SAMA5 */
/* ************************************************************************** */

#define IRAM0_SIZE (0x10000u)
#define IRAM1_SIZE (0x10000u)
#define IROM_SIZE  (0x20000u)
#define IRAM_SIZE  (0x20000u)

#define EBI_CS0_ADDR   (0x10000000u) /**< EBI Chip Select 0 base address */
#define DDR_CS_ADDR    (0x20000000u) /**< DDR Chip Select base address */
#define EBI_CS1_ADDR   (0x40000000u) /**< EBI Chip Select 1 base address */
#define EBI_CS2_ADDR   (0x50000000u) /**< EBI Chip Select 2 base address */
#define EBI_CS3_ADDR   (0x60000000u) /**< EBI Chip Select 3 base address */
#define EBI_NF_ADDR    (0x60000000u) /**< NAND Flash on EBI Chip Select 3 base address */
#define IROM_ADDR      (0x00100000u) /**< Internal ROM base address */
#define IRAM0_ADDR     (0x00300000u) /**< Internal RAM 0 base address */
#if defined IRAM0_SIZE
#define IRAM1_ADDR     (IRAM0_ADDR+IRAM0_SIZE) /**< Internal RAM 1 base address */
#endif
#define SMD_ADDR       (0x00400000u) /**< Software Modem Device base address */
#define UDPHS_RAM_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */
#define UHP_OHCI_ADDR  (0x00600000u) /**< USB Host Port OHCI base address */
#define UHP_EHCI_ADDR  (0x00700000u) /**< USB Host Port EHCI base address */
#define AXIMX_ADDR     (0x00800000u) /**< AXI Bus Matrix base address */
#define DAP_ADDR       (0x00900000u) /**< Debug Access Port base address */

/* ************************************************************************** */
/*   ELECTRICAL DEFINITIONS FOR AT91SAMA5 */
/* ************************************************************************** */

/* %ATMEL_ELECTRICAL% */

#ifdef __cplusplus
}
#endif

/*@}*/

#endif /* _AT91SAMA5_ */
